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| author | Rob Herring <rob.herring@linaro.org> | 2014-03-18 13:18:40 -0500 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-03-18 19:38:55 +0000 |
| commit | ce8f0905a59232982c8a220169e11c14c73e7dea (patch) | |
| tree | 821ac781cd68fdd8beca82c136d5ec1e10005f61 /hw/sd/sdhci.c | |
| parent | 22709e90a270a36418f1b1d5d3277016eec1edc2 (diff) | |
| download | hqemu-ce8f0905a59232982c8a220169e11c14c73e7dea.zip hqemu-ce8f0905a59232982c8a220169e11c14c73e7dea.tar.gz | |
pl011: fix UARTRSR accesses corrupting the UARTCR value
Offset 4 is UARTRSR/UARTECR, not the UARTCR. The UARTCR would be
corrupted if the UARTRSR is ever written. Fix by implementing a correct
model of the UARTRSR/UARTECR register. Reads of this register simply
reflect the error bits in data register. Only breaks can be triggered in
QEMU. With the pl011_can_receive function, we effectively have flow
control between the host and the model. Framing and parity errors simply
don't make sense in the model and will never occur.
Signed-off-by: Rob Herring <rob.herring@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1395166721-15716-3-git-send-email-robherring2@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/sd/sdhci.c')
0 files changed, 0 insertions, 0 deletions
