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author | Anthony Liguori <aliguori@us.ibm.com> | 2012-02-17 06:50:07 -0600 |
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committer | Anthony Liguori <aliguori@us.ibm.com> | 2012-02-17 06:50:07 -0600 |
commit | 3d7f5721409d10d33f03891addf67e0984cf319e (patch) | |
tree | afcc78a2eca711fc264772413f375b278ff837cf /hw/realview.c | |
parent | a19255a369f0ef34dfbbc1ed2631e68fbbebb8ce (diff) | |
parent | 13a16f1d91fc7a46b65b22a33f6ffea1b826a097 (diff) | |
download | hqemu-3d7f5721409d10d33f03891addf67e0984cf319e.zip hqemu-3d7f5721409d10d33f03891addf67e0984cf319e.tar.gz |
Merge remote-tracking branch 'pmaydell/arm-devs.for-upstream' into staging
* pmaydell/arm-devs.for-upstream: (22 commits)
hw/pl031: Actually raise interrupt on timer expiry
MAINTAINERS: Add hw/highbank.c maintainer
Remove unnecessary includes of primecell.h
hw/primecell.h: Remove obsolete pl080_init() declaration
hw/arm_sysctl: Drop legacy init function
hw/vexpress.c: Add vexpress-a15 machine
arm_boot: Pass base address of GIC CPU interface, not whole GIC
hw/vexpress.c: Instantiate the motherboard CLCD
hw/vexpress.c: Factor out daughterboard-specific initialization
hw/vexpress.c: Move secondary CPU boot code to SRAM
hw/vexpress.c: Make motherboard peripheral memory map table-driven
hw/a15mpcore.c: Add Cortex-A15 private peripheral model
MAINTAINERS: Add maintainers for Exynos SOC.
Exynos4210: added display controller implementation
hw/exynos4210.c: Add LAN support for SMDKC210.
hw/lan9118: Add basic 16-bit mode support.
ARM: exynos4210: MCT support.
ARM: exynos4210: basic Power Management Unit implementation
ARM: exynos4210: PWM support.
ARM: exynos4210: UART support
...
Diffstat (limited to 'hw/realview.c')
-rw-r--r-- | hw/realview.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/hw/realview.c b/hw/realview.c index bcf982f..ae1bbcd 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -222,21 +222,23 @@ static void realview_init(ram_addr_t ram_size, sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000); if (is_mpcore) { + target_phys_addr_t periphbase; dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_init_nofail(dev); busdev = sysbus_from_qdev(dev); if (is_pb) { - realview_binfo.smp_priv_base = 0x1f000000; + periphbase = 0x1f000000; } else { - realview_binfo.smp_priv_base = 0x10100000; + periphbase = 0x10100000; } - sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base); + sysbus_mmio_map(busdev, 0, periphbase); for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); } - sysbus_create_varargs("l2x0", realview_binfo.smp_priv_base + 0x2000, - NULL); + sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); + /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ + realview_binfo.gic_cpu_if_addr = periphbase + 0x100; } else { uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; /* For now just create the nIRQ GIC, and ignore the others. */ |