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| author | Jan Beulich <JBeulich@suse.com> | 2015-12-09 15:45:29 +0000 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineering.com> | 2019-11-29 19:28:18 -0600 |
| commit | b6b80ce249fc1b3dd4d55c7b9cdd1cc21775a2e7 (patch) | |
| tree | 6659f4339e6cb3a93e85406b6f50a129c1fc76e0 /hw/nvram | |
| parent | d7b5e291ffb166239c44682af2363080c72888aa (diff) | |
| download | hqemu-b6b80ce249fc1b3dd4d55c7b9cdd1cc21775a2e7.zip hqemu-b6b80ce249fc1b3dd4d55c7b9cdd1cc21775a2e7.tar.gz | |
xen/MSI-X: latch MSI-X table writes
The remaining log message in pci_msix_write() is wrong, as there guest
behavior may only appear to be wrong: For one, the old logic didn't
take the mask-all bit into account. And then this shouldn't depend on
host device state (i.e. the host may have masked the entry without the
guest having done so). Plus these writes shouldn't be dropped even when
an entry gets unmasked. Instead, if they can't be made take effect
right away, they should take effect on the next unmasking or enabling
operation - the specification explicitly describes such caching
behavior.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Diffstat (limited to 'hw/nvram')
0 files changed, 0 insertions, 0 deletions
