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| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2014-01-06 10:16:37 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-01-08 19:07:21 +0000 |
| commit | 589bfb6888385ae1767fe2f94528f2dacf59509a (patch) | |
| tree | 5394929d40f7919493a6dc04def85b9d8dffb72a /hw/char | |
| parent | 059ca2bf0d882349aa002e10e3769d25cb923eb4 (diff) | |
| download | hqemu-589bfb6888385ae1767fe2f94528f2dacf59509a.zip hqemu-589bfb6888385ae1767fe2f94528f2dacf59509a.tar.gz | |
char/cadence_uart: Add missing uart_update_state
This should be rechecked on bus write accesses as such accesses may
change the underlying state that generates the interrupt. Particular
relevant for when the guest touches the interrupt status or mask.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1c250cd61b7b8de492fbc8b79b8370958a56d83b.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/char')
| -rw-r--r-- | hw/char/cadence_uart.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index a7b2f21..fb9db89 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -403,6 +403,7 @@ static void uart_write(void *opaque, hwaddr offset, uart_parameters_setup(s); break; } + uart_update_status(s); } static uint64_t uart_read(void *opaque, hwaddr offset, |
