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authorPaul Burton <paul.burton@imgtec.com>2013-06-14 08:30:48 +0100
committerAurelien Jarno <aurelien@aurel32.net>2013-07-28 19:59:23 +0200
commitea0a4f34418c9f2cad9722bb27acd6349148fac0 (patch)
treefbdbd2d798041b199c75fc200c73645d3abba546 /hw/block
parent35c648078aa493c3b976840eb7cf2e53ab5b7a2d (diff)
downloadhqemu-ea0a4f34418c9f2cad9722bb27acd6349148fac0.zip
hqemu-ea0a4f34418c9f2cad9722bb27acd6349148fac0.tar.gz
pflash_cfi01: duplicate status byte from bits 23:16 for 32bit reads
The firmware commonly used with MIPS Malta boards (YAMON) reads the status of the pflash with a 32bit memory access. On real hardware this results in the status byte being mirrored in the upper 16 bits of the read value. For example if the status byte is represented by SS then the hardware reads 0x00SS00SS. The YAMON firmware compares the status against 32bit values expecting the mirrored value and fails without it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'hw/block')
-rw-r--r--hw/block/pflash_cfi01.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index 2bcd731..2973859 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
@@ -192,6 +192,9 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
case 0xe8: /* Write block */
/* Status register read */
ret = pfl->status;
+ if (width > 2) {
+ ret |= pfl->status << 16;
+ }
DPRINTF("%s: status %x\n", __func__, ret);
break;
case 0x90:
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