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authorPeter Maydell <peter.maydell@linaro.org>2012-05-02 16:49:40 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-06-19 13:24:44 +0000
commit306a571a2d75e32cd2eae5486c2714b7b7792a63 (patch)
treea6e1b1e8a6587c808110024b35cc9631162ae4c7 /hw/armv7m_nvic.c
parent2a29ddee82029580fa85276767f73fedc30c8a0a (diff)
downloadhqemu-306a571a2d75e32cd2eae5486c2714b7b7792a63.zip
hqemu-306a571a2d75e32cd2eae5486c2714b7b7792a63.tar.gz
hw/arm_gic: Add qdev property for GIC revision
GIC behaviour can be different between revision 1 and 2 of the architectural GIC specification; we also have to handle the legacy 11MPCore GIC, which is different again in some places. Introduce a qdev property so we can behave appropriately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/armv7m_nvic.c')
-rw-r--r--hw/armv7m_nvic.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index 747e245..4c130f1 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -447,6 +447,8 @@ static int armv7m_nvic_init(SysBusDevice *dev)
/* The NVIC always has only one CPU */
s->gic.num_cpu = 1;
+ /* Tell the common code we're an NVIC */
+ s->gic.revision = 0xffffffff;
gic_init(&s->gic, s->num_irq);
/* The NVIC and system controller register area looks like this:
* 0..0xff : system control registers, including systick
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