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authorPaul Brook <paul@codesourcery.com>2009-11-11 19:59:29 +0000
committerPaul Brook <paul@codesourcery.com>2009-11-11 19:59:29 +0000
commitbe0f204aa0d8743f0627cd3cffb0ffc5bbf962e9 (patch)
tree78f9e202cea9d82873866424040a663537626665 /hw/arm_sysctl.c
parent97fe84f5efbd4f3ded433b7da5daca1f8fd5a82f (diff)
downloadhqemu-be0f204aa0d8743f0627cd3cffb0ffc5bbf962e9.zip
hqemu-be0f204aa0d8743f0627cd3cffb0ffc5bbf962e9.tar.gz
Fix ARM MCore secondary cpu boot
Make MPCore secondary cpu initialization work with the new reset handling. Also change the inital FLAG value from 3 to zero to match recent kenrels. Signed-off-by: Paul Brook <paul@codesourcery.com>
Diffstat (limited to 'hw/arm_sysctl.c')
-rw-r--r--hw/arm_sysctl.c16
1 files changed, 13 insertions, 3 deletions
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index 72c7ccb..856e770 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -27,6 +27,18 @@ typedef struct {
uint32_t resetlevel;
} arm_sysctl_state;
+static void arm_sysctl_reset(DeviceState *d)
+{
+ arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));
+
+ s->leds = 0;
+ s->lockval = 0;
+ s->cfgdata1 = 0;
+ s->cfgdata2 = 0;
+ s->flags = 0;
+ s->resetlevel = 0;
+}
+
static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
@@ -195,9 +207,6 @@ static int arm_sysctl_init1(SysBusDevice *dev)
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
int iomemtype;
- /* The MPcore bootloader uses these flags to start secondary CPUs.
- We don't use a bootloader, so do this here. */
- s->flags = 3;
iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
arm_sysctl_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
@@ -220,6 +229,7 @@ static SysBusDeviceInfo arm_sysctl_info = {
.init = arm_sysctl_init1,
.qdev.name = "realview_sysctl",
.qdev.size = sizeof(arm_sysctl_state),
+ .qdev.reset = arm_sysctl_reset,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
DEFINE_PROP_END_OF_LIST(),
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