diff options
| author | Daniel Sangorrin <dsl@ertl.jp> | 2012-12-11 11:30:38 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-12-11 11:30:38 +0000 |
| commit | f47b48fb678581d6ee369cfe26b3513100b7d53e (patch) | |
| tree | ef033c1a0378a9333b650020b622e6f4d18cc5b9 /hw/arm_gic.c | |
| parent | 79f5d67e9db35d53b478699393590392f7be03ac (diff) | |
| download | hqemu-f47b48fb678581d6ee369cfe26b3513100b7d53e.zip hqemu-f47b48fb678581d6ee369cfe26b3513100b7d53e.tar.gz | |
hw/arm_gic: fix target CPUs affected by set enable/pending ops
Fix a bug on the ARM GIC model where interrupts are not
set pending on the correct target CPUs when they are
triggered by writes to the Interrupt Set Enable or
Set Pending registers.
Signed-off-by: Daniel Sangorrin <dsl@ertl.jp>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm_gic.c')
| -rw-r--r-- | hw/arm_gic.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 672d539..8d769de 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -374,7 +374,8 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, value = 0xff; for (i = 0; i < 8; i++) { if (value & (1 << i)) { - int mask = (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq); + int mask = + (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; if (!GIC_TEST_ENABLED(irq + i, cm)) { @@ -417,7 +418,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, for (i = 0; i < 8; i++) { if (value & (1 << i)) { - GIC_SET_PENDING(irq + i, GIC_TARGET(irq)); + GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); } } } else if (offset < 0x300) { |
