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| author | Fabian Aggeler <aggelerf@ethz.ch> | 2014-06-19 18:06:24 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-06-19 18:06:24 +0100 |
| commit | e389be1673052b538534643165111725a79e5afd (patch) | |
| tree | fbbc10c005058fbba47a8f5c62e9e5caa48751c7 /hw/arm/spitz.c | |
| parent | 6baa963f4dcc211801608ebe1e0482b51653350c (diff) | |
| download | hqemu-e389be1673052b538534643165111725a79e5afd.zip hqemu-e389be1673052b538534643165111725a79e5afd.tar.gz | |
target-arm: implement PD0/PD1 bits for TTBCR
Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions).
Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and
get_level1_table_address.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Message-id: 1402409556-18574-1-git-send-email-aggelerf@ethz.ch
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/spitz.c')
0 files changed, 0 insertions, 0 deletions
