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| author | Leon Alrae <leon.alrae@imgtec.com> | 2014-06-27 08:49:03 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-10-13 12:38:24 +0100 |
| commit | bf7910c6b1bc47517a9d7a6049d97d056e014eb0 (patch) | |
| tree | e78c66baf97b61ac6540dbb2dd90aa580d5b8777 /cpus.c | |
| parent | fac5a0733013f4e148b406056526f2208464d799 (diff) | |
| download | hqemu-bf7910c6b1bc47517a9d7a6049d97d056e014eb0.zip hqemu-bf7910c6b1bc47517a9d7a6049d97d056e014eb0.tar.gz | |
target-mips: move PREF, CACHE, LLD and SCD instructions
The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6.
Additionally, the hint codes in PREF instruction greater than or
equal to 24 generate Reserved Instruction Exception.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'cpus.c')
0 files changed, 0 insertions, 0 deletions
