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authorDavid Gibson <david@gibson.dropbear.id.au>2016-02-09 09:28:43 +1000
committerTimothy Pearson <tpearson@raptorengineering.com>2019-11-29 19:45:29 -0600
commitf76fccbb94269c63f5e151394b961cbaa8539d3c (patch)
tree2270ea03ac5b433ace9b6f91c95cf2a8190e6d99
parent677ed3f6fac37cc14995c521bf1806508dd1a7f4 (diff)
downloadhqemu-f76fccbb94269c63f5e151394b961cbaa8539d3c.zip
hqemu-f76fccbb94269c63f5e151394b961cbaa8539d3c.tar.gz
target-ppc: Include missing MMU models for SDR1 in info registers
The HMP command "info registers" produces somewhat different information on different ppc cpu variants. For those with a hash MMU it's supposed to include the SDR1, DAR and DSISR registers related to the MMU. However, the switch is missing a couple of MMU model variants, meaning we will miss out this information on certain CPUs which should have it. This patch corrects the oversight. (Really these MMU model IDs need a big cleanup, but we might as well fix the bug in the interim). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
-rw-r--r--target-ppc/translate.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 62cf0e4..5955cd2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11360,7 +11360,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
case POWERPC_MMU_64B:
case POWERPC_MMU_2_03:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_07:
+ case POWERPC_MMU_2_07a:
#endif
cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
" DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
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