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author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-25 07:42:14 +0000 |
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committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-25 07:42:14 +0000 |
commit | c19148bd8f5c2800265372d3554035efde1c5517 (patch) | |
tree | 48865e441f51604f9df6268a38b82063cf75eba1 | |
parent | e7d05e6f1d39b913a15911c35a857965e696fa65 (diff) | |
download | hqemu-c19148bd8f5c2800265372d3554035efde1c5517.zip hqemu-c19148bd8f5c2800265372d3554035efde1c5517.tar.gz |
Make MAXTL dynamic, bounds check tl when indexing
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4942 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r-- | target-sparc/cpu.h | 8 | ||||
-rw-r--r-- | target-sparc/helper.c | 85 | ||||
-rw-r--r-- | target-sparc/machine.c | 10 | ||||
-rw-r--r-- | target-sparc/op_helper.c | 4 |
4 files changed, 56 insertions, 51 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index ab04f38..2574690 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -252,13 +252,15 @@ typedef struct CPUSPARCState { float128 qt0, qt1; float_status fp_status; #if defined(TARGET_SPARC64) -#define MAXTL 4 +#define MAXTL_MAX 8 +#define MAXTL_MASK (MAXTL_MAX - 1) trap_state *tsptr; - trap_state ts[MAXTL]; + trap_state ts[MAXTL_MAX]; uint32_t xcc; /* Extended integer condition codes */ uint32_t asi; uint32_t pstate; uint32_t tl; + uint32_t maxtl; uint32_t cansave, canrestore, otherwin, wstate, cleanwin; uint64_t agregs[8]; /* alternate general registers */ uint64_t bgregs[8]; /* backup for normal global registers */ @@ -270,7 +272,7 @@ typedef struct CPUSPARCState { uint64_t gsr; uint32_t gl; // UA2005 /* UA 2005 hyperprivileged registers */ - uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr; + uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; void *hstick; // UA 2005 #endif uint32_t features; diff --git a/target-sparc/helper.c b/target-sparc/helper.c index 85b9d5c..811de01 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -48,6 +48,7 @@ struct sparc_def_t { uint32_t mmu_trcr_mask; uint32_t features; uint32_t nwindows; + uint32_t maxtl; }; static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); @@ -738,20 +739,20 @@ void do_interrupt(CPUState *env) } #endif #if !defined(CONFIG_USER_ONLY) - if (env->tl == MAXTL) { - cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", - env->exception_index); + if (env->tl >= env->maxtl) { + cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," + " Error state", env->exception_index, env->tl, env->maxtl); return; } #endif - if (env->tl < MAXTL - 1) { + if (env->tl < env->maxtl - 1) { env->tl++; } else { env->pstate |= PS_RED; - if (env->tl != MAXTL) + if (env->tl < env->maxtl) env->tl++; } - env->tsptr = &env->ts[env->tl]; + env->tsptr = &env->ts[env->tl & MAXTL_MASK]; env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | GET_CWP64(env); @@ -918,7 +919,7 @@ void cpu_reset(CPUSPARCState *env) env->pstate = PS_PRIV; env->hpstate = HS_PRIV; env->pc = 0x1fff0000020ULL; // XXX should be different for system_reset - env->tsptr = &env->ts[env->tl]; + env->tsptr = &env->ts[env->tl & MAXTL_MASK]; #else env->pc = 0; env->mmuregs[0] &= ~(MMU_E | MMU_NF); @@ -950,6 +951,8 @@ static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) cpu_sparc_set_id(env, 0); #else env->mmu_version = def->mmu_version; + env->maxtl = def->maxtl; + env->version |= def->maxtl << 8; env->version |= def->nwindows - 1; #endif return 0; @@ -991,159 +994,159 @@ static const sparc_def_t sparc_defs[] = { #ifdef TARGET_SPARC64 { .name = "Fujitsu Sparc64", - .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_12, .nwindows = 4, + .maxtl = 4, .features = CPU_DEFAULT_FEATURES, }, { .name = "Fujitsu Sparc64 III", - .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_12, .nwindows = 5, + .maxtl = 4, .features = CPU_DEFAULT_FEATURES, }, { .name = "Fujitsu Sparc64 IV", - .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_12, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES, }, { .name = "Fujitsu Sparc64 V", - .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_12, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES, }, { .name = "TI UltraSparc I", - .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_12, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES, }, { .name = "TI UltraSparc II", - .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_12, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES, }, { .name = "TI UltraSparc IIi", - .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_12, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES, }, { .name = "TI UltraSparc IIe", - .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_12, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES, }, { .name = "Sun UltraSparc III", - .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_12, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES, }, { .name = "Sun UltraSparc III Cu", - .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_3, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES, }, { .name = "Sun UltraSparc IIIi", - .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_12, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES, }, { .name = "Sun UltraSparc IV", - .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_4, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES, }, { .name = "Sun UltraSparc IV+", - .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_12, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, }, { .name = "Sun UltraSparc IIIi+", - .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_3, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES, }, { .name = "Sun UltraSparc T1", // defined in sparc_ifu_fdp.v and ctu.h - .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_sun4v, .nwindows = 8, + .maxtl = 6, .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT | CPU_FEATURE_GL, }, { .name = "Sun UltraSparc T2", // defined in tlu_asi_ctl.v and n2_revid_cust.v - .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_sun4v, .nwindows = 8, + .maxtl = 6, .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT | CPU_FEATURE_GL, }, { .name = "NEC UltraSparc I", - .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) - | (MAXTL << 8)), + .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), .fpu_version = 0x00000000, .mmu_version = mmu_us_12, .nwindows = 8, + .maxtl = 5, .features = CPU_DEFAULT_FEATURES, }, #else diff --git a/target-sparc/machine.c b/target-sparc/machine.c index 5d4d2eb..f5a0017 100644 --- a/target-sparc/machine.c +++ b/target-sparc/machine.c @@ -72,7 +72,7 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be64s(f, &env->dtlb_tte[i]); } qemu_put_be32s(f, &env->mmu_version); - for (i = 0; i < MAXTL; i++) { + for (i = 0; i < MAXTL_MAX; i++) { qemu_put_be64s(f, &env->ts[i].tpc); qemu_put_be64s(f, &env->ts[i].tnpc); qemu_put_be64s(f, &env->ts[i].tstate); @@ -103,7 +103,7 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be64s(f, &env->gsr); qemu_put_be32s(f, &env->gl); qemu_put_be64s(f, &env->hpstate); - for (i = 0; i < MAXTL; i++) + for (i = 0; i < MAXTL_MAX; i++) qemu_put_be64s(f, &env->htstate[i]); qemu_put_be64s(f, &env->hintp); qemu_put_be64s(f, &env->htba); @@ -165,7 +165,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) qemu_get_be64s(f, &env->dtlb_tte[i]); } qemu_get_be32s(f, &env->mmu_version); - for (i = 0; i < MAXTL; i++) { + for (i = 0; i < MAXTL_MAX; i++) { qemu_get_be64s(f, &env->ts[i].tpc); qemu_get_be64s(f, &env->ts[i].tnpc); qemu_get_be64s(f, &env->ts[i].tstate); @@ -175,7 +175,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) qemu_get_be32s(f, &env->asi); qemu_get_be32s(f, &env->pstate); qemu_get_be32s(f, &env->tl); - env->tsptr = &env->ts[env->tl]; + env->tsptr = &env->ts[env->tl & MAXTL_MASK]; qemu_get_be32s(f, &env->cansave); qemu_get_be32s(f, &env->canrestore); qemu_get_be32s(f, &env->otherwin); @@ -197,7 +197,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) qemu_get_be64s(f, &env->gsr); qemu_get_be32s(f, &env->gl); qemu_get_be64s(f, &env->hpstate); - for (i = 0; i < MAXTL; i++) + for (i = 0; i < MAXTL_MAX; i++) qemu_get_be64s(f, &env->htstate[i]); qemu_get_be64s(f, &env->hintp); qemu_get_be64s(f, &env->htba); diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 73d960b..40cdf6e 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -2742,7 +2742,7 @@ void helper_done(void) change_pstate((env->tsptr->tstate >> 8) & 0xf3f); PUT_CWP64(env, env->tsptr->tstate & 0xff); env->tl--; - env->tsptr = &env->ts[env->tl]; + env->tsptr = &env->ts[env->tl & MAXTL_MASK]; } void helper_retry(void) @@ -2754,7 +2754,7 @@ void helper_retry(void) change_pstate((env->tsptr->tstate >> 8) & 0xf3f); PUT_CWP64(env, env->tsptr->tstate & 0xff); env->tl--; - env->tsptr = &env->ts[env->tl]; + env->tsptr = &env->ts[env->tl & MAXTL_MASK]; } #endif |