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authorPaolo Bonzini <pbonzini@redhat.com>2015-10-12 18:25:40 +0200
committerEduardo Habkost <ehabkost@redhat.com>2015-10-23 12:59:26 -0200
commitdd75d4fcb4a82c34d4f466e7fc166162b71ff740 (patch)
tree9dd273335081ee3baf67de725a9a7d9efbe7b47e
parent147482ae35b896808af68c0051ad86d3aae12979 (diff)
downloadhqemu-dd75d4fcb4a82c34d4f466e7fc166162b71ff740.zip
hqemu-dd75d4fcb4a82c34d4f466e7fc166162b71ff740.tar.gz
target-i386: allow any alignment for SMBASE
Processors up to the Pentium (says Bochs---I do not have old enough manuals) require a 32KiB alignment for the SMBASE, but newer processors do not need that, and Tiano Core will use non-aligned SMBASE values. Reported-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
-rw-r--r--target-i386/smm_helper.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 02e24b9..c272a98 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -266,7 +266,7 @@ void helper_rsm(CPUX86State *env)
val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) {
- env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00) & ~0x7fff;
+ env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00);
}
#else
cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
@@ -319,7 +319,7 @@ void helper_rsm(CPUX86State *env)
val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) {
- env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8) & ~0x7fff;
+ env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8);
}
#endif
if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {
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