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| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2013-12-17 19:42:29 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-12-17 19:42:29 +0000 |
| commit | c25771281ea17c2a09c86ac6a74672f2ec297f8d (patch) | |
| tree | 3d1c7379343b478d7859c6e570d6fd092d76db72 | |
| parent | d8bbdcf8d6cb71735014dbd22baf274aea46066f (diff) | |
| download | hqemu-c25771281ea17c2a09c86ac6a74672f2ec297f8d.zip hqemu-c25771281ea17c2a09c86ac6a74672f2ec297f8d.tar.gz | |
arm/xilinx_zynq: Implement CBAR initialisation
Fix the CBAR initialisation by using the newly defined static property.
Zynq will now correctly init the CBAR to the SCU base address.
Needed to boot Linux on the xilinx_zynq machine model.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 8db7d57ebe5418fed397fcc86ea719f98446c178.1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/arm/xilinx_zynq.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 1c954a3..17251c7 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -36,6 +36,8 @@ #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ +#define MPCORE_PERIPHBASE 0xF8F00000 + static const int dma_irqs[8] = { 46, 47, 48, 49, 72, 73, 74, 75 }; @@ -122,6 +124,11 @@ static void zynq_init(QEMUMachineInitArgs *args) cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); + object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", &err); + if (err) { + error_report("%s", error_get_pretty(err)); + exit(1); + } object_property_set_bool(OBJECT(cpu), true, "realized", &err); if (err) { error_report("%s", error_get_pretty(err)); @@ -160,7 +167,7 @@ static void zynq_init(QEMUMachineInitArgs *args) qdev_prop_set_uint32(dev, "num-cpu", 1); qdev_init_nofail(dev); busdev = SYS_BUS_DEVICE(dev); - sysbus_mmio_map(busdev, 0, 0xF8F00000); + sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); |
