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author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-23 08:47:26 +0000 |
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committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-23 08:47:26 +0000 |
commit | 8fa211e881ff386f8555c113b409aa3373dca7e1 (patch) | |
tree | 05c46b1f8f2d1822fa0457a2e37bf2ae239db1e4 | |
parent | 69dd5c9ffd5c0c6a01ad14b9c6a8d7135ccc2b9a (diff) | |
download | hqemu-8fa211e881ff386f8555c113b409aa3373dca7e1.zip hqemu-8fa211e881ff386f8555c113b409aa3373dca7e1.tar.gz |
Implement tick interrupt disable bits
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6122 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r-- | hw/sun4u.c | 29 | ||||
-rw-r--r-- | target-sparc/cpu.h | 3 |
2 files changed, 22 insertions, 10 deletions
@@ -57,6 +57,9 @@ #define MAX_PILS 16 +#define TICK_INT_DIS 0x8000000000000000ULL +#define TICK_MAX 0x7fffffffffffffffULL + struct hwdef { const char * const default_cpu_model; uint16_t machine_id; @@ -269,11 +272,14 @@ static void main_cpu_reset(void *opaque) CPUState *env = s->env; cpu_reset(env); - ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1); + env->tick_cmpr = TICK_INT_DIS | 0; + ptimer_set_limit(env->tick, TICK_MAX, 1); ptimer_run(env->tick, 0); - ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1); + env->stick_cmpr = TICK_INT_DIS | 0; + ptimer_set_limit(env->stick, TICK_MAX, 1); ptimer_run(env->stick, 0); - ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1); + env->hstick_cmpr = TICK_INT_DIS | 0; + ptimer_set_limit(env->hstick, TICK_MAX, 1); ptimer_run(env->hstick, 0); env->gregs[1] = 0; // Memory start env->gregs[2] = ram_size; // Memory size @@ -286,24 +292,29 @@ static void tick_irq(void *opaque) { CPUState *env = opaque; - env->softint |= SOFTINT_TIMER; - cpu_interrupt(env, CPU_INTERRUPT_TIMER); + if (!(env->tick_cmpr & TICK_INT_DIS)) { + env->softint |= SOFTINT_TIMER; + cpu_interrupt(env, CPU_INTERRUPT_TIMER); + } } static void stick_irq(void *opaque) { CPUState *env = opaque; - env->softint |= SOFTINT_TIMER; - cpu_interrupt(env, CPU_INTERRUPT_TIMER); + if (!(env->stick_cmpr & TICK_INT_DIS)) { + env->softint |= SOFTINT_STIMER; + cpu_interrupt(env, CPU_INTERRUPT_TIMER); + } } static void hstick_irq(void *opaque) { CPUState *env = opaque; - env->softint |= SOFTINT_TIMER; - cpu_interrupt(env, CPU_INTERRUPT_TIMER); + if (!(env->hstick_cmpr & TICK_INT_DIS)) { + cpu_interrupt(env, CPU_INTERRUPT_TIMER); + } } void cpu_tick_set_count(void *opaque, uint64_t count) diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 93c1be5..905cf16 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -330,7 +330,8 @@ typedef struct CPUSPARCState { uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; void *hstick; // UA 2005 uint32_t softint; -#define SOFTINT_TIMER 1 +#define SOFTINT_TIMER 1 +#define SOFTINT_STIMER (1 << 16) #endif sparc_def_t *def; } CPUSPARCState; |