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| author | Tom Musta <tommusta@gmail.com> | 2014-12-18 10:34:31 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2015-01-07 16:16:27 +0100 |
| commit | 69d1a9377453d78ba2279fa56ae9623b3cd98673 (patch) | |
| tree | 3ee55988add9762fc51e3504e352b0f703b32f2d | |
| parent | e43668a7d20e5d2dfe92b2f3426280b2a351333c (diff) | |
| download | hqemu-69d1a9377453d78ba2279fa56ae9623b3cd98673.zip hqemu-69d1a9377453d78ba2279fa56ae9623b3cd98673.tar.gz | |
target-ppc: Introduce tm_enabled Bit to CPU State
Add a bit (tm_enabled) to CPU state that mirrors the MSR[TM] bit.
This is analogous to the other "available" bits in the MSR (FP,
VSX, etc.).
NOTE: Since MSR[TM] occupies big-endian bit 31, the code is wrapped
with a PPC64 bit check.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | target-ppc/translate.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index a772382..3b004f3 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -203,6 +203,7 @@ typedef struct DisasContext { int altivec_enabled; int vsx_enabled; int spe_enabled; + int tm_enabled; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint64_t insns_flags; @@ -11342,6 +11343,13 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, } else { ctx.vsx_enabled = 0; } +#if defined(TARGET_PPC64) + if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { + ctx.tm_enabled = msr_tm; + } else { + ctx.tm_enabled = 0; + } +#endif if ((env->flags & POWERPC_FLAG_SE) && msr_se) ctx.singlestep_enabled = CPU_SINGLE_STEP; else |
