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author | Michael S. Tsirkin <mst@redhat.com> | 2009-11-25 16:31:42 +0200 |
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committer | Michael S. Tsirkin <mst@redhat.com> | 2009-12-07 21:50:53 +0200 |
commit | b6981cb57be5d66b1b7cf9009a122fb3cdd4b96b (patch) | |
tree | ab6baa03077255ac9138ec1909f701108496d85e | |
parent | f9bf77dd1f838b0061172fe41709b221956da2f5 (diff) | |
download | hqemu-b6981cb57be5d66b1b7cf9009a122fb3cdd4b96b.zip hqemu-b6981cb57be5d66b1b7cf9009a122fb3cdd4b96b.tar.gz |
pci: interrupt disable bit support
Interrupt disable bit is mandatory in PCI spec.
Implement it to make devices spec compliant.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Isaku Yamahata <yamahata@valinux.co.jp>
-rw-r--r-- | hw/pci.c | 29 | ||||
-rw-r--r-- | hw/pci.h | 1 |
2 files changed, 28 insertions, 2 deletions
@@ -518,7 +518,8 @@ static void pci_init_wmask(PCIDevice *dev) dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; dev->wmask[PCI_INTERRUPT_LINE] = 0xff; pci_set_word(dev->wmask + PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | + PCI_COMMAND_INTX_DISABLE); memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, config_size - PCI_CONFIG_HEADER_SIZE); @@ -938,6 +939,25 @@ static void pci_update_mappings(PCIDevice *d) } } +static inline int pci_irq_disabled(PCIDevice *d) +{ + return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; +} + +/* Called after interrupt disabled field update in config space, + * assert/deassert interrupts if necessary. + * Gets original interrupt disable bit value (before update). */ +static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) +{ + int i, disabled = pci_irq_disabled(d); + if (disabled == was_irq_disabled) + return; + for (i = 0; i < PCI_NUM_PINS; ++i) { + int state = pci_irq_state(d, i); + pci_change_irq_level(d, i, disabled ? -state : state); + } +} + uint32_t pci_default_read_config(PCIDevice *d, uint32_t address, int len) { @@ -950,7 +970,7 @@ uint32_t pci_default_read_config(PCIDevice *d, void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) { - int i; + int i, was_irq_disabled = pci_irq_disabled(d); uint32_t config_size = pci_config_size(d); for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) { @@ -962,6 +982,9 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || range_covers_byte(addr, l, PCI_COMMAND)) pci_update_mappings(d); + + if (range_covers_byte(addr, l, PCI_COMMAND)) + pci_update_irq_disabled(d, was_irq_disabled); } /***********************************************************/ @@ -979,6 +1002,8 @@ static void pci_set_irq(void *opaque, int irq_num, int level) pci_set_irq_state(pci_dev, irq_num, level); pci_update_irq_status(pci_dev); + if (pci_irq_disabled(pci_dev)) + return; pci_change_irq_level(pci_dev, irq_num, change); } @@ -101,6 +101,7 @@ typedef struct PCIIORegion { #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ #define PCI_COMMAND_MASTER 0x4 /* Enable bus master */ +#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ #define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS_INTERRUPT 0x08 #define PCI_REVISION_ID 0x08 /* 8 bits */ |