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author | Andre Przywara <andre.przywara@calxeda.com> | 2013-07-05 14:21:37 +0200 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2013-07-15 16:25:57 +0100 |
commit | b25a83f0538fceede15cba6cfd6ea0f1ffc9d777 (patch) | |
tree | 14b755ae56e53b4f0a371ae8708c1e2e65f449fb | |
parent | 574f66bcbe10cd8fbf8bbf6d87451a944ae421bd (diff) | |
download | hqemu-b25a83f0538fceede15cba6cfd6ea0f1ffc9d777.zip hqemu-b25a83f0538fceede15cba6cfd6ea0f1ffc9d777.tar.gz |
ARM/highbank: add support for Calxeda ECX-2000 / Midway
The Calxeda ECX-2000 chip (aka. Midway) is model-wise quite similar
to the Highbank. The most prominent difference is the Cortex-A15 CPU
core in it, together with the associated core peripherals.
Add a new ARM machine type called "midway".
Move the L2 cache controller device into the Highbank specific part,
since Midway does not have (and need) it.
Signed-off-by: Andre Przywara <andre.przywara@calxeda.com>
Message-id: 1373026897-12085-3-git-send-email-andre.przywara@calxeda.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | hw/arm/highbank.c | 32 |
1 files changed, 27 insertions, 5 deletions
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index b8a7dd4..be264d3 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -185,6 +185,7 @@ static struct arm_boot_info highbank_binfo; enum cxmachines { CALXEDA_HIGHBANK, + CALXEDA_MIDWAY, }; /* ram_size must be set to match the upper bound of memory in the @@ -216,6 +217,9 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine) case CALXEDA_HIGHBANK: cpu_model = "cortex-a9"; break; + case CALXEDA_MIDWAY: + cpu_model = "cortex-a15"; + break; } } @@ -256,8 +260,16 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine) switch (machine) { case CALXEDA_HIGHBANK: + dev = qdev_create(NULL, "l2x0"); + qdev_init_nofail(dev); + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, 0xfff12000); + dev = qdev_create(NULL, "a9mpcore_priv"); break; + case CALXEDA_MIDWAY: + dev = qdev_create(NULL, "a15mpcore_priv"); + break; } qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); @@ -272,11 +284,6 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine) pic[n] = qdev_get_gpio_in(dev, n); } - dev = qdev_create(NULL, "l2x0"); - qdev_init_nofail(dev); - busdev = SYS_BUS_DEVICE(dev); - sysbus_mmio_map(busdev, 0, 0xfff12000); - dev = qdev_create(NULL, "sp804"); qdev_prop_set_uint32(dev, "freq0", 150000000); qdev_prop_set_uint32(dev, "freq1", 150000000); @@ -341,6 +348,11 @@ static void highbank_init(QEMUMachineInitArgs *args) calxeda_init(args, CALXEDA_HIGHBANK); } +static void midway_init(QEMUMachineInitArgs *args) +{ + calxeda_init(args, CALXEDA_MIDWAY); +} + static QEMUMachine highbank_machine = { .name = "highbank", .desc = "Calxeda Highbank (ECX-1000)", @@ -350,9 +362,19 @@ static QEMUMachine highbank_machine = { DEFAULT_MACHINE_OPTIONS, }; +static QEMUMachine midway_machine = { + .name = "midway", + .desc = "Calxeda Midway (ECX-2000)", + .init = midway_init, + .block_default_type = IF_SCSI, + .max_cpus = 4, + DEFAULT_MACHINE_OPTIONS, +}; + static void calxeda_machines_init(void) { qemu_register_machine(&highbank_machine); + qemu_register_machine(&midway_machine); } machine_init(calxeda_machines_init); |