| Commit message (Collapse) | Author | Age | Files | Lines |
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include the automatic erase present in other chip drivers
Since the majority is definitely auto-erase, change the remaining
explicit-erase cases to be auto-erase as well.
Corresponding to flashrom svn r673.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carlos Arnau Perez <cemede@gmail.com>
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Serprog compilation is now controlled by a Makefile variable.
Replace munmap with physunmap where appropriate.
Corresponding to flashrom svn r671.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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If we only send an opcode and no additional data/address, the SPI controller
will read one byte too few from the chip. Basically, the last byte of the chip
response is discarded and will not end up in the FIFO. It is unclear if the
CS# line is set high too early as well. That hardware bug is undocumented as
of now, but I'm working with AMD to add a detailed description of it to the
errata. Add loads of additional debugging to SB600/SB700 init. Add explanatory
comments for unintuitive code flow. Thanks go to Uwe for testing quite a few
iterations of the patch. Kill the SB600 flash chip status register special
case, which was a somewhat misguided workaround for that hardware erratum.
Note for future added features in the SB600 SPI driver: It may be possible to
read up to 15 bytes of command response with overlapping reads due to the ring
buffer design of the FIFO if the command can be repeated without ill effects.
Same for skipping up to 7 bytes between command and response.
Corresponding to flashrom svn r661.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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Some drivers support only a few combinations of read/write length and return
error otherwise. Having a distinct return code for this error means we can
handle it in upper layers.
Corresponding to flashrom svn r653.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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Tested it on Epia-m700 worked okay.
Tested-by: Jakob Bornecrantz <wallbraker@gmail.com>
Corresponding to flashrom svn r651.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jakob Bornecrantz <wallbraker@gmail.com>
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Some SPI opcodes need to be sent in direct succession after each other
without any chip deselect happening in between. A prominent example is
WREN (Write Enable) directly before PP (Page Program). Intel calls the
first opcode in such a row "preopcode".
Right now, we ignore the direct succession requirement completely and it
works pretty well because most onboard SPI masters have a timing or
heuristics which make the problem disappear.
The FT2232 SPI flasher is different. Since it is an external flasher,
timing is very different to what we can expect from onboard flashers and
this leads to failure at slow speeds.
This patch allows any function to submit multiple SPI commands in a
stream to any flasher. Support in the individual flashers isn't
implemented yet, so there is one generic function which passes the each
command in the stream one-by-one to the command functions of the
selected SPI flash driver.
Tested-by: Jakob Bornecrantz <wallbraker@gmail.com>
Corresponding to flashrom svn r645.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jakob Bornecrantz <wallbraker@gmail.com>
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Make a few local functions in sb600spi.c static.
Corresponding to flashrom svn r623.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
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single chip supported by flashrom
That means you can tell flashrom to read exactly bytes 12345-56789 (start
12345, length 44445) and it will not fetch a single byte more. Uwe tested
this on one LPC, one SPI, and one parallel flash board.
Corresponding to flashrom svn r596.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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And even when it checks if the erase worked, the result of that check is
often ignored.
Convert all erase functions and actually check return codes
almost everywhere.
Check inside all erase_* routines if erase worked, not outside.
erase_sector_jedec and erase_block_jedec have changed prototypes to
enable erase checking.
Uwe successfully tested LPC on an CK804 box and SPI on some SB600 box.
Corresponding to flashrom svn r595.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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This was partly due to a design problem in the abstraction layer.
There should be exactly two different functions for reading SPI chips:
- memory mapped reads
- SPI command reads.
Each of them should be contained in a separate function, optionally
taking parameters where needed.
This patch solves the problems mentioned above, shortens the code and
makes the code logic a lot more obvious.
Since open-coding the min() function leads to errors, include it in this
patch as well.
Corresponding to flashrom svn r589.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
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Right now, the annotation only differentiates between SPI and non-SPI. Anyone
who knows more about a specific flash chip should feel free to update it.
The existing flashbus variable was abused to denote the SPI controller type.
Use an aptly named variable for that purpose. Once this patch is merged,
the chipset/programmer init functions can set supported flash chip types
and flashrom can automatically select only matching probe/read/erase/write
functions. A side benefit of that will be the elimination of the Winbond
W29EE011 vs. AMIC A49LF040A conflict.
Corresponding to flashrom svn r556.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Some MMIO accesses used volatile, others didn't (and risked non-execution
of side effects) and even with volatile, some accesses looked dubious.
Since the MMIO accessor functions and the onboard flash accessor functions
are functionally identical (but have different signatures), make the flash
accessors wrappers for the MMIO accessors. For some of the conversions,
I used Coccinelle. Semantic patch follows: @@ typedef uint8_t; expression a;
volatile uint8_t *b; @@ - b[a] + *(b + a) @@ expression a; volatile uint8_t *b;
@@ - *(b) |= (a); + *(b) = *(b) | (a); @@ expression a; volatile uint8_t *b;
@@ - *(b) = (a); + mmio_writeb(a, b); @@ volatile uint8_t *b; @@ - *(b)
+ mmio_readb(b) @@ type T; T b; @@ ( mmio_readb | mmio_writeb ) (..., - (T)
- (b) + b ) Uwe tested read, write, erase with this patch on a random board
to make sure nothing breaks.
Corresponding to flashrom svn r524.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Build-tested on 32bit x86.
Corresponding to flashrom svn r521.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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AAI mode
Change SPI architecture to handle 1-byte chunk chip writing differently from
256-byte chunk chip writing. Annotate SPI chip write functions with _256
or _1 suffix denoting the number of bytes they write at maximum. The 1-byte
chunk writing is cut-n-pasted to different SPI drivers right now. A later
patch can move them to the generic spi_chip_write_1.
Corresponding to flashrom svn r485.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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should handle such special opcode failure gracefully on ICH and
Compatible chipsets. This fixes chip erase on almost all ICH+VIA SPI masters.
Thanks to Ali Nadalizadeh for helping track down this bug!
Corresponding to flashrom svn r484.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Add missing copyright year.
Corresponding to flashrom svn r428 and coreboot v2 svn r4107.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Reviewed-by: Joe, Bao <Zheng.Bao@amd.com>
Corresponding to flashrom svn r354 and coreboot v2 svn r3782.
Signed-off-by: Jason Wang <Qingpei.wang@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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This has been tested by Uwe Hermann on an RS690/SB600 board.
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Corresponding to flashrom svn r351 and coreboot v2 svn r3779.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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