| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
| |
Still fallout of adding "-Wshadow". Missed the ht1000 one
(chipset_enable is not compied on Windows where we had the collision
with "byte" last time) and the other occurrence is newly introduced.
Old libpci defines a global symbol called "byte" too.
Corresponding to flashrom svn r913.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Set supported buses based on ISA bridge reg 0x8a
- Use MCP55 chipset enable only if LPC is detected
- Allow LPC on MCP61
- Eliminate duplicated code where possible
Corresponding to flashrom svn r906.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Huge thanks to Michael Karcher for reverse engineering the MCP67 chipset
and writing a spec. Due to this, we were able to use the chinese wall
technique for 100% clean room reverse engineering. This patch doesn't touch
any of the new registers, it only reads them. Assuming that read has no side
effects, this patch is a no-op and safe. We need "flashrom -V" output from
all post-MCP55 (nForce 5) chipset boards. Please indicate if your board
uses SPI flash or LPC flash (if you know it). Note: That output is only
helpful if it is created with patched flashrom and if is from the first run
of flashrom after a cold boot (reset or Ctrl-Alt-Del is not sufficient).
There is a pattern based on which we can probably detect which flash type
is present on the board. Thanks to Alessandro Polverini for testing earlier
iterations of this patch. Note: The MCP67 should work. I guessed that the other
recent Nvidia chipsets would work in a similar way, and created a simplified
do-nothing catchall chipset enable function which dumps some info and instructs
the user to send more info.
Corresponding to flashrom svn r902.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Public chipset documentation available at
http://www.intel.com/Assets/PDF/datasheet/322896.pdf
Tested on NM10-based customer reference board from Intel.
Corresponding to flashrom svn r866.
Signed-off-by: David Hendricks <dhendrix@google.com>
Acked-by: Sean Nelson <audiohacked@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
|
|
|
|
|
|
|
|
|
| |
Some mingw declares a global identifier "byte", causing -Werror -Wshadow
to break compilation. This patch renames all identifiers called "byte".
Corresponding to flashrom svn r861.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
|
|
|
|
|
|
|
|
|
|
| |
Also remove separate sis 5596 routine: superio code will be handled
separately, which then turns this routine into the sis 5511 chipset
enable.
Corresponding to flashrom svn r859.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
|
|
|
|
|
|
|
|
| |
Fixes wrong detection of area decoded to the FWH interfaces.
Corresponding to flashrom svn r826.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
|
|
|
|
|
| |
Binary file (standard input) matches
Corresponding to flashrom svn r820.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Only done for VT8237R (possibly needed for VT8237 too), VT8235 does
not need this (even if the original bios does so: Asus A7V8X-MX SE,
MSI KT4V were verified).
This then opens a floodgate of cleanups in the board enables.
* EPIA SP board enable vanishes, taking EPIA CN match with it.
* Asus A7V8X-MX/Tyan S2498 board enable then equals
w836xx_memw_enable_2e
* AOpen vKM400Am-S board enable then equals it8705_rom_write_enable
* Epia M board enable becomes via_vt823x_gpio15_raise
* Epia N board enable becomes via_vt823x_gpio9_raise
* Asus M2V-MX board enable becomes via_vt823x_gpio5_raise
* vt823x_gpio_set becomes via_vt823x_gpio_set, and now detects ISA
bridge itself, in concordance with intel ich and nvidia mcp gpio.
Corresponding to flashrom svn r815.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Sean Nelson <audiohacked@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
|
|
|
|
|
|
| |
Corresponding to flashrom svn r809.
Signed-off-by: Adam Jurkowski <adam.jurkowski@kontron.pl>
Acked-by: Luc Verhaegen <libv@skynet.be>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Detect max FWH size for Intel
631xESB/632xESB/3100/ICH6/ICH7/ICH8/ICH9/ICH10.
- Move IDSEL override before decode size checking for the chipsets
listed above or flashrom will complain based on old values.
- Adjust supported flash buses for the chipsets listed above (none of
them supports LPC or Parallel).
- Detect max parallel size for AMD/National Semiconductor CS5530.
- Adjust supported flash buses for CS5530/CS5530A.
- Set board-specific max decode size for Elitegroup K7VTA3.
- Set board-specific max decode size for Shuttle AK38N.
Corresponding to flashrom svn r806.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Make various pieces of code conditional on support for internal programming.
Code shared between PCI device programmers and onboard programming is now
conditional as well. It is now possible to build only with dummy support:
make CONFIG_INTERNAL=no CONFIG_NIC3COM=no CONFIG_SATASII=no CONFIG_DRKAISER=no
CONFIG_SERPROG=no CONFIG_FT2232SPI=no This allows building for a specific use
case only, and it also facilitates porting to a new architecture because it
is possible to focus on highlevel code only. Note: Either internal or dummy
programmer needs to be compiled in due to the current behaviour of always
picking a default programmer if -p is not specified. Picking an arbitrary
external programmer as default wouldn't make sense. Build and runtime tested
in all 1024 possible build combinations. The only failures are by design
as mentioned above.
Corresponding to flashrom svn r797.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Sean Nelson <audiohacked@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
SiS630 chipset enable is equal to sis540 plus superio "poking".
Superio poking equals IT8705F flash write enable, which is currently
dealt with on a board by board basis in board_enable.c. Not all
630 and newer based boards come with it8705/sis950 superios.
Corresponding to flashrom svn r794.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Sean Nelson <audiohacked@gmail.com>
|
|
|
|
|
|
|
| |
Corresponding to flashrom svn r793.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Found in Intel document 322170 (Intel 5 Series Chipset and Intel 3400
Series Chipset Specification Update).
According to http://pciids.sourceforge.net/ we probably should match all
IDs from 0x3b00-0x3b1f, but so far I didn't find an Intel doc saying the
same.
If anybody has contacts at Intel and can check, I'd be happy to add the
rest of the IDs.
Corresponding to flashrom svn r784.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Sean Nelson <audiohacked@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Mark SiS 735 as supported.
Remove "SiS" from the model number to avoid printing it twice.
Reported by Adrian Glaubitz.
Corresponding to flashrom svn r760.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The two existing SiS chipset enables (compared to the 28 in this patch)
were refactored, and one of them was fixed.
A function to match PCI vendor/class combinations was added to generic
code.
Tested on the "Elitegroup K7S5A". Results are somewhat unexpected (some
PCI settings seem to be inaccessible, but it still works).
This is not based on any docs, but rather on detailed analysis
of existing opensource code for some of the chipsets.
Thanks to for Adrian Glaubitz testing.
Corresponding to flashrom svn r759.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
decode size for chipsets and tested mainboards
The rationale is to warn users when they, for example, try to flash a 512KB
parallel flash chip but their chipset only supports 256KB, or they try to flash
512KB and the chipset _does_ theoretically support 512KB but their special
board doesn't wire all address lines and thus supports only 256 KB ROM chips
at maximum. This has cost Uwe hours of debugging on some board already, until
he figured out what was going on. We should try warn our users where possible
about this. The chipset and the chip may have more than one bus in common
(e.g. SB600 and Pm49* can both speak LPC+FWH) and on SB600/SB7x0/SB8x0 there
are different limits for LPC and FWH. The only way to tell the user about
the exact circumstances is to spew error messages per bus. The code will
issue a warning during probe (which does fail for some chips if the size
is too big) and abort before the first real read/write/erase action. If no
action is specified, the warning is printed anyway. That way, a user can find
out why probe might not have worked, and will be stopped before he/she gets
incorrect results. Add a bitcount function to the infrastructure.
Corresponding to flashrom svn r755.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
| |
Oops.
Corresponding to flashrom svn r747.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
|
|
|
|
|
|
|
|
|
|
| |
Add pciids for the new isa bridge, and hook it to the nforce2
chipset enable.
Corresponding to flashrom svn r744.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Martin Szulecki <opensuse@sukimashita.com>
|
|
|
|
|
|
|
|
|
| |
This is successfully tested by me on the Elitegroup P6VAP-A+ board.
Corresponding to flashrom svn r732.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
|
|
|
| |
On the Wyse Winterm S50 lspci doesn`t show the cs5536 hostbridge and so
flashrom doesn`t detect the cs5536.
This patch is adding the cs5536 isa id [1022:2090] for chip detect.
Corresponding to flashrom svn r729.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
|
|
|
|
|
|
| |
Corresponding to flashrom svn r706.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
didn't recognize her ICH9 LPC controller on the Green City
Intel Customer Reference Board with ICH9 + Tylersburg Chipset. According to
http://pci-ids.ucw.cz/read/PC/8086/2910 the ID 0x8086/0x2910 was used for
engineering samples. No intel doc mentions this ID at all.
Corresponding to flashrom svn r696.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Anne Le Coq <annyvonne.le_coq@alcatel-lucent.fr>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Usage:
flashrom -p internal=fwh_idsel=0
Log:
flashrom v0.9.0-r670
coreboot table found at 0xcf7f3c00.
Vendor ID: KONTRON, part ID: 986LCD-M
Found chipset "Intel ICH7/ICH7R", enabling flash write...
Setting IDSEL=0 for top 8 MBOK.
This chipset supports the following protocols: LPC,FWH.
Disabling flash write protection for board "Kontron 986LCD-M"... OK.
Calibrating delay loop... OK.
Found chip "SST SST49LF016C" (2048 KB, FWH) at physical address
0xffe00000.
No operations were specified.
Corresponding to flashrom svn r685.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Chris Kinney <cmkinne@sandia.gov>
|
|
|
|
|
|
|
| |
Corresponding to flashrom svn r677.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
|
|
|
|
|
|
| |
Corresponding to flashrom svn r676.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
to the debug output
This can help debug cases where the BIOS does not set up a correct flash
decode for the given flash size. The Intel docs state that the decode applies
to FWH and SPI flash.
Corresponding to flashrom svn r675.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Chris Kinney <cmkinne@sandia.gov>
|
|
|
|
|
|
|
|
|
|
| |
Serprog compilation is now controlled by a Makefile variable.
Replace munmap with physunmap where appropriate.
Corresponding to flashrom svn r671.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
If we only send an opcode and no additional data/address, the SPI controller
will read one byte too few from the chip. Basically, the last byte of the chip
response is discarded and will not end up in the FIFO. It is unclear if the
CS# line is set high too early as well. That hardware bug is undocumented as
of now, but I'm working with AMD to add a detailed description of it to the
errata. Add loads of additional debugging to SB600/SB700 init. Add explanatory
comments for unintuitive code flow. Thanks go to Uwe for testing quite a few
iterations of the patch. Kill the SB600 flash chip status register special
case, which was a somewhat misguided workaround for that hardware erratum.
Note for future added features in the SB600 SPI driver: It may be possible to
read up to 15 bytes of command response with overlapping reads due to the ring
buffer design of the FIFO if the command can be repeated without ill effects.
Same for skipping up to 7 bytes between command and response.
Corresponding to flashrom svn r661.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Properly escape '-' chars in manpage.
- Fix typo in chipset_enable.c.
- Drop useless 'return' in chip_readn().
- Random other whitespace or cosmetic fixes.
Corresponding to flashrom svn r636.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
| |
Corresponding to flashrom svn r635.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
| |
Corresponding to flashrom svn r603.
Signed-off-by: Mateusz Murawski <matowy@tlen.pl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
|
|
|
|
|
|
|
|
| |
Drop no longer needed MAX macro, we have a max() function.
Corresponding to flashrom svn r601.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
| |
Also, list how many chips/chipsets/boards we support in 'flashrom -L'.
Corresponding to flashrom svn r599.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
|
|
|
|
|
|
|
|
|
| |
the VX800 PCI ID
Corresponding to flashrom svn r591.
Signed-off-by: Arjan Koers <0h3q2rmn2bdb@list.nospam.xutrox.com>
Acked-by: Bari Ari <bari@onelabs.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
|
|
| |
this in the last commit
Also do some random cleanups while I'm at it.
Corresponding to flashrom svn r567.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
It doesn't make sense to probe for SPI chips on a LPC host, nor does it
make sense to probe for LPC chips on a Parallel host.
This change is backwards compatible, but adding host protocol info to
chipset init functions will speed up probing.
Once all chipset init functions are updated and the Winbond W29EE011 and
AMIC A49LF040A chip definitions are updated, the W29EE011 workaround can
be deleted as the W29/A49 conflict magically disappears.
Tested on real hardware and
Corresponding to flashrom svn r560.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Right now, the annotation only differentiates between SPI and non-SPI. Anyone
who knows more about a specific flash chip should feel free to update it.
The existing flashbus variable was abused to denote the SPI controller type.
Use an aptly named variable for that purpose. Once this patch is merged,
the chipset/programmer init functions can set supported flash chip types
and flashrom can automatically select only matching probe/read/erase/write
functions. A side benefit of that will be the elimination of the Winbond
W29EE011 vs. AMIC A49LF040A conflict.
Corresponding to flashrom svn r556.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
While the other chipset enables for nvidia could potentially also work,
this one, by not touching other bits, seems like the safest solution.
Uwe tested this on his Asus A7N8X Deluxe, so hopefully the A7N8X-E
(reporter unknown) is now no longer an issue.
Corresponding to flashrom svn r548.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Update manpage, we now report supported boards via -L. - Add some missing
escaping for '-' characters in the manpage. - Shorten some of the really
long device names, so that -L output looks nicer. - Display a "table header"
for all entries/columns in -L output. - Make -L output tabular for all lists
for better readability. - Do not print "unknown XXXX SPI chip" entries in
-L output. - And random other cosmetics...
Corresponding to flashrom svn r543.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Some MMIO accesses used volatile, others didn't (and risked non-execution
of side effects) and even with volatile, some accesses looked dubious.
Since the MMIO accessor functions and the onboard flash accessor functions
are functionally identical (but have different signatures), make the flash
accessors wrappers for the MMIO accessors. For some of the conversions,
I used Coccinelle. Semantic patch follows: @@ typedef uint8_t; expression a;
volatile uint8_t *b; @@ - b[a] + *(b + a) @@ expression a; volatile uint8_t *b;
@@ - *(b) |= (a); + *(b) = *(b) | (a); @@ expression a; volatile uint8_t *b;
@@ - *(b) = (a); + mmio_writeb(a, b); @@ volatile uint8_t *b; @@ - *(b)
+ mmio_readb(b) @@ type T; T b; @@ ( mmio_readb | mmio_writeb ) (..., - (T)
- (b) + b ) Uwe tested read, write, erase with this patch on a random board
to make sure nothing breaks.
Corresponding to flashrom svn r524.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Supported out of the box (no flash enables required)
- Verifiably not yet working (unknown flash enable)
Also, move some structs to flash.h in preparation for later wiki
output support.
Corresponding to flashrom svn r523.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
| |
Build-tested on 32bit x86.
Corresponding to flashrom svn r521.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
|
|
| |
It seems some boards do not use SPI_HOLD at all. Take that into account when
trying to figure out if SPI is available. Print the SB600 ROM strap override
register status for better debugging.
Corresponding to flashrom svn r516.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
I know that the data sheets say we can't read the ROM straps, but
creative interpretation of the data sheets yielded a heuristic which
should work pretty well.
NOTE: If you test this, make sure you power down and _unplug_ the
machine for a few minutes before you boot and run flashrom with this
patch.
If the machine is not unplugged for some time, the test will yield
incorrect results.
If you run a slightly older flashrom version than svn HEAD, the test
will yield incorrect results.
If you run any flashrom version (except svn HEAD plus this patch) after
poweron, the test will yield incorrect results.
Explanation:
Older flashrom versions unconditionally write to registers which are
used for this heuristic. These registers are in the S5 power domain, so
even powering down does not clear them, you really have to unplug the
machine and remove the battery if this is a laptop.
Corresponding to flashrom svn r491.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
|
|
|
|
|
|
|
| |
Corresponding to flashrom svn r477.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
|
|
|
|
|
|
|
|
|
|
|
|
| |
The list of tested chipsets is synced from the wiki.
Also, split the chipset vendor and name into two fields for easier
wiki-syntax output later.
Corresponding to flashrom svn r472.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
|
|
|
|
|
|
| |
Corresponding to flashrom svn r469.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
|
|
|
|
|
|
|
|
|
| |
If unprotect succeeded, it will print "SB600 unprotect failed".
Corresponding to flashrom svn r467.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|