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* Increase flashrom release number to 0.9.30.9.3Carl-Daniel Hailfinger2010-10-081-1/+1
| | | | | | | Corresponding to flashrom svn r1204. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* CONFIG_BITBANG_SPI was not selected if CONFIG_NICINTEL_SPI was on by defaultCarl-Daniel Hailfinger2010-10-086-24/+41
| | | | | | | | | | | | | Wiki output was missing all flash chips if CONFIG_INTERNAL was not selected. Use correct type for toupper()/tolower()/isspace() functions. Specify software requirements in a generic way. Non-x86 compilation does not work with the default programmer set, so list the make parameters which result in a working build. Corresponding to flashrom svn r1203. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* A lot of messages sent to flashrom@flashrom.org just have "flashrom -V" as ↵Paul Menzel2010-10-084-11/+22
| | | | | | | | | | | | the subject Ask people to include more information in the subject line to make life easier for developers/supporters. Corresponding to flashrom svn r1202. Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* SPI write status register (WRSR) may take longer than 100 ms, and it makes ↵Carl-Daniel Hailfinger2010-10-082-4/+39
| | | | | | | | | | | sense to poll for completion in 10 ms steps until 5 s are over This patch complements r1115. Corresponding to flashrom svn r1201. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Joshua Roys <roysjosh@gmail.com>
* List the devices for all supported programmers in "flashrom -L" outputCarl-Daniel Hailfinger2010-10-073-30/+40
| | | | | | | | | | | Fix PCI device ID printing. Remove personal e-mail addresses from the man page, point people to flashrom@flashrom.org instead. Corresponding to flashrom svn r1200. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Flashrom -L output did not contain a list of programmers nor were all ↵Carl-Daniel Hailfinger2010-10-067-55/+111
| | | | | | | | | | | | programmers listed Fix it and mention at least the name of each programmer. Wiki output is unchanged, and will need separate fixups. Corresponding to flashrom svn r1199. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* The Direct I/O library for Mac OS X is now called DirectHW to make sure ↵Carl-Daniel Hailfinger2010-10-064-3/+5
| | | | | | | | | | | | people can find it via an internet search DirectIO was a generic name for a concept and thus not a good distinguisher for a library. Corresponding to flashrom svn r1198. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Idwer Vollering <vidwer@gmail.com>
* Update the author list in the man pageCarl-Daniel Hailfinger2010-10-062-4/+34
| | | | | | | | | Update programmer parameter documentation. Corresponding to flashrom svn r1197. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Remove duplicate includes from the codeStefan Reinauer2010-10-0616-19/+0
| | | | | | | Corresponding to flashrom svn r1196. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* DJGPP: Avoid leaking memory on lowmem mapping errorCarl-Daniel Hailfinger2010-10-051-1/+5
| | | | | | | | | Add a clarifying comment about why low memory is never unmapped. Corresponding to flashrom svn r1195. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Rudolf Marek <r.marek@assembler.cz>
* Use AAI write for SST SST25VF032BHelge Wagner2010-10-053-5/+20
| | | | | | | | | | | | Speedup from 228 to 113 seconds. Use page (256 byte) write for SST SST25VF064C. Speedup from 3091 to 123 seconds. Corresponding to flashrom svn r1194. Signed-off-by: Helge Wagner <helge.wagner@ge.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Implement on-the-fly reprogramming of the ICH SPI OPCODE tableHelge Wagner2010-10-051-20/+79
| | | | | | | Corresponding to flashrom svn r1193. Signed-off-by: Helge Wagner <helge.wagner@ge.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add a board-enable for the ASRock K7S41, chipset-enable for SiS 741Uwe Hermann2010-10-053-0/+4
| | | | | | | | | | | | | | This also adds (and marks as tested) a chipset-enable for the SiS 741. All operations successfully tested on hardware. lspci/superiotool: http://www.flashrom.org/pipermail/flashrom/2010-September/004710.html Corresponding to flashrom svn r1192. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add board enable for Dell OptiPlex GX1 and mark Intel 28F002BC/BL/BV/BX-T as ↵Mattias Mattsson2010-10-053-1/+12
| | | | | | | | | | | | | | | | | | | | tested Match on ethernet and north bridge. This is tested on an OptiPlex GX1 400L+ but will probably work for the whole GX1 series as they all share the same vendor BIOS. lspci/flashrom output http://www.flashrom.org/pipermail/flashrom/2010-July/004042.html lspci output (OptiPlex GX1 unknown model) http://www.coreboot.org/pipermail/coreboot/2010-May/058040.html superiotool output (OptiPlex GX1 266L+) http://www.flashrom.org/pipermail/flashrom/2009-July/000207.html lspci/dmidecode output (OptiPlex GX1 266L+) http://www.coreboot.org/pipermail/coreboot/2009-July/050958.html Corresponding to flashrom svn r1191. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Quickfix for broken writes on FT2232H based programmersUwe Hermann2010-10-051-1/+1
| | | | | | | | | | | | | Not sure if this is the final/correct fix, but for now it definately fixes writes on FT2232H hardware. I have tested this on both, the DLP Design DLP-USB1232H, and the openbiosprog-spi hardware. Thanks to Joshua Roys <roysjosh@gmail.com> for the hint on IRC. Corresponding to flashrom svn r1190. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Make sure all chip variants are present in .name strings in flashchips.cMattias Mattsson2010-10-052-30/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Strip package prefix in constant names (everything before "28F"). Prefix every constant name with INTEL_ Sort intel chip constants by ID. Rename the following constants to their "canonical" name: P28F400BT (0x70 -> INTEL_28F400T (28F400BV/BX/CE/CV-T) P28F400BB (0x71) -> INTEL_28F400B (28F400BV/BX/CE/CV-B) P28F004BT (0x78) -> INTEL_28F004T (28F004B5/BE/BV/BX-T) P28F004BB (0x79) -> INTEL_28F004B (28F004B5/BE/BV/BX-B) E_28F008S5 (0xA6) -> INTEL_28F008S3 (28F008S3/S5/SC) E_28F004S5 (0xA7) -> INTEL_28F004S3 (28F008S3/S5/SC) P28F001BXT (0x94) -> INTEL_28F001T (28F001BN/BX-T) P28F001BXB (0x95) -> INTEL_28F001B (28F001BN/BX-B) E_28F016S5 (0xAA) -> INTEL_28F016S3 (28F016S3/S5/SC) Add chip IDs for the following chips: 28F320J5 28F640J5 28F320J3 28F640J3 28F128J3 28F256J3 28F200BL/BV/BX/CV-T 28F200BL/BV/BX/CV-B 28F002BL/BV/BX-B 28F008BE/BV-T 28F008BE/BV-B 28F800B5/BV/CE/CV-T 28F800B5/BV/CE/CV-B 28F016SA/SV 28F008SA 28F008S3/S5/SC 28F008S3/S5/SC 28F016XS 28F010 28F512 28F256A 28F020 28F016B3-T 28F016B3-B 28F008B3-T 28F008B3-B 28F004B3-T 28F004B3-B Corresponding to flashrom svn r1189. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Speed up RayeR SPIPGM driver in flashrom by a factor of 2Carl-Daniel Hailfinger2010-10-052-35/+69
| | | | | | | | | | | | | | | | Allow specification of an alternate base address with flashrom -p rayer_spi:iobase=0x278 Any base address is allowed as long as it is nonzero, below 65536 and a multiple of four. Read speed is now on par with original spipgm.exe. Tested-by: Martin Rehak <rayer@seznam.cz> Corresponding to flashrom svn r1188. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Board enable for GA-6IEMMichael Karcher2010-10-052-0/+3
| | | | | | | | | | | | | | Reported by Konstantin <hc@comp.susu.ac.ru> lspci (superiotool missing, doesn't matter for this patch) http://www.coreboot.org/pipermail/flashrom/2010-September/004609.html DMI is needed, as there are no usefull PCI IDs. (no test of that board yet, thus marked as untested) Corresponding to flashrom svn r1187. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Update README to list all the needed rpm files for DOS cross-compilation and ↵Idwer Vollering2010-10-051-3/+4
| | | | | | | | | | | update the download location of cwsdpmi Signed-off-by: Idwer Vollering <vidwer+flashrom@gmail.com> Corresponding to flashrom svn r1186. Signed-off-by: Idwer Vollering <vidwer+flashrom@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add Intel 82571EB and 82572EI Gigabit NICs to the supported listIdwer Vollering2010-10-051-0/+2
| | | | | | | | | Tested-by: Iain Paton <selsinork@gmail.com> Corresponding to flashrom svn r1185. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for building flashrom against libpayloadPatrick Georgi2010-09-306-5/+74
| | | | | | | | | | | This doesn't include changes to the frontend which must be done separately, so this won't work out of the box. This code was tested on hardware. Corresponding to flashrom svn r1184. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Support for Loongson-2F (MIPS) flashingVladimir 'phcoder' Serbinenko2010-09-292-1/+52
| | | | | | | Corresponding to flashrom svn r1183. Signed-off-by: Vladimir 'phcoder' Serbinenko <phcoder@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Half a dozen hardcoded strcmp() don't make sense if we need a chassis-type ↵Carl-Daniel Hailfinger2010-09-261-4/+29
| | | | | | | | | | | | | list anyway once we merge the internal DMI decoder Provide and array of the most interesting chassis types and annotate them with laptop/non-laptop status. Match the dmidecode chassis type against the strings in the array. Corresponding to flashrom svn r1182. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com>
* Implement libpayload support and improve life for DOS based flashrom, tooPatrick Georgi2010-09-253-11/+18
| | | | | | | | | | | | | Change the physmap* behaviour to use (void*)-1 as error code instead of NULL. That way, 1:1 mapped memory can be supported properly because (void*)0 is not a magic pointer anymore. (void*)-1 on the other hand is a rather unlikely memory offset, so that should be safe. Corresponding to flashrom svn r1181. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* The variable 'ret' is unused when compiling on BigEndian architecturePeter Lemenkov2010-09-201-0/+2
| | | | | | | | | | | | | | | This produces an "unused variable" message, which might be treated as error if -Werror was passed to compiler. With this patch I was able to compile flashrom cleanly on ppc and ppc64: http://koji.fedoraproject.org/koji/taskinfo?taskID=2472482 http://koji.fedoraproject.org/koji/taskinfo?taskID=2472484 Corresponding to flashrom svn r1180. Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add chip IDs for Alliance Semiconductor flash chipsMattias Mattsson2010-09-181-0/+12
| | | | | | | | | | | | | | | | | | | Cross-checked with UniFlash 1.40 source, chip datasheets and EZoFlash's chip database (http://www.ezoflash.com/chip_database.php). Datasheets: http://www.ezoflash.com/datasheets/flash/Alliance/AS29F002.pdf http://www.alsc.com/pdf/flash.pdf/as29f010.pdf http://www.alsc.com/pdf/flash.pdf/as29f040.pdf http://www.alsc.com/pdf/flash.pdf/as29f200.pdf http://www.ezoflash.com/datasheets/flash/Alliance/AS29LV160.pdf http://www.ezoflash.com/datasheets/flash/Alliance/AS29LV400.pdf http://www.ezoflash.com/datasheets/flash/Alliance/AS29LV800.pdf Corresponding to flashrom svn r1179. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Binary file (standard input) matchesCarl-Daniel Hailfinger2010-09-162-2/+27
| | | | Corresponding to flashrom svn r1178.
* Add board enable for Elitegroup GeForce6100SM-MMattias Mattsson2010-09-162-0/+25
| | | | | | | | | | | | | | | | | | Match on Memory Controller/LPC Bridge. lspci/superiotool output: http://www.coreboot.org/pipermail/flashrom/2010-September/004829.html Test report: http://www.coreboot.org/pipermail/flashrom/2010-September/004835.html Tested-by: Andrew Cleveland <evil.saltine@gmail.com> Corresponding to flashrom svn r1177. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add chip definitions for the folowing chipsJoshua Roys2010-09-162-0/+84
| | | | | | | | | | | | | | | | | | | | | | | Bright BM29F040 Hyundai HY29F040A Macronix MX29F040 Also add chip IDs for Bright BM29F400T/B Datasheets: http://www.ezoflash.com/datasheets/flash/Winbond/BM29F040.pdf http://www.ezoflash.com/datasheets/flash/Hyundai/HY29F040A.pdf http://www.ezoflash.com/datasheets/flash/Macronix/MX29F040.pdf http://www.ezoflash.com/datasheets/flash/Winbond/BM29F400T_B.pdf Bright BM29F040 probe/read test report: http://www.flashrom.org/pipermail/flashrom/2010-September/004805.html Corresponding to flashrom svn r1176. Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Mattias Mattsson <vitplister@gmail.com>
* This patch changes the prefix of chip constant #defines in the following wayMattias Mattsson2010-09-153-456/+456
| | | | | | | | | | | | | | | | | | | | | | | | AM_* -> AMD_AM* AT_* -> ATMEL_AT* EN_* -> EON_EN* HY_* -> HYUNDAI_HY* MBM* -> FUJITSU_MBM* MX_ID -> MACRONIX_ID MX_* -> MACRONIX_MX* PMC_* -> PMC_PM* SST_* -> SST_SST* It leaves the Intel #defines alone because there is another pending patch for that: http://patchwork.coreboot.org/patch/1937/ Some background discussion here: http://www.flashrom.org/pipermail/flashrom/2010-July/004059.html Corresponding to flashrom svn r1175. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add chipset enable for Broadcom OSB4Joshua Roys2010-09-151-0/+18
| | | | | | | | | No docs available. Corresponding to flashrom svn r1174. Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* AMD SB700 and later have an integrated microcontroller (IMC) which runs from ↵Carl-Daniel Hailfinger2010-09-151-0/+18
| | | | | | | | | | | | | | | | | | | | | | shared flash The IMC will happily issue reads while we write, issue writes while we read, and generally cause lots of havoc due to the concurrent accesses it performs while flashrom is running. A failing or corrupted read can be detected since r1145, and the worst case is that the read aborts and the user has to retry. A failing write is much more serious. It can be detected since r1145, but if the SPI interface locks up, we can't continue writing nor can we read the current chip contents. If the IMC is inactive, there is no reason to worry. If the IMC is active, flashrom will refuse to erase/write the chip with this patch. The correct fix would be to stop the IMC during flashing, but apparently the relevant registers are undocumented, so we take the safe route for now until someone from AMD can give us more info. Tested-by: Matthias Kretz <kretz@kde.org> Corresponding to flashrom svn r1173. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Delay between probe and subsequent operationsCarl-Daniel Hailfinger2010-09-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | Some flash chips need time to exit ID mode, and while we take care of correct timing for the matching probe, subsequent probes may have totally different timing, and that can lead to garbage responses from the flash chip during the first accesses after the probe sequence is done. Delay 100 ms between the last probe and any subsequent operation. To ensure maximum correctness, we would have to reset the chip first in case the last probe function left the chip in an undefined (non-read) state. That will be possible once struct flashchip has a .reset function. This fixes unstable erase/read/write for some flahs chips on nic3com and possible other use cases as well. Thanks to Maciej Pijanka for reporting the issue and testing patches. Corresponding to flashrom svn r1172. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* SPI bitbanging: request/release busCarl-Daniel Hailfinger2010-09-154-21/+53
| | | | | | | | | | | | | | | | | | | | | | | | | SPI bitbanging on devices which speak SPI natively has a dual-use problem: We need to shut down normal SPI operations to do the bitbanging ourselves. Once we're done, it makes a lot of sense to reenable "normal" SPI operations again. Add request_bus/release_bus functions to struct bitbang_spi_master. Add a bitbang shutdown function (not used yet). Change MCP SPI and Intel NIC SPI to use the new request/release bus infrastructure. Cosmetic changes to a few error messages (80 column limit). There are multiple possible strategies for bus request/release: - Request at the start of a SPI command, release immediately afterwards. - Request at the start of a SPI multicommand, release once all commands of the multicommand are done. - Request on programmer init, release on shutdown. Each strategy has its own advantages. For now, we will stay with the first strategy which worked fine so far. Corresponding to flashrom svn r1171. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Honor ICH SPI address window for readsCarl-Daniel Hailfinger2010-09-151-1/+22
| | | | | | | | | | | | | | | | | | | | | | | ICH SPI has the ability to restrict SPI read/write accesses to a given address range. The low end of the range is configurable by the BIOS (and by flashrom if the BIOS didn't lock down the flash interface), the high end of the range is 0xffffff (2^24-1). This patch checks for an address range restriction and uses the low end of the allowed range as base for SPI reads. A similar workaround for REMS/RES opcodes has been committed in r500. This fixes read on the Intel D945GCLF mainboard where the stock BIOS enforces a restricted address range. Please note that writes need the same fix, but for architectural reasons that fix will be merged once partial write is available. Tested by David Hendricks on the Intel D945GCLF mainboard, results at http://paste.flashrom.org/view.php?id=79 Corresponding to flashrom svn r1170. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com>
* Add missing GIGABYTE GA-7DXR entry, should have been in r1166Uwe Hermann2010-09-151-0/+1
| | | | | | | Corresponding to flashrom svn r1169. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Rename constants W_nnnn -> WINBOND_WnnnnMattias Mattsson2010-09-142-97/+79
| | | | | | | | | | | | | | | | | | | | | | | W_25nnn -> WINBOND_NEX_W25nnn Kill incorrect ASD chip and vendor id. Group Winbond SPI and parallel chips separately (they have different vendor IDs). Change constant names to the "canonical" chip name for the following ids: W_29C020C (0x45) -> WINBOND_W29C020 (Same as W29C020C, W29C022 and ASD AE29F2008) W_29C040P (0x46) -> WINBOND_W29C040 ("P" is for package type [32-pin PLCC], irrelevant) W_29C011 + W_29EE011 (0xC1) -> WINBOND_W29C010 (Same as W29C010M, W29C011A, W29EE011, W29EE012, and ASD AE29F1008) List all chip variants in the .name strings in flashchips.c Have two identical entries for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012 but with different probe functions in flashchips.c as sometimes (for newer revisions of these chips?) the standard jedec probe seems to work. E.g. see test report here: http://patchwork.coreboot.org/patch/1476/ Also add ids for the following Winbond chips: W25Q40 W25Q128 W19B160BB W19B160BT W19B320SB/W19L320SB W19B320ST/W19L320ST W19B322MB W19B322MT W19B323MB W19B323MT W19B324MB W19B324MT W29C512A/W29EE512 W39L010 W39L040A W39L512 W49F002/W49F002B Corresponding to flashrom svn r1168. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Board-enable for the ASUS A7V333Uwe Hermann2010-09-142-2/+5
| | | | | | | | | | | | | | | The board-enable is the same as for the ASUS A7V8X, i.e., it raises GP51 on the ITE IT8703F. I verified using a multimeter that this will raise both, WE# and TBL# on the flash chip. All operations successfully tested on hardware. Also renamed board_asus_a7v8x() to it8703f_gpio51_raise(). Corresponding to flashrom svn r1167. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Joshua Roys <roysjosh@gmail.com>
* Another round of board/chip status updatesUwe Hermann2010-09-143-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mark the following boards as tested: - Intel Foxhollow (reported by Jason Shriver <J.Shriver@F5.com>) http://www.flashrom.org/pipermail/flashrom/2010-September/004768.html - Intel Greencity (reported by Jason Shriver <J.Shriver@F5.com>) http://www.flashrom.org/pipermail/flashrom/2010-September/004768.html - Tyan S2915-E (Thunder n6650W) (reported by Axel Bergerhoff <axelbergerhoff@compuserve.com>) http://www.flashrom.org/pipermail/flashrom/2010-August/004560.html - ASUS Z8NA-D6C (reported by John Wells <jb@sourceillustrated.com>) http://www.flashrom.org/pipermail/flashrom/2010-September/004737.html - GIGABYTE GA-7DXR (reported by Uwe Hermann <uwe@hermann-uwe.de>) http://www.flashrom.org/pipermail/flashrom/2010-September/004712.html - MSI MS-7211 (PM8M3-V) (reported by Shahar Or <mightyiampresence@gmail.com>) http://www.flashrom.org/pipermail/flashrom/2010-September/004612.html - MSI MS-6787 (P4MAM-V/P4MAM-L) (reported by Swift Geek <swiftgeek@gmail.com>) Board-enable now marked as tested. http://www.flashrom.org/pipermail/flashrom/2010-September/004687.html Chips: - SST SST25VF016B (reported by Warren Turkal <wt@penguintechs.org>) http://www.flashrom.org/pipermail/flashrom/2010-September/004716.html Corresponding to flashrom svn r1166. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add support for ST M25PX32 and M25PX64 flash chipsJason Shriver2010-09-142-0/+60
| | | | | | | | | Probe, read, erase and write have been tested and all are functional. Corresponding to flashrom svn r1165. Signed-off-by: Jason Shriver <j.shriver@f5.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Use caching for Nvidia MCP SPI GPIO accessesCarl-Daniel Hailfinger2010-09-141-35/+25
| | | | | | | | | | | | | Reduce clock delay to zero. Tests show more than 2x speedup. Tested-by: Andrew Morgan <ziltro@ziltro.com> Corresponding to flashrom svn r1164. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add support for the abit BM6 boardTim ter Laak2010-09-132-0/+11
| | | | | | | | Corresponding to flashrom svn r1163. Signed-off-by: Tim ter Laak <timl@scintilla.utwente.nl> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add support for the Macronix MX251635E chipStephan Guilloux2010-09-132-0/+34
| | | | | | | Corresponding to flashrom svn r1162. Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add board enable for ASUS P4SC-EMattias Mattsson2010-09-132-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | I does this by setting bits 3..2 of register 0x24 on the ITE IT8707F, while keeping bit 3 of register 0x23 set while manipulating the first register. AFAIK, there is no public datasheet available for this super i/o chip, but the above is how the vendor BIOS does it. Also, registers 0x23 and 0x24 seem to have the same meaning as on the ITE IT8710F. Matching on NB/SB. Tested on a P4SC-E with SST 39SF020A flash. Probe, read, erase, write all work. lspci/superio output: http://www.flashrom.org/pipermail/flashrom/2010-July/004090.html flashrom output: http://www.flashrom.org/pipermail/flashrom/2010-August/004566.html Many thanks to Reinder de Haan for help with reverse engineering this! Corresponding to flashrom svn r1161. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Board enable for MS-6163 Pro (MS-6163 rev:2)Mattias Mattsson2010-09-132-0/+11
| | | | | | | | | | | | | | | | | | | Matching on NB/SB. Probe, read, erase and write all work. lspci/superiotool output: http://www.flashrom.org/pipermail/flashrom/2010-August/004461.html I believe that this board enable also works for MSI BX Master (MS-6163 rev:3) and perhaps also for MSI MS-6163FC (MS-6163 rev:1) but these boards have not been tested. Test logs for MS-6163 (rev:2): http://www.flashrom.org/pipermail/flashrom/2010-September/004704.html Corresponding to flashrom svn r1160. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Board enable for ASUS P5GDC DeluxeJoshua Roys2010-09-132-0/+3
| | | | | | | | | | | | | Match on SMBus and Audio. lspci/superiotool/flashrom output: http://www.flashrom.org/pipermail/flashrom/2010-September/004689.html Tested-by: Alexander Mikhnovets <alexander.mikhnovets@gmail.com> Corresponding to flashrom svn r1159. Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add a board enable for MSI MS-6561 (745 Ultra)Mattias Mattsson2010-09-113-1/+4
| | | | | | | | | | | | | | | | SiS 745 chipset + Winbond W83697HF and Winbond W49F002U flash. Probe, read, erase and write all work. Matching on "NB/SB" (they are integrated). Also mark SiS 745 chipset as tested. lspci/superiotool: http://www.flashrom.org/pipermail/flashrom/2010-September/004705.html Corresponding to flashrom svn r1158. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Board enable for P4P800Michael Karcher2010-09-102-0/+3
| | | | | | | | | | | | | | | | | | | | | lspci/superiotool: http://www.coreboot.org/pipermail/flashrom/2010-August/004436.html This goes the safe route of adding a match for the P4P800 that does not match the P4P800-E Deluxe which is already in. It seems quite likely that the whole P4P800 family could use the same board enable with one generic board enable match, though. This match uses host bridge + audio, because all other IDs match the P4P800-E Deluxe board, as reported in http://www.e-monkeys.de/Everest-Bericht.txt (no user feedback, commit as "untested") Corresponding to flashrom svn r1157. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Board enable for ASUS P5GD1 ProMichael Karcher2010-09-102-0/+3
| | | | | | | | | | | | | lspci/superiotool: http://www.coreboot.org/pipermail/flashrom/2010-August/004539.html matching SMBus + Audio, because SMBus is the only core device with usable IDs. Corresponding to flashrom svn r1156. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add a board-enable for the MSI MS-6787 (P4MAM-V/P4MAM-L)Sergey A Lichack2010-09-072-0/+3
| | | | | | | | | | Marked as untested for now, as there was no response from the user. Corresponding to flashrom svn r1155. Signed-off-by: Sergey A Lichack <shadowpilot34@gmail.com> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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