diff options
| -rw-r--r-- | Makefile | 16 | ||||
| -rw-r--r-- | flash.h | 14 | ||||
| -rw-r--r-- | flashrom.8 | 10 | ||||
| -rw-r--r-- | flashrom.c | 24 | ||||
| -rw-r--r-- | rayer_spi.c | 122 | ||||
| -rw-r--r-- | spi.c | 9 |
6 files changed, 193 insertions, 2 deletions
@@ -111,8 +111,15 @@ CONFIG_INTERNAL ?= yes # Always enable serprog for now. Needs to be disabled on Windows. CONFIG_SERPROG ?= yes -# Bitbanging SPI infrastructure is not used yet. +# RayeR SPIPGM hardware support +CONFIG_RAYER_SPI ?= yes + +# Bitbanging SPI infrastructure, default off unless needed. +ifeq ($(CONFIG_RAYER_SPI), yes) +override CONFIG_BITBANG_SPI = yes +else CONFIG_BITBANG_SPI ?= no +endif # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes @@ -166,6 +173,13 @@ NEED_SERIAL := yes NEED_NET := yes endif +ifeq ($(CONFIG_RAYER_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_RAYER_SPI=1' +PROGRAMMER_OBJS += rayer_spi.o +# Actually, NEED_PCI is wrong. NEED_IOPORT_ACCESS would be more correct. +NEED_PCI := yes +endif + ifeq ($(CONFIG_BITBANG_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_BITBANG_SPI=1' PROGRAMMER_OBJS += bitbang_spi.o @@ -81,6 +81,9 @@ enum programmer { #if CONFIG_DEDIPROG == 1 PROGRAMMER_DEDIPROG, #endif +#if CONFIG_RAYER_SPI == 1 + PROGRAMMER_RAYER_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -129,6 +132,9 @@ void programmer_delay(int usecs); enum bitbang_spi_master_type { BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */ +#if CONFIG_RAYER_SPI == 1 + BITBANG_SPI_MASTER_RAYER, +#endif }; struct bitbang_spi_master { @@ -531,6 +537,11 @@ int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const u int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +/* rayer_spi.c */ +#if CONFIG_RAYER_SPI == 1 +int rayer_spi_init(void); +#endif + /* bitbang_spi.c */ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); @@ -650,6 +661,9 @@ enum spi_controller { #if CONFIG_DEDIPROG == 1 SPI_CONTROLLER_DEDIPROG, #endif +#if CONFIG_RAYER_SPI == 1 + SPI_CONTROLLER_RAYER, +#endif SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; @@ -187,6 +187,9 @@ USB SPI programmer)" .sp .BR "* buspirate_spi" " (for SPI flash ROMs attached to a Bus Pirate)" .sp +.BR "* rayer_spi" " (for SPI flash ROMs attached to a RayeR parport \ +based programmer)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -389,6 +392,10 @@ where can be any of .BR 30k ", " 125k ", " 250k ", " 1M ", " 2M ", " 2.6M ", " 4M ", " 8M (in Hz). The default is the maximum frequency of 8 MHz. +.TP +.BR "rayer_spi " programmer +No parameters defined yet. More information about the hardware is available at +http://rayer.ic.cz/elektro/spipgm.htm .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. @@ -411,6 +418,9 @@ needs PCI configuration space access and raw I/O port access. .BR gfxnvidia " and " drkaiser need PCI configuration space access and raw memory access. .sp +.B rayer_spi +needs raw I/O port access. +.sp .B satasii needs PCI configuration space read access and raw memory access. .sp @@ -48,7 +48,7 @@ enum programmer programmer = PROGRAMMER_DUMMY; * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG > 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. #endif enum programmer programmer = @@ -86,6 +86,9 @@ enum programmer programmer = #if CONFIG_DEDIPROG == 1 PROGRAMMER_DEDIPROG #endif +#if CONFIG_RAYER_SPI == 1 + PROGRAMMER_RAYER_SPI +#endif ; #endif @@ -391,6 +394,25 @@ const struct programmer_entry programmer_table[] = { }, #endif +#if CONFIG_RAYER_SPI == 1 + { + .name = "rayer_spi", + .init = rayer_spi_init, + .shutdown = noop_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = noop_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = noop_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; diff --git a/rayer_spi.c b/rayer_spi.c new file mode 100644 index 0000000..37cf752 --- /dev/null +++ b/rayer_spi.c @@ -0,0 +1,122 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009,2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Driver for the SPIPGM hardware by "RayeR" Martin Rehak. + * See http://rayer.ic.cz/elektro/spipgm.htm for schematics and instructions. + */ + +/* This driver uses non-portable direct I/O port accesses which won't work on + * any non-x86 platform, and even on x86 there is a high chance there will be + * collisions with any loaded parallel port drivers. + * The big advantage of direct port I/O is OS independence and speed because + * most OS parport drivers will perform many unnecessary accesses although + * this driver just treats the parallel port as a GPIO set. + */ +#if defined(__i386__) || defined(__x86_64__) + +#include "flash.h" + +/* We have two sets of pins, out and in. The numbers for both sets are + * independent and are bitshift values, not real pin numbers. + */ +/* Pins for master->slave direction */ +#define SPI_CS_PIN 5 +#define SPI_SCK_PIN 6 +#define SPI_MOSI_PIN 7 +/* Pins for slave->master direction */ +#define SPI_MISO_PIN 6 + +static int lpt_iobase; + +/* FIXME: All rayer_bitbang_set_* functions could use caching of the value + * stored at port lpt_iobase to avoid unnecessary INB. In theory, only one + * INB(lpt_iobase) would be needed on programmer init to get the initial + * value. + */ + +void rayer_bitbang_set_cs(int val) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase); + tmp &= ~(1 << SPI_CS_PIN); + tmp |= (val << SPI_CS_PIN); + OUTB(tmp, lpt_iobase); +} + +void rayer_bitbang_set_sck(int val) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase); + tmp &= ~(1 << SPI_SCK_PIN); + tmp |= (val << SPI_SCK_PIN); + OUTB(tmp, lpt_iobase); +} + +void rayer_bitbang_set_mosi(int val) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase); + tmp &= ~(1 << SPI_MOSI_PIN); + tmp |= (val << SPI_MOSI_PIN); + OUTB(tmp, lpt_iobase); +} + +int rayer_bitbang_get_miso(void) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase + 1); + tmp = (tmp >> SPI_MISO_PIN) & 0x1; + return tmp; +} + +static const struct bitbang_spi_master bitbang_spi_master_rayer = { + .type = BITBANG_SPI_MASTER_RAYER, + .set_cs = rayer_bitbang_set_cs, + .set_sck = rayer_bitbang_set_sck, + .set_mosi = rayer_bitbang_set_mosi, + .get_miso = rayer_bitbang_get_miso, +}; + +int rayer_spi_init(void) +{ + /* Pick a default value for now. */ + lpt_iobase = 0x378; + + msg_pdbg("Using port 0x%x as I/O base for parallel port access.\n", + lpt_iobase); + + get_io_perms(); + + /* 1 usec halfperiod delay for now. */ + if (bitbang_spi_init(&bitbang_spi_master_rayer, 1)) + return 1; + + buses_supported = CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_RAYER; + + return 0; +} + +#else +#error PCI port I/O access is not supported on this architecture yet. +#endif @@ -121,6 +121,15 @@ const struct spi_programmer spi_programmer[] = { }, #endif +#if CONFIG_RAYER_SPI == 1 + { /* SPI_CONTROLLER_RAYER */ + .command = bitbang_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = bitbang_spi_read, + .write_256 = bitbang_spi_write_256, + }, +#endif + {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ }; |
