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| author | Nikolay Petukhov <nikolay.petukhov@gmail.com> | 2008-05-17 01:08:58 +0000 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2008-05-17 01:08:58 +0000 |
| commit | 30d431f1950a2395047b3f27f15fefbf2cf1a451 (patch) | |
| tree | fb7ab264b5a252ffee6aec466827c2e1da8ff22f /Makefile | |
| parent | 5a1320102f0a39bb227d24333f28c038a1992530 (diff) | |
| download | flashrom-30d431f1950a2395047b3f27f15fefbf2cf1a451.zip flashrom-30d431f1950a2395047b3f27f15fefbf2cf1a451.tar.gz | |
Support Pm49FL004/2 Block Locking Registers
The PMC chips understand both LPC and FWH flash commands. When in FWH mode
(MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block
Locking Registers by default lock the flash chip for write and erase - in
addition to any chipset write protection.
This patch adds unlock operations before Pm49FL004/2 write and erase, and
it includes an svn mv pm49fl004.c pm49fl00x.c
Thanks go to Nikolay for this patch.
Corresponding to flashrom svn r243 and coreboot v2 svn r3332.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Bari Ari <bari@onelabs.com>
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -22,7 +22,7 @@ endif OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.c \ sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o \ - w49f002u.o 82802ab.o msys_doc.o pm49fl004.o sst49lf040.o \ + w49f002u.o 82802ab.o msys_doc.o pm49fl00x.o sst49lf040.o \ sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o \ flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ ichspi.o |
