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| author | Jukka Ojanen <jukka.ojanen@linkotec.net> | 2014-11-09 13:53:50 +0200 |
|---|---|---|
| committer | Jukka Ojanen <jukka.ojanen@linkotec.net> | 2014-11-09 13:53:50 +0200 |
| commit | a1ddbc888ab5d54bcd80cb7d5a7f35fad724c2a1 (patch) | |
| tree | d79cfdce3fb806a95e12779c94831da492ae827d | |
| parent | d9e01009d828f4ce7a7988bf0f4e2e1dbab32208 (diff) | |
| parent | f342eb3215720f9c2fe621e3445484d55c00ff3d (diff) | |
| download | ffts-a1ddbc888ab5d54bcd80cb7d5a7f35fad724c2a1.zip ffts-a1ddbc888ab5d54bcd80cb7d5a7f35fad724c2a1.tar.gz | |
Merge commit 'f342eb3215720f9c2fe621e3445484d55c00ff3d'
| -rw-r--r-- | src/arch/x64/x64-codegen.h | 44 |
1 files changed, 39 insertions, 5 deletions
diff --git a/src/arch/x64/x64-codegen.h b/src/arch/x64/x64-codegen.h index 3fb7104..0fbffbe 100644 --- a/src/arch/x64/x64-codegen.h +++ b/src/arch/x64/x64-codegen.h @@ -209,6 +209,9 @@ typedef union { x86_membase_emit ((inst),(reg)&0x7, (basereg)&0x7, (disp)); \ } while (0) +#define x64_memindex_emit(inst, reg, basereg, disp, indexreg, shift) \ + x86_memindex_emit((inst), ((reg) & 0x7), ((basereg) & 0x7), (disp), ((indexreg) & 0x7), (shift)) + #define x64_alu_reg_imm_size_body(inst,opc,reg,imm,size) \ do { \ if (x86_is_imm8((imm))) { \ @@ -950,6 +953,16 @@ typedef union { x64_codegen_post(inst); \ } while (0) +#define emit_sse_memindex_reg_op2(inst, basereg, disp, indexreg, shift, reg, op1, op2) \ + do { \ + x64_codegen_pre(inst); \ + x64_emit_rex (inst, 0, (reg), (indexreg), (basereg)); \ + *(inst)++ = (unsigned char)(op1); \ + *(inst)++ = (unsigned char)(op2); \ + x64_memindex_emit((inst), (reg), (basereg), (disp), (indexreg), (shift)); \ + x64_codegen_post(inst); \ + } while(0) + #define emit_sse_reg_membase_op2(inst,dreg,basereg,disp,op1,op2) do { \ x64_codegen_pre(inst); \ x64_emit_rex ((inst), 0, (dreg), 0, (basereg) == X64_RIP ? 0 : (basereg)); \ @@ -959,6 +972,16 @@ typedef union { x64_codegen_post(inst); \ } while (0) +#define emit_sse_reg_memindex_op2(inst, dreg, basereg, disp, indexreg, shift, op1, op2) \ + do { \ + x64_codegen_pre(inst); \ + x64_emit_rex (inst, 0, (dreg), (indexreg), (basereg) == X64_RIP ? 0 : (basereg)); \ + *(inst)++ = (unsigned char)(op1); \ + *(inst)++ = (unsigned char)(op2); \ + x64_memindex_emit((inst), (dreg), (basereg), (disp), (indexreg), (shift)); \ + x64_codegen_post(inst); \ + } while(0) + /* Three opcode SSE defines */ #define emit_opcode3(inst,op1,op2,op3) do { \ @@ -1391,15 +1414,26 @@ typedef union { #define x64_sse_movups_reg_membase(inst, dreg, basereg, disp) emit_sse_reg_membase_op2((inst), (dreg), (basereg), (disp), 0x0f, 0x10) -#define x64_sse_movaps_membase_reg(inst, basereg, disp, reg) emit_sse_membase_reg_op2((inst), (basereg), (disp), (reg), 0x0f, 0x29) +#define x64_sse_movaps_membase_reg(inst, basereg, disp, reg) \ + emit_sse_membase_reg_op2((inst), (basereg), (disp), (reg), 0x0f, 0x29) + +#define x64_sse_movaps_memindex_reg(inst, basereg, disp, indexreg, shift, reg) \ + emit_sse_memindex_reg_op2((inst), (basereg), (disp), (indexreg), (shift), (reg), 0x0f, 0x29); + +#define x64_sse_movaps_reg_membase(inst, dreg, basereg, disp) \ + emit_sse_reg_membase_op2((inst), (dreg), (basereg), (disp), 0x0f, 0x28) -#define x64_sse_movaps_reg_membase(inst, dreg, basereg, disp) emit_sse_reg_membase_op2((inst), (dreg), (basereg), (disp), 0x0f, 0x28) +#define x64_sse_movaps_reg_memindex(inst, dreg, basereg, disp, indexreg, shift) \ + emit_sse_reg_memindex_op2((inst), (dreg), (basereg), (disp), (indexreg), (shift), 0x0f, 0x28); -#define x64_sse_movaps_reg_reg(inst, dreg, reg) emit_sse_reg_reg_op2((inst), (dreg), (reg), 0x0f, 0x28) +#define x64_sse_movaps_reg_reg(inst, dreg, reg) \ + emit_sse_reg_reg_op2((inst), (dreg), (reg), 0x0f, 0x28) -#define x64_sse_movntps_reg_membase(inst, dreg, basereg, disp) emit_sse_reg_membase_op2((inst), (dreg), (basereg), (disp), 0x0f, 0x2b) +#define x64_sse_movntps_reg_membase(inst, dreg, basereg, disp) \ + emit_sse_reg_membase_op2((inst), (dreg), (basereg), (disp), 0x0f, 0x2b) -#define x64_sse_prefetch_reg_membase(inst, arg, basereg, disp) emit_sse_reg_membase_op2((inst), (arg), (basereg), (disp), 0x0f, 0x18) +#define x64_sse_prefetch_reg_membase(inst, arg, basereg, disp) \ + emit_sse_reg_membase_op2((inst), (arg), (basereg), (disp), 0x0f, 0x18) #define x64_sse_movdqa_membase_reg(inst, basereg, disp, reg) \ emit_sse_membase_reg((inst), (basereg), (disp), (reg), 0x66, 0x0f, 0x7f) |
