| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Reviewed-by: Paul B Mahol <onemda@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Previously there was a limit of two cpuflags.
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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This makes more sense for future implementations of templates with zmm registers.
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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501 to 439 decicycles.
See 45c7f3997ea11c3d1007b2126b1c0049a8c27105.
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~560 → ~500 decicycles
This is following the comments from Michael in
https://ffmpeg.org/pipermail/ffmpeg-devel/2014-August/160599.html
Using 2 registers for accumulator didn't help. On the other hand,
some re-ordering between the movs and psadbw allowed going ~538 to ~500.
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Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Up to four instructions less depending on function and instruction set.
Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Only 8-bit and 10-bit idct_dc() functions are included (adding others should be trivial).
Benchmarks on an Intel Core i5-4200U:
idct8x8_dc
SSE2 MMXEXT C
cycles 22 26 57
idct16x16_dc
AVX2 SSE2 C
cycles 27 32 249
idct32x32_dc
AVX2 SSE2 C
cycles 62 126 1375
Signed-off-by: James Almer <jamrial@gmail.com>
Reviewed-by: Mickaël Raulet <mraulet@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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* commit '79793f833784121d574454af4871866576c0749d':
Update Fiona's name in copyright statements.
Merged-by: Michael Niedermayer <michaelni@gmx.at>
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Those macros take a byte number as shift argument, as this argument
differs between MMX and SSE2 instructions.
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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It was lost during the port.
Should fix fate on 3dnowext machines.
Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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tos3k-vp9-b10000.webm on a Core i5-4200U @1.6GHz
1219 decicycles in ff_vp9_ipred_dc_32x32_ssse3, 131070 runs, 2 skips
439 decicycles in ff_vp9_ipred_dc_32x32_avx2, 131070 runs, 2 skips
3570 decicycles in ff_vp9_ipred_dc_top_32x32_ssse3, 4096 runs, 0 skips
2494 decicycles in ff_vp9_ipred_dc_top_32x32_avx2, 4096 runs, 0 skips
1419 decicycles in ff_vp9_ipred_dc_left_32x32_ssse3, 16384 runs, 0 skips
717 decicycles in ff_vp9_ipred_dc_left_32x32_avx2, 16384 runs, 0 skips
2737 decicycles in ff_vp9_ipred_tm_32x32_avx, 1024 runs, 0 skips
2088 decicycles in ff_vp9_ipred_tm_32x32_avx2, 1024 runs, 0 skips
3090 decicycles in ff_vp9_ipred_v_32x32_avx, 512 runs, 0 skips
2226 decicycles in ff_vp9_ipred_v_32x32_avx2, 512 runs, 0 skips
1565 decicycles in ff_vp9_ipred_h_32x32_avx, 1024 runs, 0 skips
922 decicycles in ff_vp9_ipred_h_32x32_avx2, 1024 runs, 0 skips
Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Use the xm# and ym# aliases as they remain in sync with m# after a SWAP.
No actual changes to the assembly.
Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Also port relevant AVX2/XOP optimizations from x264 with permission
to relicense to LGPL from the corresponding authors
Signed-off-by: James Almer <jamrial@gmail.com>
Reviewed-by: "Ronald S. Bultje" <rsbultje@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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~6% faster SSE2 performance. AVX/FMA3 are unaffected.
Signed-off-by: James Almer <jamrial@gmail.com>
Reviewed-by: Christophe Gisquet <christophe.gisquet@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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The mova is unnecessary
Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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AV_CPU_FLAG_AVX is enabled at this point only if there's OS support.
Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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symbol reference in inline asm are not supported.
This is part of the patch-set for intel C inline asm on windows support
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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~7% faster than AVX
Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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We need the emulation to support the cases where the first
argument is the same as the fourth. To achieve this a fifth
argument working as a temporary may be needed.
Emulation that doesn't obey the original instruction semantics
can't be in x86inc.
Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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* qatar/master:
x86: add detection for Bit Manipulation Instruction sets
Conflicts:
libavutil/x86/cpu.c
See: 0bc3de19ffe296254f214dc7615e624d8e401bcb
Merged-by: Michael Niedermayer <michaelni@gmx.at>
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Based on x264 code
Signed-off-by: James Almer <jamrial@gmail.com>
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* commit '1b932eb1508f550fac9e911923a0383efda53aa3':
x86: add detection for FMA3 instruction set
Conflicts:
configure
libavutil/cpu.h
libavutil/x86/cpu.c
See: a2af8eddab75f1eac712411e4dde89823c0845e8
Merged-by: Michael Niedermayer <michaelni@gmx.at>
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Based on x264 code
Signed-off-by: James Almer <jamrial@gmail.com>
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Signed-off-by: James Almer <jamrial@gmail.com>
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vector_fmul and vector_fmac_scalar are guaranteed that they can process in
batch of 16 elements, but their SSE versions only does 8 at a time.
Therefore, unroll them a bit.
299 to 261c for 256 elements in vector_fmac_scalar on Arrandale/Win64.
Signed-off-by: Janne Grunau <janne-libav@jannau.net>
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Work around Yasm's inefficiency with handling large numbers of variables
in the global scope.
Signed-off-by: Diego Biurrun <diego@biurrun.de>
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Based on x264 code
Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Based on x264 code
Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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vector_fmul and vector_fmac_scalar are guaranteed that they can process in
batch of 16 elements, but their SSE versions only does 8 at a time.
Therefore, unroll them a bit.
299 to 261c for 256 elements in vector_fmac_scalar on Arrandale/Win64.
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Support the cases where the first and last operand of
the XOP instruction are the same.
Also add vpmacsdql emulation.
Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Signed-off-by: James Almer <jamrial@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Work around yasm's inefficiency with handling large numbers of variables
in the global scope.
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different ABI
also remove failed attempt at a compatibility layer, the code simply cannot work
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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* commit '4d6ee0725553a43ba88d6f8327ebcf8f1c5ae8d4':
libavutil: x86: Add AVX2 capable CPU detection.
Conflicts:
libavutil/cpu.c
libavutil/cpu.h
libavutil/x86/cpu.c
See: 865b70bc5d1cf37ec6d6cb729a69dda2cca28bd5
Merged-by: Michael Niedermayer <michaelni@gmx.at>
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Patch based on x264's AVX2 detection
Signed-off-by: Derek Buitenhuis <derek.buitenhuis@gmail.com>
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Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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* qatar/master:
x86: more AVX2 framework
Merged-by: Michael Niedermayer <michaelni@gmx.at>
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Signed-off-by: Derek Buitenhuis <derek.buitenhuis@gmail.com>
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