From be61a173512ece32de01562995a91fbbf3f5b335 Mon Sep 17 00:00:00 2001
From: Patrick Georgi <patrick.georgi@coresystems.de>
Date: Sat, 18 Dec 2010 07:48:43 +0000
Subject: Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board which
 uses it.

Compiles, but not boot tested lately.
Many things missing (eg. SMM support, proper ACPI, ...)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
 src/northbridge/intel/sch/port_access.c | 75 +++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 src/northbridge/intel/sch/port_access.c

(limited to 'src/northbridge/intel/sch/port_access.c')

diff --git a/src/northbridge/intel/sch/port_access.c b/src/northbridge/intel/sch/port_access.c
new file mode 100644
index 0000000..73e03c8
--- /dev/null
+++ b/src/northbridge/intel/sch/port_access.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009-2010 iWave Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include "sch.h"
+
+/*
+ * Restricted Access Regions:
+ *
+ * MCR - Message Control Register
+ * 31        24              16                 8              4              0
+ * ----------------------------------------------------------------------------
+ * |          |               |    Target       |   Write      |              |
+ * | Opcode   |  Port         |    register     |   byte       |   Reserved   |
+ * |          |               |    Address      |   Enables    |              |
+ * ----------------------------------------------------------------------------
+ *
+ * MDR - Message Data Register
+ * 31                                                                         0
+ * ----------------------------------------------------------------------------
+ * |                                                                          |
+ * |                            Data                                          |
+ * |                                                                          |
+ * ----------------------------------------------------------------------------
+ *
+ */
+#define MSG_OPCODE_READ  0xD0000000
+#define MSG_OPCODE_WRITE 0xE0000000
+
+#define MCR 0xD0
+#define MDR 0xD4
+
+int sch_port_access_read(int port,int reg, int bytes)
+{
+	pci_write_config32(PCI_DEV(0, 0, 0), MCR, (MSG_OPCODE_READ |(port <<16) | (reg << 8) ));
+	return pci_read_config32(PCI_DEV(0, 0, 0), MDR);
+}
+
+void sch_port_access_write(int port,int reg,int bytes,long data)
+{
+	pci_write_config32(PCI_DEV(0, 0, 0), MDR,data);
+	pci_write_config32(PCI_DEV(0, 0, 0), MCR, (MSG_OPCODE_WRITE |(port <<16) | (reg << 8) ));
+	pci_read_config32(PCI_DEV(0, 0, 0), MDR);
+}
+
+void sch_port_access_write_ram_cmd(int cmd,int port,int reg,int data)
+{
+
+ 	pci_write_config32(PCI_DEV(0, 0, 0), MDR,data);
+	pci_write_config32(PCI_DEV(0, 0, 0), MCR, ((cmd << 24) |(port <<16) | (reg << 8)));
+	pci_read_config32(PCI_DEV(0, 0, 0), MDR);
+}
+
-- 
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