From dd2e8c35fb368316b51d969d046696a017f09d25 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 24 Apr 2014 02:58:11 +1000 Subject: superio/fintek/f71869ad: Configure multi-func reg in devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Facilitate for the configuration of so called "Multi-function Select Registers" with devicetree.cb in ramstage. Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI mode. This allows the Fintek to correctly talk to the Southbridge over the SMBus for CPU temperature data as to control fans and so on. Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/5576 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 6c26f75..1c8853d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -56,6 +56,11 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/fintek/f71869ad + register "multi_function_register_1" = "0x01" + register "multi_function_register_2" = "0x6f" + register "multi_function_register_3" = "0x24" + register "multi_function_register_4" = "0x00" + register "multi_function_register_5" = "0x60" # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, -- cgit v1.1