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| author | Scott Radcliffe <sradcliffe@microind.com> | 2014-10-10 16:09:52 -0400 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-10-14 18:59:22 +0200 |
| commit | 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e (patch) | |
| tree | 8213ae3028d138abe5b9f6ef9874154949ec9819 | |
| parent | bf9d6a856788f7bae7c3732b1761adb99ac3914f (diff) | |
| download | coreboot-staging-8ffc085e1affaabbe3dca8ac6a89346b71dfc02e.zip coreboot-staging-8ffc085e1affaabbe3dca8ac6a89346b71dfc02e.tar.gz | |
intel/fsp_baytrail: Add padding so device_nvs location matches ACPI
The offset of the device_nvs in the gnvs struct is expected to be
0x1000. It is actually 0x100 so padding is needed to move device_nvs
to the expected location. ACPI references to device_nvs objects will
be correct with the padding.
This was tested using a Micro Industries customized Baytrail-I board
based on the Intel Bayley Bay CRB. In intel/baytrail/nvs.h, there's
a Google customized structure located at 0x0100-0x0FFF that is
removed from the fsp_baytrail/nvs.h which explains the mismatch here.
Change-Id: I4721a79b53b5b3345ff9b0c053bdd31d2cf9cb61
Signed-off-by: Scott Radcliffe <sradcliffe@microind.com>
Reviewed-on: http://review.coreboot.org/7038
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
| -rw-r--r-- | src/soc/intel/fsp_baytrail/baytrail/nvs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/baytrail/nvs.h b/src/soc/intel/fsp_baytrail/baytrail/nvs.h index 53c4a64..242f6d3 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/nvs.h +++ b/src/soc/intel/fsp_baytrail/baytrail/nvs.h @@ -61,6 +61,9 @@ typedef struct { u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[196]; + /* Pad 0x0100-0x0fff */ + u8 rsvd4[3840]; + /* Baytrail LPSS (0x1000) */ device_nvs_t dev; } __attribute__((packed)) global_nvs_t; |
