newconfig is no more.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

653 files changed, 15 insertions, 64257 deletions

diff --git a/src/arch/i386/Config.lb b/src/arch/i386/Config.lb
deleted file mode 100644
index 7234c33..0000000
--- a/src/arch/i386/Config.lb
+++ /dev/null
@@ -1,73 +0,0 @@
-uses CONFIG_SMP
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_USE_INIT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_USE_FALLBACK_IMAGE
-
-init init/crt0.S.lb
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-	initobject /src/lib/cbfs.o
-	initobject /src/lib/lzma.o
-end
-
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		ldscript init/ldscript_failover.lb
-	else
-			ldscript init/ldscript_cbfs.lb
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		ldscript init/ldscript_fallback_cbfs.lb
-	else
-		ldscript init/ldscript_cbfs.lb
-	end
-end
-
-makerule all
-	depends	"coreboot.rom"
-end
-
-makerule floppy 
-	depends	"all" 
-	action	"mcopy -o coreboot.rom a:"
-end
-
-makerule nrv2b 
-	depends	"$(TOP)/util/nrv2b/nrv2b.c"
-	action	"$(HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@"
-end
-
-if CONFIG_USE_FAILOVER_IMAGE
-	makedefine COREBOOT_APC:=
-	makedefine COREBOOT_RAM_ROM:=
-end
-
-makerule crt0.S
-	depends "$(CONFIG_CRT0)"
-	action  "cp $< $@"
-end
-
-addaction clean "rm -f romimage payload.*"
-
-if CONFIG_USE_INIT
-	makerule init.o
-        	depends "$(INIT-OBJECTS)"
-	        action  "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)"
-	        action  "$(CONFIG_OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
-	end
-
-        makerule coreboot   
-		depends	"crt0.o init.o $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
-		action	"$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
-		action	"$(CONFIG_CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
-        end
-
-end
-
-dir lib
-dir boot
-dir smp
diff --git a/src/arch/i386/boot/Config.lb b/src/arch/i386/boot/Config.lb
deleted file mode 100644
index ec5c669..0000000
--- a/src/arch/i386/boot/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_MULTIBOOT
-uses CONFIG_HAVE_ACPI_RESUME
-
-object boot.o
-object coreboot_table.o
-if CONFIG_MULTIBOOT
-object multiboot.o
-end
-object tables.o
-if CONFIG_GENERATE_PIRQ_TABLE
-object pirq_routing.o 
-end
-if CONFIG_GENERATE_ACPI_TABLES
-object acpi.o
-object acpigen.o
-if CONFIG_HAVE_ACPI_RESUME
-object wakeup.S
-end
-end
-object gdt.o
diff --git a/src/arch/i386/lib/Config.lb b/src/arch/i386/lib/Config.lb
deleted file mode 100644
index 1d434e2..0000000
--- a/src/arch/i386/lib/Config.lb
+++ /dev/null
@@ -1,18 +0,0 @@
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_USE_FAILOVER_IMAGE
-
-object c_start.S
-object cpu.c
-object pci_ops_conf1.c
-object pci_ops_conf2.c
-object pci_ops_mmconf.c
-object pci_ops_auto.c
-object exception.c
-
-initobject printk_init.o
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-	initobject cbfs_and_run.o
-end
diff --git a/src/arch/i386/smp/Config.lb b/src/arch/i386/smp/Config.lb
deleted file mode 100644
index 70981a9..0000000
--- a/src/arch/i386/smp/Config.lb
+++ /dev/null
@@ -1,10 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_IOAPIC
-
-if CONFIG_GENERATE_MP_TABLE
-  object mpspec.o 
-end
-if CONFIG_IOAPIC
-  object ioapic.o
-end
-
diff --git a/src/boot/Config.lb b/src/boot/Config.lb
deleted file mode 100644
index 8afe637..0000000
--- a/src/boot/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-object hardwaremain.o
-object selfboot.o
diff --git a/src/config/Config.lb b/src/config/Config.lb
deleted file mode 100644
index 082cf80..0000000
--- a/src/config/Config.lb
+++ /dev/null
@@ -1,214 +0,0 @@
-## This is Architecture independant part of the makefile
-
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_AP_CODE_IN_CAR
-uses CONFIG_ASSEMBLER_DEBUG
-
-makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E
-makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
-makedefine GCC ?= $(CC)
-makedefine GCC_INC_DIR := $(shell LC_ALL=C $(GCC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")
-
-makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(CONFIG_ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
-makedefine CFLAGS = $(CONFIG_CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -pipe
-
-if CONFIG_ASSEMBLER_DEBUG
-makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm
-end
-
-makedefine HOSTCFLAGS:= -Os -Wall -Wstrict-prototypes -Wmissing-prototypes -Wredundant-decls -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow
-
-makerule ldscript.ld   
-	depends	"ldoptions $(LDSUBSCRIPTS-1)" 
-	action  "echo 'INCLUDE ldoptions' > $@; for file in $(LDSUBSCRIPTS-1) ; do echo /\* $$file \*/ >> $@; cat $$file >> $@ ; done"
-end
-
-#makerule cpuflags   
-#	depends	"Makefile.settings" 
-#	action	"perl -e 'print \"CPUFLAGS :=\n\"; foreach $$var (split(\" \", $$ENV{VARIABLES})) { if (exists($$ENV{$$var})) { print \"CPUFLAGS += -D$$var\" . (length($$ENV{$$var})?\"=\x27$$ENV{$$var}\x27\":\"\") .\"\n\"} else { print \"CPUFLAGS += -U$$var\n\"} }' > $@"
-#end
-
-#makerule ldoptions   
-#	depends	"Makefile.settings" 
-#	action	"perl -e 'foreach $$var (split(\" \", $$ENV{VARIABLES})) { if ($$ENV{$$var} =~ m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$$/) { print \"$$var = $$ENV{$$var};\n\"; }}' > $@"
-#end
-
-makerule coreboot.rom
-	depends	"coreboot" 
-	action	"$(CONFIG_OBJCOPY) -O binary coreboot coreboot.rom"
-end
-
-makerule coreboot.a
-        depends "$(OBJECTS)"
-        action  "rm -f coreboot.a"
-        action  "$(CONFIG_CROSS_COMPILE)ar cr coreboot.a $(OBJECTS)"
-end
-
-
-makerule coreboot_ram.o
-	depends	"src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" 
-	action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,-\( coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)"
-end
-
-makerule coreboot_ram
-	depends	"coreboot_ram.o $(TOP)/src/config/coreboot_ram.ld ldoptions" 
-	action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_ram.ld coreboot_ram.o"
-	action 	"$(CONFIG_CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map"
-end
-
-##
-## By default compress the part of coreboot that runs from RAM
-##
-makedefine COREBOOT_RAM-$(CONFIG_COMPRESS):=coreboot_ram.nrv2b
-makedefine COREBOOT_RAM-$(CONFIG_UNCOMPRESSED):=coreboot_ram.bin
-
-makerule coreboot_ram.bin 
-	depends	"coreboot_ram" 
-	action	"$(CONFIG_OBJCOPY) -O binary $< $@"
-end
-
-makerule coreboot_ram.nrv2b 
-	depends	"coreboot_ram.bin nrv2b" 
-	action	"./nrv2b e $< $@"
-end
-
-makerule coreboot_ram.rom
-	depends	"$(COREBOOT_RAM-1)" 
-	action	"cp $(COREBOOT_RAM-1) coreboot_ram.rom"
-end
-
-makedefine COREBOOT_APC:=
-
-if CONFIG_AP_CODE_IN_CAR
-	#for ap code in cache
-
-	makerule coreboot_apc.a
-		depends "apc_auto.o"
-		action  "rm -f coreboot_apc.a"
-		action  "$(CONFIG_CROSS_COMPILE)ar cr coreboot_apc.a apc_auto.o"
-	end
-
-	makerule coreboot_apc.o
-		depends "src/arch/$(CONFIG_ARCH)/lib/c_start.o coreboot_apc.a"
-        	action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^"
-	end
-
-	makerule coreboot_apc
-		depends "coreboot_apc.o $(TOP)/src/config/coreboot_apc.ld ldoptions"
-		action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_apc.ld coreboot_apc.o"
-		action  "$(CONFIG_CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map"
-	end
-
-	##
-	## By default compress the part of coreboot that runs from cache as ram
-	##
-	makedefine COREBOOT_APC-$(CONFIG_COMPRESS):=coreboot_apc.nrv2b
-	makedefine COREBOOT_APC-$(CONFIG_UNCOMPRESSED):=coreboot_apc.bin
-
-	makerule coreboot_apc.bin
-		depends "coreboot_apc"
-		action  "$(CONFIG_OBJCOPY) -O binary $< $@"
-	end
-
-	makerule coreboot_apc.nrv2b
-        depends "coreboot_apc.bin nrv2b"
-        action  "./nrv2b e $< $@"
-	end
-
-	makerule coreboot_apc.rom
-		depends "$(COREBOOT_APC-1)"
-		action  "cp $(COREBOOT_APC-1) coreboot_apc.rom"
-	end
-
-	makedefine COREBOOT_APC:=coreboot_apc.rom
-
-end
-
-makedefine COREBOOT_RAM_ROM:=coreboot_ram.rom
-
-makerule coreboot   
-	depends	"crt0.o $(INIT-OBJECTS) $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
-	action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)"
-	action	"$(CONFIG_CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
-	action 	"$(CONFIG_CROSS_COMPILE)objdump -dS coreboot > coreboot.disasm"	
-end
-
-# Force crt0.s (which has build time version code in it to rebuild every time)
-makedefine .PHONY : crt0.s
-makerule crt0.s   
-	depends	"crt0.S $(CRT0_INCLUDES)" 
-	action	"$(CPP) $(CPPFLAGS) -I. -I$(TOP)/src  $< > $@.new && mv $@.new $@"
-end
-
-# generate an assembly listing via -a switch.
-makerule crt0.o  
-	depends	"crt0.s" 
-	action	"$(CC) -Wa,-acdlns -c $(CONFIG_CPU_OPT) -o $@ $< >crt0.disasm"
-end
-
-makerule etags   
-	depends	"$(SOURCES)" 
-	action	"etags $(SOURCES)"
-end
-makerule tags   
-	depends	"$(SOURCES)" 
-	action	"ctags $(SOURCES)"
-end
-makerule corebootDoc.config
-	depends	"$(TOP)/src/config/corebootDoc.config" 
-	action "cat $(TOP)/src/config/corebootDoc.config > corebootDoc.config"
-        action "echo 'INPUT=$(SOURCES)' >> corebootDoc.config"
-end
-makerule documentation   
-	depends	"corebootDoc.config"
-	action	"doxygen corebootDoc.config"
-end
-
-# Yes, the rule doesn't seem to make sense, but multiple images could try to
-# create a romcc binary at the same time, clobbering each other.
-# Our makefile architecture won't allow us to easily have the romcc target
-# in the main makefile, so keep it here and move the race condition winner
-# in place. That way, romcc may get compiled twice, but the binary will always
-# be in a correct and valid state if it exists because the move is atomic.
-makerule ../romcc   
-	depends	"$(TOP)/util/romcc/romcc.c" 
-	action	"$(HOSTCC) -g $(HOSTCFLAGS) $< -o romcc.tmpfile"
-	action	"mv romcc.tmpfile $@"
-end
-
-makerule build_opt_tbl   
-	depends	"$(TOP)/util/options/build_opt_tbl.c $(TOP)/src/include/pc80/mc146818rtc.h $(TOP)/src/include/boot/coreboot_tables.h Makefile.settings Makefile"
-	action	"$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) $< -o $@" 
-end
-
-makerule option_table.h option_table.c
-	depends	"build_opt_tbl $(CONFIG_MAINBOARD)/cmos.layout" 
-	action	"./build_opt_tbl --config $(CONFIG_MAINBOARD)/cmos.layout --header option_table.h --option option_table.c"
-end
-
-if CONFIG_HAVE_OPTION_TABLE
-object ./option_table.o 
-end
-
-makerule clean 
-	action  "rm -f $(OBJECTS)"
-	action  "rm -f $(DRIVER)"
-	action	"rm -f coreboot.* *~"
-	action	"rm -f coreboot"
-	action	"rm -f ldscript.ld"
-	action	"rm -f a.out *.s *.l *.o *.E *.inc"
-	action	"rm -f TAGS tags romcc*"
-	action	"rm -f docipl chips.c *chip.c coreboot_apc* coreboot_ram* coreboot_pay*"
-	action	"rm -f build_opt_tbl* nrv2b* option_table.c option_table.h crt0.S crt0.disasm"
-	action	"rm -f smm smm.elf smm.map smm_bin.c"
-	action	"rm -f dsdt.aml dsdt.c"
-	action	"rm -f payload"
-end
-
-# do standard config files that the user need not specify
-# for now, this is just 'lib', but it may be more later. 
-dir /lib
-dir /console
-dir /devices
-dir /pc80
-dir /boot
diff --git a/src/config/Options.lb b/src/config/Options.lb
deleted file mode 100644
index 9af3daf..0000000
--- a/src/config/Options.lb
+++ /dev/null
@@ -1,1122 +0,0 @@
-#######################################################
-#
-# Main options file for coreboot
-#
-# Each option used by a part must be defined in
-# this file. The format for options is:
-#
-#   define <name> 
-#	default <expr> | {<expr>} | "<string>" | none
-#	format "<string>"
-#	export always | used | never
-#	comment "<string>"
-#   end
-#
-# where 
-#
-#   <name> is the name of the option
-#   <expr> is a numeric expression
-#   <string> is a string
-#
-# Either a default value or 'default none' must
-# be specified for every option. An option
-# specified as 'default none' will not be exported
-# (i.e. will remain undefined) unless it has
-# been assigned a value.
-#
-# Option values can be an immediate expression that 
-# evaluates to a numeric value, a delayed expression 
-# (surrounded by curley braces), or a string 
-# (surrounded by double quotes.)
-#
-# Immediate expressions are evaluated at the time an
-# option is defined or set and the numeric result 
-# becomes the value of the option.
-#
-# Delayed expression are evaluated at the time the 
-# option is used, either in another expression or 
-# when being exported.
-#
-# String values will have the double quotes removed 
-# automatically. 
-#
-# Format strings determine the print format that is 
-# used when exporting options. The default format
-# is "%s" for strings and "%d" for numbers.
-#
-# Exported options generate entries in the 
-# Makefile.settings file. Options can be always 
-# exported, exported only if used, or never exported.
-#
-# A comment string must be supplied for every option.
-#
-#######################################################
-
-###############################################
-# Architecture options
-###############################################
-
-define CONFIG_ARCH_X86
-	default 1
-	export always
-	comment "X86 is the default"
-end
-define CONFIG_ARCH
-	default "i386"
-	export always
-	comment "Default architecture is i386, options are alpha and ppc"
-end
-define CONFIG_HAVE_MOVNTI
-	default 0
-	export always
-	comment "This cpu supports the MOVNTI directive"
-end
-
-###############################################
-# Build options
-###############################################
-
-define CONFIG_CROSS_COMPILE
-	default ""
-	export always
-	comment "Cross compiler prefix"
-end
-define CC
-	default "$(CONFIG_CROSS_COMPILE)gcc"
-	export always
-	comment "Target C Compiler"
-end
-define HOSTCC
-	default "gcc"
-	export always
-	comment "Host C Compiler"
-end
-define CONFIG_CPU_OPT
-	default none
-	export used
-	comment "Additional per-cpu CFLAGS"
-end
-define CONFIG_OBJCOPY
-	default "$(CONFIG_CROSS_COMPILE)objcopy --gap-fill 0xff"
-	export always
-	comment "Objcopy command"
-end
-
-# Try to determine svn revision first.
-# If that fails, try last svn revision in git log.
-define COREBOOT_VERSION
-	default "2.0.0-r$(shell if [ -d $(TOP)/.svn -a -f `which svnversion` ]; then svnversion $(TOP); else if [ -d $(TOP)/.git -a -f `which git` ]; then git --git-dir=/$(TOP)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)"
-	export always
-	format "\"%s\""
-	comment "coreboot version"
-end
-define COREBOOT_EXTRA_VERSION
-        default ""
-        export used
-	format "\"%s\""
-        comment "coreboot extra version"
-end
-define COREBOOT_BUILD
-	default "$(shell date)"
-	export always
-	format "\"%s\""
-	comment "Build date"
-end
-define COREBOOT_COMPILE_TIME
-	default "$(shell date +%T)"
-	export always
-	format "\"%s\""
-	comment "Build time"
-end
-define COREBOOT_COMPILE_BY
-	default "$(shell whoami)"
-	export always
-	format "\"%s\""
-	comment "Who build this image"
-end
-define COREBOOT_COMPILE_HOST
-	default "$(shell hostname)"
-	export always
-	format "\"%s\""
-	comment "Build host"
-end
-
-define COREBOOT_COMPILE_DOMAIN
-	default "$(shell dnsdomainname)"
-	export always
-	format "\"%s\""
-	comment "Build domain name"
-end
-define COREBOOT_COMPILER
-	default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -1)"
-	export always
-	format "\"%s\""
-	comment "Build compiler"
-end
-define COREBOOT_LINKER
-	default "$(shell  $(CC) -Wl,--version 2>&1 | grep \" ld\")"
-	export always
-	format "\"%s\""
-	comment "Build linker"
-end
-define COREBOOT_ASSEMBLER
-	default "$(shell  touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
-	export always
-	format "\"%s\""
-	comment "Build assembler"
-end
-define CONFIG_CHIP_CONFIGURE
-	default 0
-	export used
-	comment "Use new chip_configure method for configuring (non-pci) devices"
-end
-define CONFIG_USE_INIT
-	default 0
-	export always
-	comment "Use stage 1 initialization code"
-end
-
-###############################################
-# ROM image options
-###############################################
-
-define CONFIG_HAVE_FALLBACK_BOOT
-	format "%d"
-	default 0
-	export always
-	comment "Set if fallback booting required"
-end
-define CONFIG_HAVE_FAILOVER_BOOT
-	format "%d"
-	default 0
-	export always
-	comment "Set if failover booting required"
-end
-define CONFIG_USE_FALLBACK_IMAGE
-	format "%d"
-	default 0
-	export used
-	comment "Set to build a fallback image"
-end
-define CONFIG_USE_FAILOVER_IMAGE
-        format "%d"
-        default 0
-        export used
-        comment "Set to build a failover image"
-end
-define CONFIG_FALLBACK_SIZE
-	default 65536
-	format "0x%x"
-	export used
-	comment "Default fallback image size"
-end
-define CONFIG_FAILOVER_SIZE
-        default 0
-        format "0x%x"
-        export used
-        comment "Default failover image size"
-end
-define CONFIG_ROM_SIZE
-	default none
-	format "0x%x"
-	export used
-	comment "Size of your ROM"
-end
-define CONFIG_ROM_IMAGE_SIZE
-	default 65535
-	format "0x%x"
-	export always
-	comment "Default image size"
-end
-define CONFIG_ROM_SECTION_SIZE
-	default {CONFIG_FALLBACK_SIZE}
-	format "0x%x"
-	export used
-	comment "Default rom section size"
-end
-define CONFIG_ROM_SECTION_OFFSET
-	default {CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE}
-	format "0x%x"
-	export used
-	comment "Default rom section offset"
-end
-define CONFIG_ROMBASE
-	default {0xffffffff - CONFIG_ROM_SIZE + 1}
-	format "0x%x"
-	export always
-	comment "Base address of coreboot in ROM"
-end
-define CONFIG_ROMSTART
-	default none
-	format "0x%x"
-	export used
-	comment "Start address of coreboot in ROM"
-end
-define CONFIG_RESET
-	default {CONFIG_ROMBASE}
-	format "0x%x"
-	export always
-	comment "Hardware reset vector address"
-end
-define CONFIG_STACK_SIZE
-	default 0x2000
-	format "0x%x"
-	export always
-	comment "Default stack size"
-end
-define CONFIG_HEAP_SIZE
-	default 0x2000
-	format "0x%x"
-	export always
-	comment "Default heap size"
-end
-define CONFIG_RAMBASE
-	default none
-	format "0x%x"
-	export always
-	comment "Base address of coreboot in RAM"
-end
-define CONFIG_RAMSTART
-	default none
-	format "0x%x"
-	export used
-	comment "Start address of coreboot in RAM"
-end
-define CONFIG_USE_DCACHE_RAM
-	default 0
-	export always
-	comment "Use data cache as temporary RAM if possible"
-end
-define CONFIG_DCACHE_RAM_BASE
-	default 0xc0000
-	format "0x%x"
-	export always
-	comment "Base address of data cache when using it for temporary RAM"
-end
-define CONFIG_DCACHE_RAM_SIZE
-	default 0x1000
-	format "0x%x"
-	export always
-	comment "Size of data cache when using it for temporary RAM"
-end
-define CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-	default 0
-	format "0x%x"
-	export always
-	comment "Size of region that for global variable of cache as ram stage"
-end
-define CONFIG_AP_CODE_IN_CAR
-        default 0
-        export always
-        comment "will copy coreboot_apc to AP cache ane execute in AP"
-end
-define CONFIG_MEM_TRAIN_SEQ
-        default 0
-        export always
-        comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
-end
-define CONFIG_WAIT_BEFORE_CPUS_INIT
-        default 0
-        export always
-        comment "execute cpus_ready_for_init if it is set to 1"
-end
-define CONFIG_XIP_ROM_BASE
-	default 0
-	format "0x%x"
-	export used
-	comment "Start address of area to cache during coreboot execution directly from ROM"
-end
-define CONFIG_XIP_ROM_SIZE
-	default 0
-	format "0x%x"
-	export used
-	comment "Size of area to cache during coreboot execution directly from ROM"
-end
-define CONFIG_COMPRESS
-	default 1
-	export always
-	comment "Set for compressed image"
-end
-define CONFIG_UNCOMPRESSED
-	format "%d"
-	default {!CONFIG_COMPRESS}
-	export always
-	comment "Set for uncompressed image"
-end
-define CONFIG_RAMTOP
-	format "%d"
-	default 2048*1024
-	export always
-	comment "Highest RAM that coreboot_ram will use"
-end
-define CONFIG_HAVE_OPTION_TABLE
-	default 0
-	export always
-	comment "Export CMOS option table"
-end
-define CONFIG_USE_OPTION_TABLE
-	format "%d"
-	default {CONFIG_HAVE_OPTION_TABLE && !CONFIG_USE_FALLBACK_IMAGE}
-	export always
-	comment "Use option table"
-end
-
-###############################################
-# CMOS variable options
-###############################################
-define CONFIG_LB_CKS_RANGE_START
-	default 49
-	format "%d"
-	export always
-	comment "First CMOS byte to use for coreboot options"
-end
-define CONFIG_LB_CKS_RANGE_END
-	default 125
-	format "%d"
-	export always
-	comment "Last CMOS byte to use for coreboot options"
-end
-define CONFIG_LB_CKS_LOC
-	default 126
-	format "%d"
-	export always
-	comment "Pair of bytes to use for CMOS checksum"
-end
-
-
-###############################################
-# Build targets
-###############################################
-
-define CONFIG_CRT0
-	default "$(TOP)/src/arch/$(CONFIG_ARCH)/init/crt0.S.lb"
-	export always
-	comment "Main initialization target"
-end
-
-###############################################
-# Debugging/Logging options
-###############################################
-
-define CONFIG_DEBUG
-	default 0
-	export always
-	comment "Enable x86emu debugging code"
-end
-define CONFIG_VGA_BRIDGE_SETUP
-	default 1
-	export always
-	comment "Set bridge bits to enable legacy VGA ranges"
-end
-define CONFIG_CONSOLE_VGA
-	default 0
-	export always
-	comment "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"
-end
-define CONFIG_CONSOLE_VGA_MULTI
-        default 0
-        export always
-        comment "Multi VGA console"
-end
-define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
-        default 0
-        export always
-        comment "Use onboard VGA instead of add on VGA card"
-end
-define CONFIG_CONSOLE_BTEXT
-        default 0
-        export always
-        comment "Log messages to btext fb console"
-end
-define CONFIG_CONSOLE_LOGBUF
-	default 0
-	export always
-	comment "Log messages to buffer"
-end
-define CONFIG_CONSOLE_SROM
-	default 0
-	export always
-	comment "Log messages to SROM console"
-end
-define CONFIG_CONSOLE_SERIAL8250
-	default 0
-	export always
-	comment "Log messages to 8250 uart based serial console"
-end
-define CONFIG_USBDEBUG_DIRECT
-	default 0
-	export always
-	comment "Log messages to ehci debug port console"
-end
-define CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-	default 7
-	export always
-	comment "Console will log at this level unless changed"
-end
-define CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-	default 8
-	export always
- 	comment "Error messages up to this level can be printed"
-end
-define CONFIG_SERIAL_POST
-	default 0
-	export always
-	comment "Enable SERIAL POST codes"
-end
-define CONFIG_NO_POST
-	default none
-	export used
-	comment "Disable POST codes"
-end
-define CONFIG_TTYS0_BASE
-	default 0x3f8
-	format "0x%x"
-	export always
-	comment "Base address for 8250 uart for the serial console"
-end
-define CONFIG_TTYS0_BAUD
-	default 115200
-	export always
-	comment "Default baud rate for serial console"
-end
-define CONFIG_TTYS0_DIV
-	default none
-	format "%d"
-	export used
-	comment "Allow UART divisor to be set explicitly"
-end
-define CONFIG_TTYS0_LCS
-	default 0x3
-	format "0x%x"
-	export always
-	comment "Default flow control settings for the 8250 serial console uart"
-end
-
-define CONFIG_USE_PRINTK_IN_CAR
-	default 0
-	export always
-	comment "use printk instead of print in CAR stage code"
-end
-define CONFIG_ASSEMBLER_DEBUG
-	default 0
-	export always
-	comment "Create disassembly files for debugging"
-end
-
-###############################################
-# Mainboard options
-###############################################
-
-define CONFIG_MAINBOARD
-	default "Mainboard_not_set"
-	export always
-	comment "Mainboard name"
-end
-define CONFIG_MAINBOARD_PART_NUMBER
-	default "Part_number_not_set"
-	export always
-	format "\"%s\""
-	comment "Part number of mainboard"
-end
-define CONFIG_MAINBOARD_VENDOR
-	default "Vendor_not_set"
-	export always
-	format "\"%s\""
-	comment "Vendor of mainboard"
-end
-define CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	default 0
-	export always
-	comment "PCI Vendor ID of mainboard manufacturer"
-end
-define CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	default 0
-	format "0x%x"
-	export always
-	comment "PCI susbsystem device id assigned my mainboard manufacturer"
-end
-define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-	default none
-	export used
-	comment "Default power on after power fail setting"
-end
-define CONFIG_SYS_CLK_FREQ
-	default none
-	export used
-	comment "System clock frequency in MHz"
-end
-define CONFIG_EPIA_VT8237R_INIT
-	default none
-	export used
-	comment "Enable EPIA Specific Initialisation of VT8237R SB" 
-end
-###############################################
-# SMP options
-###############################################
-
-define CONFIG_SMP
-	default 0
-	export always
-	comment "Define if we support SMP"
-end
-define CONFIG_MAX_CPUS
-        default 1
-        export always
-        comment "Maximum CPU count for this machine"
-end
-define CONFIG_MAX_PHYSICAL_CPUS
-        default 1
-        export always
-        comment "Maximum physical CPU count for this machine"
-end
-define CONFIG_LOGICAL_CPUS
-	default 0
-	export always
-	comment "Should multiple cpus per die be enabled?"
-end
-define CONFIG_AP_IN_SIPI_WAIT
-	default 0
-	export always
-	comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)"
-end
-define CONFIG_GENERATE_MP_TABLE
-	default none
-	export used
-	comment "Define to build an MP table"
-end
-define CONFIG_SERIAL_CPU_INIT
-        default 1
-        export always
-        comment "Serialize CPU init"
-end
-define CONFIG_APIC_ID_OFFSET
-	default 0
-	export always
-	comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
-end
-define CONFIG_ENABLE_APIC_EXT_ID
-	default 0
-	export always
-	comment "Enable APIC ext id mode 8 bit"
-end
-define CONFIG_LIFT_BSP_APIC_ID
-	default 0
-	export always
-	comment "decide if we lift bsp apic id while ap apic id"
-end
-###############################################
-# Boot options
-###############################################
-
-define CONFIG_MULTIBOOT
-	default 1
-	export always
-	comment "Use Multiboot (rather than ELF boot notes) to boot the payload"
-end
-define CONFIG_ROM_PAYLOAD
-	default 0
-	export always
-	comment "Boot image is located in ROM" 
-end
-define CONFIG_COMPRESSED_PAYLOAD_NRV2B
-	default 0
-	export always
-	comment "NRV2B compressed boot image is located in ROM" 
-end
-define CONFIG_COMPRESSED_PAYLOAD_LZMA
-	default 0
-	export always
-	comment "LZMA compressed boot image is located in ROM" 
-end
-define CONFIG_PRECOMPRESSED_PAYLOAD
-	default 0
-	export always
-	comment "boot image is already compressed" 
-end
-
-define CONFIG_USE_WATCHDOG_ON_BOOT
-	default 0
-	export always
-	comment "Use the watchdog on booting"
-end
-
-###############################################
-# Plugin Device support options
-###############################################
-
-define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
-	default 1
-	export always
-	comment "Enable support for plugin Hypertransport busses"
-end
-define CONFIG_AGP_PLUGIN_SUPPORT
-	default 1
-	export always
-	comment "Enable support for plugin AGP busses"
-end
-define CONFIG_CARDBUS_PLUGIN_SUPPORT
-	default 1
-	export always
-	comment "Enable support cardbus plugin cards"
-end
-define CONFIG_PCIX_PLUGIN_SUPPORT
-	default 1
-	export always
-	comment "Enable support for plugin PCI-X busses"
-end
-define CONFIG_PCIEXP_PLUGIN_SUPPORT
-	default 1
-	export always
-	comment "Enable support for plugin PCI-E busses"
-end
-
-###############################################
-# IRQ options
-###############################################
-
-define CONFIG_GENERATE_PIRQ_TABLE
-	default none
-	export used
-	comment "Define if we have a PIRQ table"
-end
-define CONFIG_PIRQ_ROUTE
-	default 0
-	export always
-	comment "Define if we have a PIRQ table and want routing IRQs"
-end
-define CONFIG_IRQ_SLOT_COUNT
-	default none
-	export used
-	comment "Number of IRQ slots"
-end
-define CONFIG_PCIBIOS_IRQ
-	default none
-	export used
-	comment "PCIBIOS IRQ support"
-end
-define CONFIG_IOAPIC
-	default 0
-	export always
-	comment "IOAPIC support"
-end
-
-###############################################
-# Options for memory mapped I/O
-###############################################
-
-define CONFIG_PCI_IO_CFG_EXT
-	default 0
-	export always
-	comment "allow 4K register space via io CFG port"
-end
-
-define CONFIG_PCIC0_CFGADDR
-	default none
-	format "0x%x"
-	export used
-	comment "Address of PCI Configuration Address Register"
-end
-define CONFIG_PCIC0_CFGDATA
-	default none
-	format "0x%x"
-	export used
-	comment "Address of PCI Configuration Data Register"
-end
-define CONFIG_ISA_IO_BASE
-	default none
-	format "0x%x"
-	export used
-	comment "Base address of PCI/ISA I/O address range"
-end
-define CONFIG_ISA_MEM_BASE
-	default none
-	format "0x%x"
-	export used
-	comment "Base address of PCI/ISA memory address range"
-end
-define CONFIG_PNP_CFGADDR
-	default none
-	format "0x%x"
-	export used
-	comment "PNP Configuration Address Register offset"
-end
-define CONFIG_PNP_CFGDATA
-	default none
-	format "0x%x"
-	export used
-	comment "PNP Configuration Data Register offset"
-end
-define CONFIG_IO_BASE
-	default none
-	format "0x%x"
-	export used
-	comment "Base address of memory mapped I/O operations"
-end
-
-###############################################
-# Options for embedded systems
-###############################################
-
-define CONFIG_EMBEDDED_RAM_SIZE
-	default none
-	export used
-	comment "Embedded boards generally have fixed RAM size"
-end
-
-###############################################
-# Misc options
-###############################################
-
-define CONFIG_GDB_STUB
-	default 0
-	export used
-	comment "Compile in gdb stub support?"
-end
-
-define CONFIG_HAVE_INIT_TIMER
-	default 0
-	export always
-	comment "Have a init_timer function"
-end
-define CONFIG_HAVE_HARD_RESET
-	default none
-	export used
-	comment "Have hard reset"
-end
-define CONFIG_HAVE_SMI_HANDLER
-	default 0
-	export always
-	comment "Set, if the board needs an SMI handler"
-end
-define CONFIG_MEMORY_HOLE
-	default none
-	export used
-	comment "Set to deal with memory hole"
-end
-define CONFIG_MAX_REBOOT_CNT
-	default 3
-	export always
-	comment "Set maximum reboots"
-end
-
-###############################################
-# Misc device options
-###############################################
-
-define CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
-	default 0
-	export used
-	comment "Include board specific FAN control initialization"
-end
-define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-	default 0
-	export used
-	comment "Use timer2 to callibrate the x86 time stamp counter"
-end
-define CONFIG_INTEL_PPRO_MTRR
-	default none
-	export used
-	comment ""
-end
-define CONFIG_UDELAY_TSC
-	default 0
-	export used
-	comment "Implement udelay with the x86 time stamp counter"
-end
-define CONFIG_UDELAY_IO
-	default 0
-	export used
-	comment "Implement udelay with x86 io registers"
-end
-define CONFIG_UDELAY_LAPIC
-	default 0
-	export used
-	comment "Implement udelay with the x86 Local APIC"
-end
-
-define CONFIG_GENERATE_ACPI_TABLES
-	default 0
-	export always
-	comment "Define to build ACPI tables"
-end
-
-define CONFIG_HAVE_ACPI_RESUME
-	default 0
-	export always
-	comment "Define to build ACPI with resume support"
-end
-
-define CONFIG_ACPI_SSDTX_NUM
-	default 0
-	export always
-	comment "extra ssdt num for PCI Device"
-end
-
-define CONFIG_AGP_APERTURE_SIZE
-	default none
-	export used
-	format "0x%x"
-	comment "AGP graphics virtual memory aperture size"
-end
-
-define CONFIG_HT_CHAIN_UNITID_BASE
-	default 1
-	export always
-	comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
-end
-
-define CONFIG_HT_CHAIN_END_UNITID_BASE
-        default 0x20
-        export always
-        comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than CONFIG_HT_CHAIN_UNITID_BASE, it could be 0"
-end
-
-define CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-        default 1
-        export always
-        comment "this will decided if only offset SB hypertransport chain"
-end
-
-define CONFIG_SB_HT_CHAIN_ON_BUS0
-        default 0 
-        export always
-        comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
-end
-
-define CONFIG_PCI_BUS_SEGN_BITS
-        default 0
-        export always
-        comment "It could be 0, 1, 2, 3 and 4 only"
-end
-
-define CONFIG_MMCONF_SUPPORT
-	default 0
-	export always
-	comment "enable mmconfig for pci conf"
-end
-
-define CONFIG_MMCONF_SUPPORT_DEFAULT
-	default 0
-	export always
-	comment "enable mmconfig for pci conf"
-end
-
-define CONFIG_MMCONF_BASE_ADDRESS
-	default none
-	format "0x%x"
-	export used
-	comment "enable mmconfig base address"
-end
-
-define CONFIG_HW_MEM_HOLE_SIZEK
-        default 0
-        export always
-        comment "Opteron E0 later memory hole size in K, 0 mean disable"
-end
-
-define CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-        default 0
-        export always
-        comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
-end
-
-define CONFIG_VAR_MTRR_HOLE
-	default 1
-	export always
-	comment "using hole in MTRR instead of increasing method"
-end
-
-define CONFIG_K8_HT_FREQ_1G_SUPPORT
-	default 0 
-	export always
-	comment "Optern E0 later could support 1G HT, but still depends MB design"
-end
-
-define CONFIG_K8_REV_F_SUPPORT
-        default 0
-        export always
-        comment "Opteron Rev F (DDR2) support"
-end
-
-define CONFIG_CBB
-	default 0
-	export always
-	comment "Opteron cpu bus num base"
-end
-
-define CONFIG_CDB
-	default 0x18
-	export always
-	comment "Opteron cpu device num base"
-end
-
-define CONFIG_HT3_SUPPORT
-	default 0
-	export always
-	comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
-end
-
-define CONFIG_EXT_RT_TBL_SUPPORT
-	default 0
-	export always
-	comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
-end
-
-define CONFIG_EXT_CONF_SUPPORT
-	default 0
-	export always
-	comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
-end
-
-define CONFIG_DIMM_SUPPORT
-        default 0x0108
-	format "0x%x"
-        export always
-        comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
-end
-
-define CONFIG_CPU_SOCKET_TYPE
-	default 0x10
-	export always
-	comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
-end
-
-define CONFIG_CPU_ADDR_BITS
-	default 36
-	export always
-	comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
-end
-
-define CONFIG_VGA
-	default 0
-	export always
-	comment "Include VGA initialisation code"
-end
-
-define CONFIG_VGA_ROM_RUN
-	default 0
-	export always
-	comment "Init x86 ROMs on VGA-class PCI devices"
-end
-
-define CONFIG_PCI_ROM_RUN
-	default 0
-	export always
-	comment "Init x86 ROMs on all PCI devices"
-end
-
-define CONFIG_PCI_OPTION_ROM_RUN_YABEL
-	default 0
-	export used
-	comment "Use Yabel instead of old bios emulator"
-end
-
-define CONFIG_YABEL_DEBUG_FLAGS
-	default 0
-	export used
-	comment "YABEL debug flags, for possible values, see util/x86emu/yabel/debug.h"
-end
-
-define CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES
-	default 0
-	export used
-	comment "Allow Option ROMs executed by YABEL to access the config space of devices other than the one YABEL is running for. This may be needed by some onboard Graphics cards ROMs."
-
-end
-
-define CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-	default 0
-	export used
-	comment "Use Yabel instead of old bios emulator"
-end
-
-define CONFIG_PCI_64BIT_PREF_MEM
-        default 0
-        export always
-        comment "allow PCI device get 4G above Region as pref mem"
-end
-
-define CONFIG_AMDMCT
-	default 0
-	export always
-	comment "use AMD MCT to init RAM instead of native code"
-end
-
-define CONFIG_AMD_UCODE_PATCH_FILE
-	default none
-	export used
-	format "\"%s\""
-	comment "name of the microcode patch file"	
-end
-
-define CONFIG_K8_MEM_BANK_B_ONLY
-	default 0
-	export always
-	comment "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert."
-end
-
-define CONFIG_VIDEO_MB
-        default 0
-        export always
-        comment "Integrated graphics with UMA has dynamic setup"
-end
-
-define CONFIG_GFXUMA
-        default 0
-        export always
-        comment "GFX UMA"
-end
-
-define CONFIG_HAVE_MAINBOARD_RESOURCES
-	default 0
-	export always
-	comment "Enable if the mainboard/chipset requires extra entries in the memory map"
-end
-
-define CONFIG_HAVE_LOW_TABLES
-	default 1
-	export always
-	comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte"
-end
-
-define CONFIG_WRITE_HIGH_TABLES
-	default 0
-	export always
-	comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory"
-end
-
-define CONFIG_SPLASH_GRAPHIC
-	default 0
-	export used
-	comment "Paint a splash screen"
-end
-
-define CONFIG_GX1_VIDEO
-	default 0
-	export used
-	comment "Build in GX1's graphic support"
-end
-
-define CONFIG_GX1_VIDEOMODE
-	default none
-	export used
-	comment "Define video mode after reset"
-# could be
-# 0 for 640x480
-# 1 for 800x600
-# 2 for 1024x768
-# 3 for 1280x960
-# 4 for 1280x1024
-end
-
-define CONFIG_PCIE_CONFIGSPACE_HOLE
-	default 0
-	export always
-	comment "Leave a hole for PCIe config space in the device allocator"
-end
-
-define CONFIG_ID_SECTION_OFFSET
-	default 0x10
-	export always
-	comment "Offset of the .id section. Only needs to change if something like a romstrap is in the way"
-end
diff --git a/src/console/Config.lb b/src/console/Config.lb
deleted file mode 100644
index eda9cf4..0000000
--- a/src/console/Config.lb
+++ /dev/null
@@ -1,31 +0,0 @@
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_USBDEBUG_DIRECT
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_CONSOLE_LOGBUF
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-object printk.o
-if CONFIG_CONSOLE_SERIAL8250
-	driver uart8250_console.o
-end
-if CONFIG_USBDEBUG_DIRECT
-	driver usbdebug_direct_console.o
-end
-if CONFIG_CONSOLE_VGA
-	driver vga_console.o
-end
-if CONFIG_CONSOLE_BTEXT
-	driver btext_console.o
-	driver font-8x16.o
-end
-if CONFIG_CONSOLE_LOGBUF
-	driver logbuf_console.o
-end
-
-object console.o
-object vtxprintf.o
-object vsprintf.o
-
-initobject vtxprintf.o
diff --git a/src/cpu/amd/dualcore/Config.lb b/src/cpu/amd/dualcore/Config.lb
deleted file mode 100644
index acc5d2e..0000000
--- a/src/cpu/amd/dualcore/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object amd_sibling.o
diff --git a/src/cpu/amd/microcode/Config.lb b/src/cpu/amd/microcode/Config.lb
deleted file mode 100644
index f19d210..0000000
--- a/src/cpu/amd/microcode/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object microcode.o
\ No newline at end of file
diff --git a/src/cpu/amd/model_10xxx/Config.lb b/src/cpu/amd/model_10xxx/Config.lb
deleted file mode 100644
index 47f1600..0000000
--- a/src/cpu/amd/model_10xxx/Config.lb
+++ /dev/null
@@ -1,38 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_HAVE_MOVNTI
-uses CONFIG_CPU_ADDR_BITS
-
-default CONFIG_HAVE_INIT_TIMER=1
-default CONFIG_HAVE_MOVNTI=1
-default CONFIG_CPU_ADDR_BITS=48
-dir /cpu/x86/tsc
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/pae
-dir /cpu/x86/smm
-dir /cpu/amd/mtrr
-dir /cpu/amd/quadcore
-dir /cpu/amd/microcode
-driver model_10xxx_init.o
-object update_microcode.o
-object apic_timer.o
-object processor_name.o
diff --git a/src/cpu/amd/model_fxx/Config.lb b/src/cpu/amd/model_fxx/Config.lb
deleted file mode 100644
index fad7560..0000000
--- a/src/cpu/amd/model_fxx/Config.lb
+++ /dev/null
@@ -1,20 +0,0 @@
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_HAVE_MOVNTI
-uses CONFIG_CPU_ADDR_BITS
-
-default CONFIG_HAVE_INIT_TIMER=1
-default CONFIG_HAVE_MOVNTI=1
-default CONFIG_CPU_ADDR_BITS=40
-dir /cpu/x86/tsc
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/pae
-dir /cpu/x86/smm
-dir /cpu/amd/mtrr
-dir /cpu/amd/dualcore
-dir /cpu/amd/microcode
-driver model_fxx_init.o
-object apic_timer.o
-object model_fxx_update_microcode.o
-object processor_name.o
-object powernow_acpi.o
diff --git a/src/cpu/amd/model_gx1/Config.lb b/src/cpu/amd/model_gx1/Config.lb
deleted file mode 100644
index d04be3d..0000000
--- a/src/cpu/amd/model_gx1/Config.lb
+++ /dev/null
@@ -1,5 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-driver model_gx1_init.o
diff --git a/src/cpu/amd/model_gx2/Config.lb b/src/cpu/amd/model_gx2/Config.lb
deleted file mode 100644
index 0f57790..0000000
--- a/src/cpu/amd/model_gx2/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-driver model_gx2_init.o
-object cpubug.o
-object vsmsetup.o
diff --git a/src/cpu/amd/model_lx/Config.lb b/src/cpu/amd/model_lx/Config.lb
deleted file mode 100644
index 25324e7..0000000
--- a/src/cpu/amd/model_lx/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-driver model_lx_init.o
-object cpubug.o
-object vsmsetup.o
diff --git a/src/cpu/amd/mtrr/Config.lb b/src/cpu/amd/mtrr/Config.lb
deleted file mode 100644
index f042c2c..0000000
--- a/src/cpu/amd/mtrr/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-dir /cpu/x86/mtrr
-object amd_mtrr.o
diff --git a/src/cpu/amd/quadcore/Config.lb b/src/cpu/amd/quadcore/Config.lb
deleted file mode 100644
index 680436f..0000000
--- a/src/cpu/amd/quadcore/Config.lb
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-object amd_sibling.o
diff --git a/src/cpu/amd/sc520/Config.lb b/src/cpu/amd/sc520/Config.lb
deleted file mode 100644
index 10bb996..0000000
--- a/src/cpu/amd/sc520/Config.lb
+++ /dev/null
@@ -1,3 +0,0 @@
-config chip.h
-object sc520.o
-
diff --git a/src/cpu/amd/socket_754/Config.lb b/src/cpu/amd/socket_754/Config.lb
deleted file mode 100644
index bd96105..0000000
--- a/src/cpu/amd/socket_754/Config.lb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-config chip.h
-object socket_754.o
-dir /cpu/amd/model_fxx
diff --git a/src/cpu/amd/socket_939/Config.lb b/src/cpu/amd/socket_939/Config.lb
deleted file mode 100644
index 963a27e..0000000
--- a/src/cpu/amd/socket_939/Config.lb
+++ /dev/null
@@ -1,5 +0,0 @@
-config chip.h
-
-object socket_939.o
-
-dir /cpu/amd/model_fxx
diff --git a/src/cpu/amd/socket_940/Config.lb b/src/cpu/amd/socket_940/Config.lb
deleted file mode 100644
index 34d1405..0000000
--- a/src/cpu/amd/socket_940/Config.lb
+++ /dev/null
@@ -1,5 +0,0 @@
-config chip.h
-
-object socket_940.o
-
-dir /cpu/amd/model_fxx
diff --git a/src/cpu/amd/socket_AM2/Config.lb b/src/cpu/amd/socket_AM2/Config.lb
deleted file mode 100644
index 095643b..0000000
--- a/src/cpu/amd/socket_AM2/Config.lb
+++ /dev/null
@@ -1,16 +0,0 @@
-uses CONFIG_K8_REV_F_SUPPORT
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_DIMM_SUPPORT
-uses CONFIG_CPU_SOCKET_TYPE
-
-config chip.h
-
-default CONFIG_K8_REV_F_SUPPORT=1
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-default CONFIG_DIMM_SUPPORT=0x0004  #DDR2 unbuffered
-default CONFIG_CPU_SOCKET_TYPE=0x11
-
-object socket_AM2.o
-
-dir /cpu/amd/model_fxx
diff --git a/src/cpu/amd/socket_AM2r2/Config.lb b/src/cpu/amd/socket_AM2r2/Config.lb
deleted file mode 100644
index 2d3d12e..0000000
--- a/src/cpu/amd/socket_AM2r2/Config.lb
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-uses CONFIG_PCI_IO_CFG_EXT
-uses CONFIG_MMCONF_SUPPORT
-uses CONFIG_HT3_SUPPORT
-uses CONFIG_EXT_RT_TBL_SUPPORT
-uses CONFIG_EXT_CONF_SUPPORT
-uses CONFIG_DIMM_SUPPORT
-uses CONFIG_CPU_SOCKET_TYPE
-uses CONFIG_CBB
-uses CONFIG_CDB
-uses CONFIG_PCI_BUS_SEGN_BITS
-
-config chip.h
-
-default CONFIG_PCI_IO_CFG_EXT=1
-
-default CONFIG_HT3_SUPPORT=1
-default CONFIG_EXT_RT_TBL_SUPPORT=0
-default CONFIG_EXT_CONF_SUPPORT=0
-default CONFIG_DIMM_SUPPORT=0x0104  #DDR2 and REG
-default CONFIG_CPU_SOCKET_TYPE=0x11
-
-if CONFIG_EXT_RT_TBL_SUPPORT
-	default CONFIG_CBB=0xff
-	default CONFIG_CDB=0
-end
-
-#default CONFIG_MMCONF_SUPPORT=1
-#default CONFIG_MMCONF_SUPPORT_DEFAULT=1
-
-object socket_AM2r2.o
-
-dir /cpu/amd/model_10xxx
diff --git a/src/cpu/amd/socket_F/Config.lb b/src/cpu/amd/socket_F/Config.lb
deleted file mode 100644
index 72f2a1b..0000000
--- a/src/cpu/amd/socket_F/Config.lb
+++ /dev/null
@@ -1,16 +0,0 @@
-uses CONFIG_K8_REV_F_SUPPORT
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_DIMM_SUPPORT
-uses CONFIG_CPU_SOCKET_TYPE
-
-config chip.h
-
-default CONFIG_K8_REV_F_SUPPORT=1
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-default CONFIG_DIMM_SUPPORT=0x0104  #DDR2 and REG
-default CONFIG_CPU_SOCKET_TYPE=0x10
-
-object socket_F.o
-
-dir /cpu/amd/model_fxx
diff --git a/src/cpu/amd/socket_F_1207/Config.lb b/src/cpu/amd/socket_F_1207/Config.lb
deleted file mode 100644
index 447b6cb..0000000
--- a/src/cpu/amd/socket_F_1207/Config.lb
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-uses CONFIG_PCI_IO_CFG_EXT
-uses CONFIG_MMCONF_SUPPORT
-uses CONFIG_HT3_SUPPORT
-uses CONFIG_EXT_RT_TBL_SUPPORT
-uses CONFIG_EXT_CONF_SUPPORT
-uses CONFIG_DIMM_SUPPORT
-uses CONFIG_CPU_SOCKET_TYPE
-uses CONFIG_CBB
-uses CONFIG_CDB
-uses CONFIG_PCI_BUS_SEGN_BITS
-
-config chip.h
-
-default CONFIG_PCI_IO_CFG_EXT=1
-
-default CONFIG_HT3_SUPPORT=1
-default CONFIG_EXT_RT_TBL_SUPPORT=0
-default CONFIG_EXT_CONF_SUPPORT=0
-default CONFIG_DIMM_SUPPORT=0x0104  #DDR2 and REG
-default CONFIG_CPU_SOCKET_TYPE=0x10
-
-if CONFIG_EXT_RT_TBL_SUPPORT
-	default CONFIG_CBB=0xff
-	default CONFIG_CDB=0
-end
-
-#default CONFIG_MMCONF_SUPPORT=1
-#default CONFIG_MMCONF_SUPPORT_DEFAULT=1
-
-object socket_F_1207.o
-
-dir /cpu/amd/model_10xxx
diff --git a/src/cpu/amd/socket_S1G1/Config.lb b/src/cpu/amd/socket_S1G1/Config.lb
deleted file mode 100644
index 6aa6b5a..0000000
--- a/src/cpu/amd/socket_S1G1/Config.lb
+++ /dev/null
@@ -1,16 +0,0 @@
-uses CONFIG_K8_REV_F_SUPPORT
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_DIMM_SUPPORT
-uses CONFIG_CPU_SOCKET_TYPE
-
-config chip.h
-
-default CONFIG_K8_REV_F_SUPPORT=1
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-default CONFIG_DIMM_SUPPORT=0x0204  #DDR2 and REG, S1G1
-default CONFIG_CPU_SOCKET_TYPE=0x12
-
-object socket_S1G1.o
-
-dir /cpu/amd/model_fxx
diff --git a/src/cpu/emulation/qemu-x86/Config.lb b/src/cpu/emulation/qemu-x86/Config.lb
deleted file mode 100644
index 4a0c2c8..0000000
--- a/src/cpu/emulation/qemu-x86/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object northbridge.o
diff --git a/src/cpu/intel/bga956/Config.lb b/src/cpu/intel/bga956/Config.lb
deleted file mode 100644
index f334dce..0000000
--- a/src/cpu/intel/bga956/Config.lb
+++ /dev/null
@@ -1,3 +0,0 @@
-config chip.h
-object bga956.o
-dir /cpu/intel/model_1067x
diff --git a/src/cpu/intel/ep80579/Config.lb b/src/cpu/intel/ep80579/Config.lb
deleted file mode 100644
index 04d2e3f..0000000
--- a/src/cpu/intel/ep80579/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object ep80579.o
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver ep80579_init.o
diff --git a/src/cpu/intel/hyperthreading/Config.lb b/src/cpu/intel/hyperthreading/Config.lb
deleted file mode 100644
index dce4044..0000000
--- a/src/cpu/intel/hyperthreading/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object intel_sibling.o
diff --git a/src/cpu/intel/microcode/Config.lb b/src/cpu/intel/microcode/Config.lb
deleted file mode 100644
index f19d210..0000000
--- a/src/cpu/intel/microcode/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object microcode.o
\ No newline at end of file
diff --git a/src/cpu/intel/model_1067x/Config.lb b/src/cpu/intel/model_1067x/Config.lb
deleted file mode 100644
index 71b83a4..0000000
--- a/src/cpu/intel/model_1067x/Config.lb
+++ /dev/null
@@ -1,11 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-driver model_1067x_init.o
diff --git a/src/cpu/intel/model_106cx/Config.lb b/src/cpu/intel/model_106cx/Config.lb
deleted file mode 100644
index 1df2919..0000000
--- a/src/cpu/intel/model_106cx/Config.lb
+++ /dev/null
@@ -1,31 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-dir /cpu/intel/speedstep
-driver model_106cx_init.o
diff --git a/src/cpu/intel/model_69x/Config.lb b/src/cpu/intel/model_69x/Config.lb
deleted file mode 100644
index c558cd0..0000000
--- a/src/cpu/intel/model_69x/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_69x_init.o
diff --git a/src/cpu/intel/model_6dx/Config.lb b/src/cpu/intel/model_6dx/Config.lb
deleted file mode 100644
index 802dcd0..0000000
--- a/src/cpu/intel/model_6dx/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_6dx_init.o
diff --git a/src/cpu/intel/model_6ex/Config.lb b/src/cpu/intel/model_6ex/Config.lb
deleted file mode 100644
index 1dac2f2..0000000
--- a/src/cpu/intel/model_6ex/Config.lb
+++ /dev/null
@@ -1,12 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-dir /cpu/intel/speedstep
-driver model_6ex_init.o
diff --git a/src/cpu/intel/model_6fx/Config.lb b/src/cpu/intel/model_6fx/Config.lb
deleted file mode 100644
index ae3b6bd..0000000
--- a/src/cpu/intel/model_6fx/Config.lb
+++ /dev/null
@@ -1,11 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-driver model_6fx_init.o
diff --git a/src/cpu/intel/model_6xx/Config.lb b/src/cpu/intel/model_6xx/Config.lb
deleted file mode 100644
index 3419512..0000000
--- a/src/cpu/intel/model_6xx/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_6xx_init.o
diff --git a/src/cpu/intel/model_f0x/Config.lb b/src/cpu/intel/model_f0x/Config.lb
deleted file mode 100644
index b790c72..0000000
--- a/src/cpu/intel/model_f0x/Config.lb
+++ /dev/null
@@ -1,9 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_f0x_init.o
diff --git a/src/cpu/intel/model_f1x/Config.lb b/src/cpu/intel/model_f1x/Config.lb
deleted file mode 100644
index 26fbeef..0000000
--- a/src/cpu/intel/model_f1x/Config.lb
+++ /dev/null
@@ -1,9 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_f1x_init.o
diff --git a/src/cpu/intel/model_f2x/Config.lb b/src/cpu/intel/model_f2x/Config.lb
deleted file mode 100644
index 7843d4a..0000000
--- a/src/cpu/intel/model_f2x/Config.lb
+++ /dev/null
@@ -1,10 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-driver model_f2x_init.o
diff --git a/src/cpu/intel/model_f3x/Config.lb b/src/cpu/intel/model_f3x/Config.lb
deleted file mode 100644
index 214c689..0000000
--- a/src/cpu/intel/model_f3x/Config.lb
+++ /dev/null
@@ -1,10 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-driver model_f3x_init.o
diff --git a/src/cpu/intel/model_f4x/Config.lb b/src/cpu/intel/model_f4x/Config.lb
deleted file mode 100644
index adfc7d2..0000000
--- a/src/cpu/intel/model_f4x/Config.lb
+++ /dev/null
@@ -1,10 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-driver model_f4x_init.o
diff --git a/src/cpu/intel/slot_2/Config.lb b/src/cpu/intel/slot_2/Config.lb
deleted file mode 100644
index f39eb77..0000000
--- a/src/cpu/intel/slot_2/Config.lb
+++ /dev/null
@@ -1,3 +0,0 @@
-config chip.h
-object slot_2.o
-dir /cpu/intel/model_6xx
diff --git a/src/cpu/intel/socket_441/Config.lb b/src/cpu/intel/socket_441/Config.lb
deleted file mode 100644
index 6e8b65e..0000000
--- a/src/cpu/intel/socket_441/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object socket_441.o
-dir /cpu/intel/model_106cx
diff --git a/src/cpu/intel/socket_PGA370/Config.lb b/src/cpu/intel/socket_PGA370/Config.lb
deleted file mode 100644
index 8db263b..0000000
--- a/src/cpu/intel/socket_PGA370/Config.lb
+++ /dev/null
@@ -1,3 +0,0 @@
-config chip.h
-object socket_PGA370.o
-dir /cpu/intel/model_6xx
diff --git a/src/cpu/intel/socket_mFCPGA478/Config.lb b/src/cpu/intel/socket_mFCPGA478/Config.lb
deleted file mode 100644
index baeda00..0000000
--- a/src/cpu/intel/socket_mFCPGA478/Config.lb
+++ /dev/null
@@ -1,6 +0,0 @@
-config chip.h
-object socket_mFCPGA478.o
-dir /cpu/intel/model_69x
-dir /cpu/intel/model_6dx
-dir /cpu/intel/model_6ex
-dir /cpu/intel/model_6fx
diff --git a/src/cpu/intel/socket_mPGA478/Config.lb b/src/cpu/intel/socket_mPGA478/Config.lb
deleted file mode 100644
index a68eeeb..0000000
--- a/src/cpu/intel/socket_mPGA478/Config.lb
+++ /dev/null
@@ -1,4 +0,0 @@
-config chip.h
-object socket_mPGA478.o
-dir /cpu/intel/model_69x
-dir /cpu/intel/model_6dx
diff --git a/src/cpu/intel/socket_mPGA479M/Config.lb b/src/cpu/intel/socket_mPGA479M/Config.lb
deleted file mode 100644
index 70eda9a..0000000
--- a/src/cpu/intel/socket_mPGA479M/Config.lb
+++ /dev/null
@@ -1,4 +0,0 @@
-config chip.h
-object socket_mPGA479M.o
-dir /cpu/intel/model_69x
-dir /cpu/intel/model_6dx
diff --git a/src/cpu/intel/socket_mPGA603/Config.lb b/src/cpu/intel/socket_mPGA603/Config.lb
deleted file mode 100644
index fa66e44..0000000
--- a/src/cpu/intel/socket_mPGA603/Config.lb
+++ /dev/null
@@ -1,6 +0,0 @@
-config chip.h
-object socket_mPGA603_400Mhz.o
-dir /cpu/intel/model_f0x
-dir /cpu/intel/model_f1x
-dir /cpu/intel/model_f2x
-
diff --git a/src/cpu/intel/socket_mPGA604/Config.lb b/src/cpu/intel/socket_mPGA604/Config.lb
deleted file mode 100644
index 21276eb..0000000
--- a/src/cpu/intel/socket_mPGA604/Config.lb
+++ /dev/null
@@ -1,5 +0,0 @@
-config chip.h
-object socket_mPGA604.o
-dir /cpu/intel/model_f2x
-dir /cpu/intel/model_f3x
-dir /cpu/intel/model_f4x
diff --git a/src/cpu/intel/speedstep/Config.lb b/src/cpu/intel/speedstep/Config.lb
deleted file mode 100644
index 6a75160..0000000
--- a/src/cpu/intel/speedstep/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object acpi.o
diff --git a/src/cpu/via/model_c3/Config.lb b/src/cpu/via/model_c3/Config.lb
deleted file mode 100644
index 0bb6b96..0000000
--- a/src/cpu/via/model_c3/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# This file is part of the coreboot project.
-# 
-# (C) 2007-2008 coresystems GmbH
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_c3_init.o
diff --git a/src/cpu/via/model_c7/Config.lb b/src/cpu/via/model_c7/Config.lb
deleted file mode 100644
index de22d8a..0000000
--- a/src/cpu/via/model_c7/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# This file is part of the coreboot project.
-# 
-# (C) 2007-2008 coresystems GmbH
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; version 2 of
-# the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_c7_init.o
diff --git a/src/cpu/x86/cache/Config.lb b/src/cpu/x86/cache/Config.lb
deleted file mode 100644
index e39bb2d..0000000
--- a/src/cpu/x86/cache/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object cache.o
diff --git a/src/cpu/x86/lapic/Config.lb b/src/cpu/x86/lapic/Config.lb
deleted file mode 100644
index 9491687..0000000
--- a/src/cpu/x86/lapic/Config.lb
+++ /dev/null
@@ -1,11 +0,0 @@
-uses CONFIG_UDELAY_LAPIC
-
-object lapic.o
-object lapic_cpu_init.o
-object secondary.S
-
-if CONFIG_UDELAY_LAPIC
-	default CONFIG_HAVE_INIT_TIMER=1
-	object apic_timer.o
-end
-
diff --git a/src/cpu/x86/mtrr/Config.lb b/src/cpu/x86/mtrr/Config.lb
deleted file mode 100644
index df5c16f..0000000
--- a/src/cpu/x86/mtrr/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object mtrr.o
\ No newline at end of file
diff --git a/src/cpu/x86/pae/Config.lb b/src/cpu/x86/pae/Config.lb
deleted file mode 100644
index 45e7f57..0000000
--- a/src/cpu/x86/pae/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object pgtbl.o
\ No newline at end of file
diff --git a/src/cpu/x86/smm/Config.lb b/src/cpu/x86/smm/Config.lb
deleted file mode 100644
index f725581..0000000
--- a/src/cpu/x86/smm/Config.lb
+++ /dev/null
@@ -1,48 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_HAVE_SMI_HANDLER
-
-if CONFIG_HAVE_SMI_HANDLER
-	object smmrelocate.S
-
-	smmobject smmhandler.S
-	smmobject smihandler.o
-	smmobject smiutil.o
-
-	makerule smm.o
-		depends	"$(SMM-OBJECTS) src/console/printk.o src/console/vtxprintf.o $(LIBGCC_FILE_NAME)" 
-		action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^"
-	end
-
-	makerule smm
-		depends	"smm.o $(TOP)/src/cpu/x86/smm/smm.ld ldoptions" 
-		action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/cpu/x86/smm/smm.ld smm.o"
-		action 	"$(CONFIG_CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
-		action  "$(CONFIG_OBJCOPY) -O binary smm.elf smm"
-	end
-
-	makerule smm_bin.c
-		depends "smm"
-		action "(echo 'unsigned char smm[] = {'; od -vtx1 smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c smm |awk '{print $$1;}' ; echo ';')  > smm_bin.c"
-	end
-
-	object ./smm_bin.o
-end
diff --git a/src/cpu/x86/tsc/Config.lb b/src/cpu/x86/tsc/Config.lb
deleted file mode 100644
index 21aa9a4..0000000
--- a/src/cpu/x86/tsc/Config.lb
+++ /dev/null
@@ -1,9 +0,0 @@
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_HAVE_INIT_TIMER
-
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
-if CONFIG_UDELAY_TSC 
-	default CONFIG_HAVE_INIT_TIMER=1
-	object delay_tsc.o  
-end
diff --git a/src/devices/Config.lb b/src/devices/Config.lb
deleted file mode 100644
index a8c08d8..0000000
--- a/src/devices/Config.lb
+++ /dev/null
@@ -1,25 +0,0 @@
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VGA_ROM_RUN
-
-object device.o
-object root_device.o
-object device_util.o
-object pci_device.o
-object hypertransport.o
-object pcix_device.o
-object pciexp_device.o
-object agp_device.o
-object cardbus_device.o
-object pnp_device.o
-object pci_ops.o
-object smbus_ops.o
-
-if CONFIG_PCI_ROM_RUN
-	object pci_rom.o
-	dir ../../util/x86emu
-else
-if CONFIG_VGA_ROM_RUN
-	object pci_rom.o
-	dir ../../util/x86emu
-end
-end
diff --git a/src/drivers/ati/ragexl/Config.lb b/src/drivers/ati/ragexl/Config.lb
deleted file mode 100644
index dc9ca32..0000000
--- a/src/drivers/ati/ragexl/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver xlinit.o
diff --git a/src/drivers/emulation/qemu/Config.lb b/src/drivers/emulation/qemu/Config.lb
deleted file mode 100644
index 3a8d35a..0000000
--- a/src/drivers/emulation/qemu/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver init.o
diff --git a/src/drivers/generic/debug/Config.lb b/src/drivers/generic/debug/Config.lb
deleted file mode 100644
index df69ac1..0000000
--- a/src/drivers/generic/debug/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object debug_dev.o
diff --git a/src/drivers/generic/generic/Config.lb b/src/drivers/generic/generic/Config.lb
deleted file mode 100644
index e69de29..0000000
--- a/src/drivers/generic/generic/Config.lb
+++ /dev/null
diff --git a/src/drivers/i2c/adm1026/Config.lb b/src/drivers/i2c/adm1026/Config.lb
deleted file mode 100644
index 52cbfaa..0000000
--- a/src/drivers/i2c/adm1026/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object adm1026.o
diff --git a/src/drivers/i2c/adm1027/Config.lb b/src/drivers/i2c/adm1027/Config.lb
deleted file mode 100644
index 395ebab..0000000
--- a/src/drivers/i2c/adm1027/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object adm1027.o
diff --git a/src/drivers/i2c/i2cmux/Config.lb b/src/drivers/i2c/i2cmux/Config.lb
deleted file mode 100644
index 6bce919..0000000
--- a/src/drivers/i2c/i2cmux/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object i2cmux.o
diff --git a/src/drivers/i2c/i2cmux2/Config.lb b/src/drivers/i2c/i2cmux2/Config.lb
deleted file mode 100644
index a0d83ba..0000000
--- a/src/drivers/i2c/i2cmux2/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object i2cmux2.o
diff --git a/src/drivers/i2c/lm63/Config.lb b/src/drivers/i2c/lm63/Config.lb
deleted file mode 100644
index 959c7af..0000000
--- a/src/drivers/i2c/lm63/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object lm63.o
diff --git a/src/drivers/si/3114/Config.lb b/src/drivers/si/3114/Config.lb
deleted file mode 100644
index a7ebf67..0000000
--- a/src/drivers/si/3114/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver si_sata.o
diff --git a/src/drivers/trident/blade3d/Config.lb b/src/drivers/trident/blade3d/Config.lb
deleted file mode 100644
index 0b2416d..0000000
--- a/src/drivers/trident/blade3d/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver blade3d.o
diff --git a/src/lib/Config.lb b/src/lib/Config.lb
deleted file mode 100644
index 7af325d..0000000
--- a/src/lib/Config.lb
+++ /dev/null
@@ -1,33 +0,0 @@
-uses CONFIG_USE_INIT
-uses CONFIG_USBDEBUG_DIRECT
-
-object clog2.o
-object uart8250.o
-
-if CONFIG_USBDEBUG_DIRECT
-	object usbdebug_direct.o
-end
-
-object memset.o
-object memcpy.o
-object memcmp.o
-object memmove.o
-object malloc.o
-object delay.o
-object fallback_boot.o
-object compute_ip_checksum.o
-object version.o
-object gcc.o
-object cbfs.o
-object lzma.o
-object cbmem.o
-
-# Force version.o to recompile every time
-makedefine .PHONY : version.o
-
-initobject uart8250.o
-initobject memset.o
-initobject memcpy.o
-initobject memcmp.o
-
-
diff --git a/src/mainboard/a-trend/atc-6220/Config.lb b/src/mainboard/a-trend/atc-6220/Config.lb
deleted file mode 100644
index da9f349..0000000
--- a/src/mainboard/a-trend/atc-6220/Config.lb
+++ /dev/null
@@ -1,132 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# Consumer IR
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/a-trend/atc-6220/Options.lb b/src/mainboard/a-trend/atc-6220/Options.lb
deleted file mode 100644
index 6884393..0000000
--- a/src/mainboard/a-trend/atc-6220/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/a-trend/atc-6240/Config.lb b/src/mainboard/a-trend/atc-6240/Config.lb
deleted file mode 100644
index 1f8a889..0000000
--- a/src/mainboard/a-trend/atc-6240/Config.lb
+++ /dev/null
@@ -1,142 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83627hf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# Consumer IR
-            io 0x60 = 0x00
-          end
-          device pnp 3f0.7 on		# Game port / MIDI / GPIO 1
-            io 0x60 = 0x201
-            io 0x62 = 0x330
-            irq 0x70 = 9
-          end
-          device pnp 3f0.8 off		# GPIO 2 / WDT
-          end
-          device pnp 3f0.9 off		# GPIO 3
-          end
-          device pnp 3f0.a off		# ACPI
-          end
-          device pnp 3f0.b off		# HWM (TODO)
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      device pci c.0 on end		# Onboard audio (ES1371)
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/a-trend/atc-6240/Options.lb b/src/mainboard/a-trend/atc-6240/Options.lb
deleted file mode 100644
index 7930819..0000000
--- a/src/mainboard/a-trend/atc-6240/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/abit/be6-ii_v2_0/Config.lb b/src/mainboard/abit/be6-ii_v2_0/Config.lb
deleted file mode 100644
index 58193b8..0000000
--- a/src/mainboard/abit/be6-ii_v2_0/Config.lb
+++ /dev/null
@@ -1,132 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# Consumer IR
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE, UDMA/33 (part of 82371EB)
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      device pci 13.0 on end		# IDE, UDMA/66 (HPT366 controller)
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      register "ide0_drive0_udma33_enable" = "1"
-      register "ide0_drive1_udma33_enable" = "1"
-      register "ide1_drive0_udma33_enable" = "1"
-      register "ide1_drive1_udma33_enable" = "1"
-    end
-  end
-end
diff --git a/src/mainboard/abit/be6-ii_v2_0/Options.lb b/src/mainboard/abit/be6-ii_v2_0/Options.lb
deleted file mode 100644
index c415fd2..0000000
--- a/src/mainboard/abit/be6-ii_v2_0/Options.lb
+++ /dev/null
@@ -1,98 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024		# Override this in targets/*/Config.lb.
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 9		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
-default CONFIG_CONSOLE_VGA = 1		# Override this in targets/*/Config.lb.
-default CONFIG_PCI_ROM_RUN = 1		# Override this in targets/*/Config.lb.
-
-end
diff --git a/src/mainboard/advantech/pcm-5820/Config.lb b/src/mainboard/advantech/pcm-5820/Config.lb
deleted file mode 100644
index 44ec55d..0000000
--- a/src/mainboard/advantech/pcm-5820/Config.lb
+++ /dev/null
@@ -1,129 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1		# Northbridge
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 12.0 on		# ISA bridge
-        chip superio/winbond/w83977f	# SUper I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.4 on		# RTC / On-Now control
-            io 0x60 = 0x70
-            irq 0x70 = 8
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# IR
-            # TODO?
-          end
-          device pnp 3f0.7 on		# GPIO 1
-            # TODO?
-          end
-          device pnp 3f0.8 on		# GPIO 2
-            # TODO?
-          end
-        end
-      end
-      device pci 12.1 on end		# SMI
-      device pci 12.2 on end		# IDE
-      device pci 12.3 on end		# Audio (onboard)
-      device pci 12.4 on end		# VGA
-      device pci 13.0 on end		# USB
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-    end
-  end
-  chip cpu/amd/model_gx1		# CPU
-  end
-end
diff --git a/src/mainboard/advantech/pcm-5820/Options.lb b/src/mainboard/advantech/pcm-5820/Options.lb
deleted file mode 100644
index 684e4dc..0000000
--- a/src/mainboard/advantech/pcm-5820/Options.lb
+++ /dev/null
@@ -1,103 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_VIDEO_MB
-uses CONFIG_SPLASH_GRAPHIC
-uses CONFIG_GX1_VIDEO
-uses CONFIG_GX1_VIDEOMODE
-uses CONFIG_PIRQ_ROUTE
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-default CONFIG_GX1_VIDEO = 1
-default CONFIG_GX1_VIDEOMODE = 0
-default CONFIG_SPLASH_GRAPHIC = 1
-default CONFIG_VIDEO_MB = 2
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 2		# Override this in targets/*/Config.lb.
-default CONFIG_PIRQ_ROUTE = 1
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-end
diff --git a/src/mainboard/amd/db800/Config.lb b/src/mainboard/amd/db800/Config.lb
deleted file mode 100644
index de22906..0000000
--- a/src/mainboard/amd/db800/Config.lb
+++ /dev/null
@@ -1,152 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-	#compile cache_as_ram.c to auto.inc
-	makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-#	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/lx
-	device pci_domain 0 on
-		device pci 1.0 on end				# Northbridge
-		device pci 1.1 on end				# Graphics
-		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
-			register "lpc_serirq_enable" = "0x0000105a"
-			register "lpc_serirq_polarity" = "0x0000EFA5"
-			register "lpc_serirq_mode" = "1"
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0"	# 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "1"	# 0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "0"
-			register "com1_address" = "0x3F8"
-			register "com1_irq" = "4"
-			register "com2_enable" = "0"
-			register "com2_address" = "0x2F8"
-			register "com2_irq" = "3"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci d.0 on end			# Ethernet
-			device pci e.0 on end			# Slot1
-			device pci f.0 on			# ISA Bridge
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 off	# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.1 off	# Parallel port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.2 on	# Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 off end	# Com2
-					device pnp 2e.5 on	# Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-					device pnp 2e.6 off end	# CIR
-					device pnp 2e.7 off end	# GAME_MIDI_GIPO1
-					device pnp 2e.8 off end	# GPIO2
-					device pnp 2e.9 off end	# GPIO3
-					device pnp 2e.a off end	# ACPI
-					device pnp 2e.b off end	# HW Monitor
-				end
-			end
-			device pci f.2 on end			# IDE Controller
-			device pci f.3 on end			# Audio
-			device pci f.4 on end			# OHCI
-			device pci f.5 on end			# EHCI
-		end
-	end
-	# APIC cluster is late CPU init.
-	device apic_cluster 0 on
-		chip cpu/amd/model_lx
-			device apic 0 on end
-		end
-	end
-end
-
diff --git a/src/mainboard/amd/db800/Options.lb b/src/mainboard/amd/db800/Options.lb
deleted file mode 100644
index 5ec7b1e..0000000
--- a/src/mainboard/amd/db800/Options.lb
+++ /dev/null
@@ -1,180 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_VIDEO_MB=8
-default CONFIG_PCI_ROM_RUN=0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=4
-default CONFIG_PIRQ_ROUTE=1
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 32768
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/amd/dbm690t/Config.lb b/src/mainboard/amd/dbm690t/Config.lb
deleted file mode 100644
index fde48a1..0000000
--- a/src/mainboard/amd/dbm690t/Config.lb
+++ /dev/null
@@ -1,258 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE
-	object get_bus_conf.o
-	object irq_tables.o
-end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object acpi_tables.o
-	object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-	if CONFIG_USE_INIT
-
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else
-
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript      /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-#The variables belong to mainboard are defined here.
-
-#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_S1G1
-		device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  southbridge
-				chip southbridge/amd/rs690
-					device pci 0.0 on end # HT  	0x7910
-					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						device pci 5.0 on end	# Internal Graphics 0x791F
-					end
-					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
-					device pci 3.0 off end # PCIE P2P bridge	0x791b
-					device pci 4.0 on end # PCIE P2P bridge 0x7914
-					device pci 5.0 on end # PCIE P2P bridge 0x7915
-					device pci 6.0 on end # PCIE P2P bridge 0x7916
-					device pci 7.0 on end # PCIE P2P bridge 0x7917
-					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "gpp_configuration" = "4"
-					register "port_enable" = "0xfc"
-					register "gfx_dev2_dev3" = "1"
-					register "gfx_dual_slot" = "0"
-					register "gfx_lane_reversal" = "0"
-					register "gfx_tmds" = "0"
-					register "gfx_compliance" = "0"
-					register "gfx_reconfiguration" = "1"
-					register "gfx_link_width" = "0"
-				end
-				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
-					device pci 12.0 on end # SATA  0x4380
-					device pci 13.0 on end # USB   0x4387
-					device pci 13.1 on end # USB   0x4388
-					device pci 13.2 on end # USB   0x4389
-					device pci 13.3 on end # USB   0x438a
-					device pci 13.4 on end # USB   0x438b
-					device pci 13.5 on end # USB 2 0x4386
-	 				device pci 14.0 on # SM        0x4385
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end
-					end # SM
-					device pci 14.1 on end # IDE    0x438c
-					device pci 14.2 on end # HDA    0x4383
-					device pci 14.3 on # LPC	0x438d
-						chip superio/ite/it8712f
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.2 off #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.3 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.4 off end #  EC
-							device pnp 2e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 2e.6 on #  Mouse
-								irq 0x70 = 12
-							end
-							device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
-							end
-							device pnp 2e.8 off #  MIDI
-								io 0x60 = 0x300
-								irq 0x70 = 9
-							end
-							device pnp 2e.9 off #  GAME
-								io 0x60 = 0x220
-							end
-							device pnp 2e.a off end #  CIR
-						end	#superio/ite/it8712f
-					end		#LPC
-					device pci 14.4 on end # PCI 0x4384
-					device pci 14.5 on end # ACI 0x4382
-					device pci 14.6 on end # MCI 0x438e
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "hda_viddid" = "0x10ec0882"
-				end	#southbridge/amd/sb600
-			end #  device pci 18.0
-
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end		#northbridge/amd/amdk8
-	end #pci_domain
-end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/amd/dbm690t/Options.lb b/src/mainboard/amd/dbm690t/Options.lb
deleted file mode 100644
index d5d54f9..0000000
--- a/src/mainboard/amd/dbm690t/Options.lb
+++ /dev/null
@@ -1,301 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VGA_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_VIDEO_MB
-uses CONFIG_GFXUMA
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-default CONFIG_VGA_ROM_RUN=1
-
-# BTDC: Only one HT device on Herring.
-#HT Unit ID offset
-#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-
-#real SB Unit ID
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
-
-#make the SB HT chain on bus 0
-default CONFIG_SB_HT_CHAIN_ON_BUS0=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="dbm690t"
-default CONFIG_MAINBOARD_VENDOR="amd"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
-
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_VIDEO_MB=1
-default CONFIG_GFXUMA=1
-default CONFIG_HAVE_MAINBOARD_RESOURCES=1
-
-### End Options.lb
-end
diff --git a/src/mainboard/amd/norwich/Config.lb b/src/mainboard/amd/norwich/Config.lb
deleted file mode 100644
index 5f0dc33..0000000
--- a/src/mainboard/amd/norwich/Config.lb
+++ /dev/null
@@ -1,125 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-	#compile cache_as_ram.c to auto.inc
-	makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-#	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/lx
-	device pci_domain 0 on
-		device pci 1.0 on end	# Northbridge
-		device pci 1.1 on end	# Graphics
-		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
-			register "lpc_serirq_enable" = "0x00001002"
-			register "lpc_serirq_polarity" = "0x0000EFFD"
-			register "lpc_serirq_mode" = "1"
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "0"	#0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "1"
-			register "com1_address" = "0x3F8"
-			register "com1_irq" = "4"
-			register "com2_enable" = "0"
-			register "com2_address" = "0x2F8"
-			register "com2_irq" = "3"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci b.0 on end	# Slot 3
-			device pci c.0 on end	# Slot 4
-			device pci d.0 on end	# Slot 1
-			device pci e.0 on end	# Slot 2
-			device pci f.0 on end	# ISA Bridge
-			device pci f.2 on end	# IDE Controller
-			device pci f.3 on end	# Audio
-			device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-		end
-	end
-	# APIC cluster is late CPU init.
-	device apic_cluster 0 on
-		chip cpu/amd/model_lx
-			device apic 0 on end
-		end
-	end
-end
-
diff --git a/src/mainboard/amd/norwich/Options.lb b/src/mainboard/amd/norwich/Options.lb
deleted file mode 100644
index 0ca2026..0000000
--- a/src/mainboard/amd/norwich/Options.lb
+++ /dev/null
@@ -1,180 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_VIDEO_MB=8
-default CONFIG_PCI_ROM_RUN=0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=6
-default CONFIG_PIRQ_ROUTE=1
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/amd/pistachio/Config.lb b/src/mainboard/amd/pistachio/Config.lb
deleted file mode 100644
index 1f59668..0000000
--- a/src/mainboard/amd/pistachio/Config.lb
+++ /dev/null
@@ -1,218 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE
-	object get_bus_conf.o
-	object irq_tables.o
-end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object acpi_tables.o
-	object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-	if CONFIG_USE_INIT
-
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else
-
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript      /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-#The variables belong to mainboard are defined here.
-
-#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_AM2
-		device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  southbridge, K8 HT Configuration
-				chip southbridge/amd/rs690
-					device pci 0.0 on end # HT  	0x7910
-				#	device pci 0.1 off end # CLK
-					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						device pci 5.0 on end	# Internal Graphics 0x791F
-					end
-					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
-					device pci 3.0 off end # PCIE P2P bridge	0x791b
-					device pci 4.0 on end # PCIE P2P bridge 0x7914
-					device pci 5.0 on end # PCIE P2P bridge 0x7915
-					device pci 6.0 on end # PCIE P2P bridge 0x7916
-					device pci 7.0 on end # PCIE P2P bridge 0x7917
-					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "gpp_configuration" = "4"
-					register "port_enable" = "0xfc"
-					register "gfx_dev2_dev3" = "1"
-					register "gfx_dual_slot" = "0"
-					register "gfx_lane_reversal" = "0"
-					register "gfx_tmds" = "0"
-					register "gfx_compliance" = "0"
-					register "gfx_reconfiguration" = "1"
-					register "gfx_link_width" = "0"
-				end
-				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
-					device pci 12.0 on end # SATA  0x4380
-					device pci 13.0 on end # USB   0x4387
-					device pci 13.1 on end # USB   0x4388
-					device pci 13.2 on end # USB   0x4389
-					device pci 13.3 on end # USB   0x438a
-					device pci 13.4 on end # USB   0x438b
-					device pci 13.5 on end # USB 2 0x4386
-	 				device pci 14.0 on # SM        0x4385
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 off end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 off end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 off end
-						end
-					end # SM
-				device pci 14.1 on end # IDE    0x438c
-				device pci 14.2 on end # HDA    0x4383
-				device pci 14.3 on end # LPC	0x438d
-				device pci 14.4 on end # PCI 0x4384
-				device pci 14.5 on end # ACI 0x4382
-				device pci 14.6 on end # MCI 0x438e
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "hda_viddid" = "0x10ec0882"
-				end	#southbridge/amd/sb600
-			end #  device pci 18.0
-
-			device pci 18.1 on end		# K8 Address Map
-			device pci 18.2 on end		# K8 DRAM Controller and HT Trace Mode
-			device pci 18.3 on end		# K8 Miscellaneous Control
-		end		#northbridge/amd/amdk8
-	end #pci_domain
-end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/amd/pistachio/Options.lb b/src/mainboard/amd/pistachio/Options.lb
deleted file mode 100644
index 922edf5..0000000
--- a/src/mainboard/amd/pistachio/Options.lb
+++ /dev/null
@@ -1,301 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VGA_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_VIDEO_MB
-uses CONFIG_GFXUMA
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-default CONFIG_VGA_ROM_RUN=1
-
-# BTDC: Only one HT device on Herring.
-#HT Unit ID offset
-#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-
-#real SB Unit ID
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
-
-#make the SB HT chain on bus 0
-default CONFIG_SB_HT_CHAIN_ON_BUS0=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="pistachio"
-default CONFIG_MAINBOARD_VENDOR="amd"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
-
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_VIDEO_MB=1
-default CONFIG_GFXUMA=1
-default CONFIG_HAVE_MAINBOARD_RESOURCES=1
-
-### End Options.lb
-end
diff --git a/src/mainboard/amd/rumba/Config.lb b/src/mainboard/amd/rumba/Config.lb
deleted file mode 100644
index 9083949..0000000
--- a/src/mainboard/amd/rumba/Config.lb
+++ /dev/null
@@ -1,115 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx2
-	device apic_cluster 0 on
-		chip cpu/amd/model_gx2
-			device apic 0 on end
-		end
-	end
-  	device pci_domain 0 on 
-    		device pci 1.0 on end
-		device pci 1.1 on end
-      		chip southbridge/amd/cs5536
-			register "lpc_serirq_enable" = "0x80"  # enabled with default timing
-        		device pci d.0 on end	# Realtek 8139 LAN
-        		device pci f.0 on end	# ISA Bridge
-        		device pci f.2 on end	# IDE Controller
-        		device pci f.3 on end 	# Audio
-        		device pci f.4 on end	# OHCI
-			device pci f.4 on end	# UHCI
-      		end
-    	end
-end
-
diff --git a/src/mainboard/amd/rumba/Options.lb b/src/mainboard/amd/rumba/Options.lb
deleted file mode 100644
index e6a9b48..0000000
--- a/src/mainboard/amd/rumba/Options.lb
+++ /dev/null
@@ -1,159 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=2
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb
deleted file mode 100644
index 1e2f1b2..0000000
--- a/src/mainboard/amd/serengeti_cheetah/Config.lb
+++ /dev/null
@@ -1,358 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE 
-	object mptable.o 
-end
-
-if CONFIG_GENERATE_PIRQ_TABLE 
-	object irq_tables.o 
-end
-
-#if CONFIG_GENERATE_ACPI_TABLES
-#       object acpi_tables.o
-#       object fadt.o
-#       if CONFIG_SB_HT_CHAIN_ON_BUS0
-#               object dsdt_bus0.o
-#       else
-#               object dsdt.o
-#       end
-#       object ssdt.o
-#       if CONFIG_ACPI_SSDTX_NUM
-#                if CONFIG_SB_HT_CHAIN_ON_BUS0
-#                 object ssdt2_bus0.o
-#                else
-#                 object ssdt2.o
-#                end
-#       end
-#end
-
-if CONFIG_GENERATE_ACPI_TABLES
-        object acpi_tables.o
-        object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "mv dsdt_lb.hex dsdt.c"
-	end
-        object ./dsdt.o
-
-	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
-	
-        if CONFIG_ACPI_SSDTX_NUM
-            makerule ssdt2.c
-                        depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
-                        action  "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
-                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
-                        action  "mv pci2.hex ssdt2.c"
-            end
-            object ./ssdt2.o
-            makerule ssdt3.c
-                        depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
-                        action  "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
-                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
-                        action  "mv pci3.hex ssdt3.c"
-            end
-            object ./ssdt3.o
-            makerule ssdt4.c
-                        depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
-                        action  "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
-                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
-                        action  "mv pci4.hex ssdt4.c"
-            end
-            object ./ssdt4.o
-        end
-end
-
-	if CONFIG_USE_INIT
-		# compile cache_as_ram.c to auto.o
-		makerule ./cache_as_ram_auto.o
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else   
-		#compile cache_as_ram.c to auto.inc 
-		makerule ./cache_as_ram_auto.inc
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-	makerule ./apc_auto.o
-		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-	end
-	ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for amd/serengeti_cheetah 
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_F
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  northbridge 
-				#  devices on link 0, link 0 == LDT 0
-				chip southbridge/amd/amd8132
-					# the on/off keyword is mandatory
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 off #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	        			device pnp 2e.6 off #  CIR
-								io 0x60 = 0x100
-							end
-                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end						
-                	        			device pnp 2e.8 off end #  GPIO2
-                	        			device pnp 2e.9 off end #  GPIO3
-                	        			device pnp 2e.a off end #  ACPI
-                	        			device pnp 2e.b on #  HW Monitor
- 					 			io 0x60 = 0x290
-								irq 0x70 = 5
-                					end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on
-                                                chip drivers/i2c/i2cmux # pca9556 smbus mux
-                                                        device i2c 18 on #0 pca9516 1
-                                                                chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                        end
-                                                        device i2c 18 on #1 pca9516 2
-                                                                chip drivers/generic/generic #dimm 1-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-2-0
-                                                                        device i2c 54 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-2-1
-                                                                        device i2c 55 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-3-0
-                                                                        device i2c 56 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-3-1
-                                                                        device i2c 57 on end
-                                                                end
-                                                        end
-						end
-					end # acpi
-					device pci 1.5 off end
-					device pci 1.6 off end
-                	                register "ide0_enable" = "1"
-                	                register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0
-
-                        device pci 18.0 on end
-                        device pci 18.0 on end  
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-                chip northbridge/amd/amdk8
-                        device pci 19.0 on #  northbridge
-                                chip southbridge/amd/amd8151
-                                        # the on/off keyword is mandatory
-                                        device pci 0.0 on end
-                                        device pci 1.0 on end
-                                end
-                        end #  device pci 19.0
-
-                        device pci 19.0 on end
-                        device pci 19.0 on end
-                        device pci 19.1 on end
-                        device pci 19.2 on end
-                        device pci 19.3 on end
-                end
-
-
-	end #pci_domain
-#        chip drivers/generic/debug
-#        	device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 off end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#                device pnp 0.7 off end # tsc
-#       end
-
-end
-
-
diff --git a/src/mainboard/amd/serengeti_cheetah/Options.lb b/src/mainboard/amd/serengeti_cheetah/Options.lb
deleted file mode 100644
index a20289d..0000000
--- a/src/mainboard/amd/serengeti_cheetah/Options.lb
+++ /dev/null
@@ -1,325 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-## extra SSDT num
-default CONFIG_ACPI_SSDTX_NUM=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=8
-default CONFIG_MAX_PHYSICAL_CPUS=4
-default CONFIG_LOGICAL_CPUS=1
-
-default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x8
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0xa
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-
-##
-## for rev F training on AP purpose
-##
-default CONFIG_AP_CODE_IN_CAR=1
-default CONFIG_MEM_TRAIN_SEQ=1
-default CONFIG_WAIT_BEFORE_CPUS_INIT=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="serengeti_cheetah"
-default CONFIG_MAINBOARD_VENDOR="AMD"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
deleted file mode 100644
index da52d4d..0000000
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
+++ /dev/null
@@ -1,362 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE
-	object mptable.o
-end
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	 object acpi_tables.o
-	 object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action	"iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action	"mv dsdt_lb.hex dsdt.c"
-	end
-	 object ./dsdt.o
-
-	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
-
-	if CONFIG_ACPI_SSDTX_NUM
-	makerule ssdt2.c
-		depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
-		action	"iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
-		action	"perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
-		action	"mv pci2.hex ssdt2.c"
-	end
-	object ./ssdt2.o
-	makerule ssdt3.c
-		depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
-		action	"iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
-		action	"perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
-		action	"mv pci3.hex ssdt3.c"
-	end
-	object ./ssdt3.o
-	makerule ssdt4.c
-		depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
-		action	"iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
-		action	"perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
-		action	"mv pci4.hex ssdt4.c"
-	end
-	object ./ssdt4.o
-	makerule ssdt5.c
-		depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
-		action	"iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
-		action	"perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
-		action	"mv pci5.hex ssdt5.c"
-	end
-	object ./ssdt5.o
-	 end
-end
-
-	if CONFIG_USE_INIT
-		# compile cache_as_ram.c to auto.o
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else
-		#compile cache_as_ram.c to auto.inc
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-	 makerule ./apc_auto.o
-		 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-		 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-	 end
-	 ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-	 if CONFIG_USE_INIT
-		 ldscript /cpu/x86/32bit/entry32.lds
-	 end
-
-	 if CONFIG_USE_INIT
-		 ldscript /cpu/amd/car/cache_as_ram.lds
-	 end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-end
-
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-dir /southbridge/amd/amd8151
-
-# sample config for amd/serengeti_cheetah_fam10
-chip northbridge/amd/amdfam10/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_F_1207  #L1 and DDR2
-			 device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdfam10
-			device pci 18.0 on #  northbridge
-				#  devices on link 0, link 0 == LDT 0
-				chip southbridge/amd/amd8132
-					# the on/off keyword is mandatory
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 off #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-								irq 0x72 = 12
-							end
-							device pnp 2e.6 off #  CIR
-								io 0x60 = 0x100
-							end
-							device pnp 2e.7 off #  GAME_MIDI_GIPO1
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end
-							device pnp 2e.8 off end #  GPIO2
-							device pnp 2e.9 off end #  GPIO3
-							device pnp 2e.a off end #  ACPI
-							device pnp 2e.b on #  HW Monitor
-								io 0x60 = 0x290
-								irq 0x70 = 5
-							end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on
-						chip drivers/i2c/i2cmux2 # pca9556 smbus mux
-						chip drivers/i2c/i2cmux2 # pca9556 smbus mux
-							device i2c 18 on #0 pca9516 1
-								chip drivers/generic/generic #dimm 0-0-0
-									device i2c 50 on end
-								end
-								chip drivers/generic/generic #dimm 0-0-1
-									device i2c 51 on end
-								end
-								chip drivers/generic/generic #dimm 0-1-0
-									device i2c 52 on end
-								end
-								chip drivers/generic/generic #dimm 0-1-1
-									device i2c 53 on end
-								end
-							end
-							device i2c 18 on #1 pca9516 2
-								chip drivers/generic/generic #dimm 1-0-0
-									device i2c 50 on end
-								end
-								chip drivers/generic/generic #dimm 1-0-1
-									device i2c 51 on end
-								end
-								chip drivers/generic/generic #dimm 1-1-0
-									device i2c 52 on end
-								end
-								chip drivers/generic/generic #dimm 1-1-1
-									device i2c 53 on end
-								end
-							end
-						end
-						end
-					end # acpi
-					device pci 1.5 off end
-					device pci 1.6 off end
-					register "ide0_enable" = "1"
-					register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0
-
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-#			device pci 00.5 on end
-		end
-	end #pci_domain
-	#for node 32 to node 63
-#	device pci_domain 0 on
-#		chip northbridge/amd/amdfam10
-#			  device pci 00.0 on end#  northbridge
-#			  device pci 00.0 on end
-#			  device pci 00.0 on end
-#			  device pci 00.0 on end
-#			  device pci 00.1 on end
-#			  device pci 00.2 on end
-#			  device pci 00.3 on end
-#			  device pci 00.4 on end
-#			 device pci 00.5 on end
-#		end
-#	end #pci_domain
-
-#	  chip drivers/generic/debug
-#		 device pnp 0.0 off end # chip name
-#		  device pnp 0.1 on end # pci_regs_all
-#		  device pnp 0.2 off end # mem
-#		  device pnp 0.3 off end # cpuid
-#		  device pnp 0.4 off end # smbus_regs_all
-#		  device pnp 0.5 off end # dual core msr
-#		  device pnp 0.6 off end # cache size
-#		  device pnp 0.7 off end # tsc
-#		  device pnp 0.8 off end # hard reset
-#		  device pnp 0.9 off end # mcp55
-#		  device pnp 0.a on end # GH ext table
-#	 end
-
-end
-
-
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
deleted file mode 100644
index 5a17e34..0000000
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ /dev/null
@@ -1,365 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_PCI_BUS_SEGN_BITS
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_AMDMCT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_AMD_UCODE_PATCH_FILE
-
-uses CONFIG_ID_SECTION_OFFSET
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1024*1024
-
-##
-##
-#FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-#FALLBACK: 1024K - 8K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#FAILOVER: 8k
-default CONFIG_FAILOVER_SIZE=0x02000
-
-#more 1M for pgtbl
-#if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.
-default CONFIG_RAMTOP=16384*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-## extra SSDT num
-default CONFIG_ACPI_SSDTX_NUM=31
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_PHYSICAL_CPUS=8
-default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS
-default CONFIG_LOGICAL_CPUS=1
-
-#default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=1
-default CONFIG_APIC_ID_OFFSET=0x00
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0xa
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-#it only be 0, 1, 2, 3, 4 and default is 0
-#default CONFIG_PCI_BUS_SEGN_BITS=3
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc4000
-default CONFIG_DCACHE_RAM_SIZE=0x0c000
-#default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
-default CONFIG_USE_INIT=0
-
-#default CONFIG_AP_CODE_IN_CAR=1
-default CONFIG_MEM_TRAIN_SEQ=2
-default CONFIG_WAIT_BEFORE_CPUS_INIT=0
-
-default CONFIG_AMDMCT = 1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="Cheetah Fam10"
-default CONFIG_MAINBOARD_VENDOR="AMD"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
-
-##
-## Set microcode patch file name
-##
-##	Barcelona rev DR-Ax:  "mc_patch_01000020.h"
-##	Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h"
-##	Barcelona rev DR-B2, B3: "mc_patch_01000095.h"
-##	Shanghai rev DA-C2: "mc_patch_0100009f.h"
-##
-default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 768k heap
-##
-default CONFIG_HEAP_SIZE=0xc0000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00200000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb
deleted file mode 100644
index 13e351f..0000000
--- a/src/mainboard/arima/hdama/Config.lb
+++ /dev/null
@@ -1,297 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# config for arima/hdama
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_940
-			device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  northbridge 
-				#  devices on link 0, link 0 == LDT 0 
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-					device pci 0.0 on	# PCIX bridge
-						## On board NIC A
-						#chip drivers/generic/generic
-						#	device pci 3.0 on	
-						#		irq 0 = 0x13
-						#	end
-						#end
-						## On board NIC B
-						#chip drivers/generic/generic
-						#	device pci 4.0 on
-						#		irq 0 = 0x13
-						#	end
-						#end
-						## PCI Slot 3
-						#chip drivers/generic/generic
-						#	device pci 1.0 on
-						#		irq 0 = 0x11
-						#		irq 1 = 0x12
-						#		irq 2 = 0x13
-						#		irq 3 = 0x10
-						#	end
-						#end 
-						## PCI Slot 4
-						#chip drivers/generic/generic
-						#	device pci 2.0 on
-						#		irq 0 = 0x12
-						#		irq 1 = 0x13
-						#		irq 2 = 0x10
-						#		irq 3 = 0x11
-						#	end
-						#end 
-					end
-					device pci 0.1 on end	# IOAPIC
-					device pci 1.0 on 	# PCIX bridge
-						## PCI Slot 1
-						#chip drivers/generic/generic
-						#	device pci 1.0 on
-						#		irq 0 = 0x11
-						#		irq 1 = 0x12
-						#		irq 2 = 0x13
-						#		irq 3 = 0x10
-						#	end
-						#end
-						## PCI Slot 2
-						#chip drivers/generic/generic
-						#	device pci 2.0 on
-						#		irq 0 = 0x12
-						#		irq 1 = 0x13
-						#		irq 2 = 0x10
-						#		irq 3 = 0x11
-						#	end
-						#end 
-					end
-					device pci 1.1 on end	# IOAPIC
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent of the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on  end	# USB0
-						device pci 0.1 on  end	# USB1
-						device pci 0.2 off end	# USB 2.0
-						device pci 1.0 off end	# LAN
-						device pci 6.0 on end # ATI Rage XL
-						## PCI Slot 5 (correct?)
-						#chip drivers/generic/generic
-						#	device pci 5.0 on
-						#		irq 0 = 0x11
-						#		irq 1 = 0x12
-						#		irq 2 = 0x13
-						#		irq 3 = 0x10
-						#	end
-						#end 
-						## PCI Slot 6 (correct?)
-						#chip drivers/generic/generic
-						#	device pci 4.0 on
-						#		irq 0 = 0x10
-						#		irq 1 = 0x11
-						#		irq 2 = 0x12
-						#		irq 3 = 0x13
-						#	end
-						#end 
-
-					end
-					# LPC bridge
-					device pci 1.0 on
-						chip superio/nsc/pc87360
-							device	pnp 2e.0 off  # Floppy 
-								 io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off  # Parallel Port
-								 io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 off # Com 2
-								 io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.3 on  # Com 1
-								 io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.4 off end # SWC
-							device pnp 2e.5 off end # Mouse
-							device pnp 2e.6 on  # Keyboard
-								 io 0x60 = 0x60
-								 io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 2e.7 off end # GPIO
-							device pnp 2e.8 off end # ACB
-							device pnp 2e.9 off end # FSCM
-							device pnp 2e.a off end # WDT  
-						end
-					end
-					device pci 1.1 on end	# IDE
-					device pci 1.2 on end	# SMBus 2.0
-					device pci 1.3 on 	# System Management
-						chip drivers/generic/generic
-							#phillips pca9545 smbus mux
-							device i2c 70 on 
-								# analog_devices adm1026	
-								chip drivers/generic/generic
-									device i2c 2c on end
-								end
-							end
-							device i2c 70 on end
-							device i2c 70 on end
-							device i2c 70 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end 
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end 
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end 
-						chip drivers/generic/generic #dimm 1-0-0
-							device i2c 54 on end 
-						end
-						chip drivers/generic/generic #dimm 1-0-1
-							device i2c 55 on end
-						end 
-						chip drivers/generic/generic #dimm 1-1-0
-							device i2c 56 on end
-						end 
-						chip drivers/generic/generic #dimm 1-1-1
-							device i2c 57 on end
-						end 
-					end
-					device pci 1.5 off end	# AC97 Audio
-					device pci 1.6 on  end	# AC97 Modem
-					register "ide0_enable" = "1"
-					register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0 
-			
-			device pci 18.0 on end # LDT1
-			device pci 18.0 on end # LDT2
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end  # chip northbridge/amd/amdk8
-		chip northbridge/amd/amdk8
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-		end
-	end 
-end
-
diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb
deleted file mode 100644
index c047282..0000000
--- a/src/mainboard/arima/hdama/Options.lb
+++ /dev/null
@@ -1,242 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_LOGICAL_CPUS enables dual core support
-##
-default CONFIG_LOGICAL_CPUS=1
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
- 
-#VGA
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="HDAMA"
-default CONFIG_MAINBOARD_VENDOR="ARIMA"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
-
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/artecgroup/dbe61/Config.lb b/src/mainboard/artecgroup/dbe61/Config.lb
deleted file mode 100644
index e3cc41b..0000000
--- a/src/mainboard/artecgroup/dbe61/Config.lb
+++ /dev/null
@@ -1,124 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	#compile cache_as_ram.c to auto.inc
-	makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-#	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/lx
-	device pci_domain 0 on
-		device pci 1.0 on end	# Northbridge
-		device pci 1.1 on end	# Graphics
-		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
-			register "lpc_serirq_enable" = "0x00001002"
-			register "lpc_serirq_polarity" = "0x0000EFFD"
-			register "lpc_serirq_mode" = "1"
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "0"	#0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "0"
-			register "com1_address" = "0x2F8"
-			register "com1_irq" = "3"
-			register "com2_enable" = "1"
-			register "com2_address" = "0x3F8"
-			register "com2_irq" = "4"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci b.0 on end	# Slot 3
-			device pci c.0 on end	# Slot 4
-			device pci d.0 on end	# Slot 1
-			device pci e.0 on end	# Slot 2
-			device pci f.0 on end	# ISA Bridge
-			device pci f.2 on end	# IDE Controller
-			device pci f.3 on end	# Audio
-			device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-		end
-	end
-	# APIC cluster is late CPU init.
-	device apic_cluster 0 on
-		chip cpu/amd/model_lx
-			device apic 0 on end
-		end
-	end
-
-end
-
diff --git a/src/mainboard/artecgroup/dbe61/Options.lb b/src/mainboard/artecgroup/dbe61/Options.lb
deleted file mode 100644
index 3aebf74..0000000
--- a/src/mainboard/artecgroup/dbe61/Options.lb
+++ /dev/null
@@ -1,180 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_PCI_ROM_RUN=0
-default CONFIG_VIDEO_MB=8
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=3
-default CONFIG_PIRQ_ROUTE=1
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/artecgroup/dbe61/realmode/Config.lb b/src/mainboard/artecgroup/dbe61/realmode/Config.lb
deleted file mode 100644
index 899843d..0000000
--- a/src/mainboard/artecgroup/dbe61/realmode/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-driver vgabios.o
diff --git a/src/mainboard/asi/mb_5blgp/Config.lb b/src/mainboard/asi/mb_5blgp/Config.lb
deleted file mode 100644
index 7bd25dc..0000000
--- a/src/mainboard/asi/mb_5blgp/Config.lb
+++ /dev/null
@@ -1,128 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1		# Northbridge
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 0f.0 on end		# Ethernet
-      device pci 12.0 on		# ISA bridge
-        chip superio/nsc/pc87351	# Super I/O
-          device pnp 2e.0 off		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.2 on		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.e on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.4 on		# System wake-up control (SWC)
-            irq 0x60 = 0x500
-          end
-          device pnp 2e.5 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.6 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.7 on		# GPIO
-            irq 0x60 = 0x800
-          end
-          device pnp 2e.8 on		# Fan speed control
-            irq 0x60 = 0x900
-          end
-        end
-      end
-      device pci 12.1 off end		# SMI
-      device pci 12.2 on end		# IDE
-      device pci 12.3 on end		# Audio
-      device pci 12.4 on end		# VGA
-      device pci 13.0 on end		# USB
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "0"	# No connector on this board
-    end
-  end
-  chip cpu/amd/model_gx1		# CPU
-  end
-end
diff --git a/src/mainboard/asi/mb_5blgp/Options.lb b/src/mainboard/asi/mb_5blgp/Options.lb
deleted file mode 100644
index 7865fa3..0000000
--- a/src/mainboard/asi/mb_5blgp/Options.lb
+++ /dev/null
@@ -1,103 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_VIDEO_MB
-uses CONFIG_SPLASH_GRAPHIC
-uses CONFIG_GX1_VIDEO
-uses CONFIG_GX1_VIDEOMODE
-uses CONFIG_PIRQ_ROUTE
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-default CONFIG_GX1_VIDEO = 1
-default CONFIG_GX1_VIDEOMODE = 0
-default CONFIG_SPLASH_GRAPHIC = 1
-default CONFIG_VIDEO_MB = 2
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 3		# Override this in targets/*/Config.lb.
-default CONFIG_PIRQ_ROUTE = 1
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-end
diff --git a/src/mainboard/asi/mb_5blmp/Config.lb b/src/mainboard/asi/mb_5blmp/Config.lb
deleted file mode 100644
index 93ac8e6..0000000
--- a/src/mainboard/asi/mb_5blmp/Config.lb
+++ /dev/null
@@ -1,146 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-##
-## Romcc output
-##
-# makerule ./failover.E
-# 	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-# 	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-# end
-# 
-# makerule ./failover.inc
-# 	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-# 	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-# end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-# if CONFIG_USE_FALLBACK_IMAGE
-# 	ldscript /arch/i386/lib/failover.lds 
-# 	mainboardinit ./failover.inc
-# end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1		# Northbridge
-  device pci_domain 0 on
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 0f.0 off end		# Ethernet (Realtek RTL8139B)
-      device pci 12.0 on		# ISA bridge
-        chip superio/nsc/pc87351	# Super I/O
-          device pnp 2e.4 on		# PS/2 keyboard (+ mouse?)
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-            # irq 0x72 = 12
-          end
-          device pnp 2e.a on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.e on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.f off		# Floppy
-            io 0x60 = 0x3f2
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.10 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.12 on		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-        end
-      end
-      device pci 12.1 off end		# SMI
-      device pci 12.2 on  end		# IDE
-      device pci 12.3 on  end		# Audio
-      device pci 12.4 on  end		# VGA (onboard)
-      device pci 13.0 on end		# USB
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-    end
-  end
-  chip cpu/amd/model_gx1		# CPU
-  end
-end
-
diff --git a/src/mainboard/asi/mb_5blmp/Options.lb b/src/mainboard/asi/mb_5blmp/Options.lb
deleted file mode 100644
index 8924226..0000000
--- a/src/mainboard/asi/mb_5blmp/Options.lb
+++ /dev/null
@@ -1,163 +0,0 @@
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESS
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-# uses CONFIG_CONSOLE_VGA
-# uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE = 256 * 1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=5
-default CONFIG_PIRQ_ROUTE=1
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to export a CMOS option table
-##
-# default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-# default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-## At a maximum only compile in this level of debugging
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-# VGA Console
-# default CONFIG_CONSOLE_VGA=1
-# default CONFIG_PCI_ROM_RUN=1
-default CONFIG_VIDEO_MB = 0
-
-end
diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb
deleted file mode 100644
index 374629c..0000000
--- a/src/mainboard/asus/a8n_e/Config.lb
+++ /dev/null
@@ -1,241 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
-## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
-## (Thanks to LSRA University of Mannheim for their support)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-# Needed by irq_tables and mptable and acpi_tables.
-object get_bus_conf.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-	if CONFIG_USE_INIT
-		makerule ./auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit cpu/x86/16bit/entry16.inc
-		ldscript /cpu/x86/16bit/entry16.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit cpu/x86/16bit/entry16.inc
-		ldscript /cpu/x86/16bit/entry16.lds
-	end
-end
-mainboardinit cpu/x86/32bit/entry32.inc
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit cpu/x86/16bit/reset16.inc
-		ldscript /cpu/x86/16bit/reset16.lds
-	else
-		mainboardinit cpu/x86/32bit/reset32.inc
-		ldscript /cpu/x86/32bit/reset32.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit cpu/x86/16bit/reset16.inc
-		ldscript /cpu/x86/16bit/reset16.lds
-	else
-		mainboardinit cpu/x86/32bit/reset32.inc
-		ldscript /cpu/x86/32bit/reset32.lds
-	end
-end
-# Include an ID string (for safe flashing).
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-# ROMSTRAP table for CK804.
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit southbridge/nvidia/ck804/romstrap.inc
-		ldscript /southbridge/nvidia/ck804/romstrap.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit southbridge/nvidia/ck804/romstrap.inc
-		ldscript /southbridge/nvidia/ck804/romstrap.lds
-	end
-end
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-			ldscript /arch/i386/lib/failover_failover.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-			ldscript /arch/i386/lib/failover.lds
-	end
-end
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_939			# Socket 939 CPU
-      device apic 0 on end			# APIC
-    end
-  end
-
-  device pci_domain 0 on			# PCI domain
-    chip northbridge/amd/amdk8			# mc0
-      device pci 18.0 on			# Northbridge
-        # Devices on link 0, link 0 == LDT 0
-        chip southbridge/nvidia/ck804		# Southbridge
-          device pci 0.0 on end			# HT
-          device pci 1.0 on			# LPC
-            chip superio/ite/it8712f		# Super I/O
-              device pnp 2e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 2e.1 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 2e.2 off		# Com2 (N/A on this board)
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 2e.3 on		# Parallel port
-                io 0x60 = 0x378
-                irq 0x70 = 7
-                drq 0x74 = 3
-              end
-              device pnp 2e.4 on		# Environment controller
-                io 0x60 = 0x290
-                io 0x62 = 0x0000
-                irq 0x70 = 0x00
-              end
-              device pnp 2e.5 on		# PS/2 keyboard
-                io 0x60 = 0x60
-                io 0x62 = 0x64
-                irq 0x70 = 1
-                irq 0x71 = 2
-              end
-              device pnp 2e.6 on		# PS/2 mouse
-                irq 0x70 = 12
-                irq 0x71 = 2
-              end
-              device pnp 2e.7 on		# GPIO config
-                io 0x60 = 0x0800
-                # Set GPIO 1 & 2
-                io 0x25 = 0x0000
-                # Set GPIO 3 & 4
-                io 0x27 = 0x2540
-                # GPIO Polarity for Set 3
-                io 0xb2 = 0x2100
-                # GPIO Pin Internal Pull up for Set 3
-                io 0xba = 0x0100
-                # Simple I/O register config
-                io 0xc0 = 0x0000
-                io 0xc2 = 0x2540
-                io 0xc8 = 0x0000
-                io 0xca = 0x0500
-              end
-              device pnp 2e.8 on		# Midi port
-                io 0x60 = 0x300
-                irq 0x70 = 10
-              end
-              device pnp 2e.9 on		# Game port
-                io 0x60 = 0x201
-              end
-              device pnp 2e.a off		# IR (N/A on this board)
-                io 0x60 = 0x310
-                irq 0x70 = 11
-              end
-            end
-          end
-          device pci 1.1 on			# SM 0
-            # chip drivers/generic/generic #dimm 0-0-0
-            #   device i2c 50 on end
-            # end
-            # chip drivers/generic/generic #dimm 0-0-1
-            #   device i2c 51 on end
-            # end
-            # chip drivers/generic/generic #dimm 0-1-0
-            #   device i2c 52 on end
-            # end
-            # chip drivers/generic/generic #dimm 0-1-1
-            #   device i2c 53 on end
-            # end
-            # chip drivers/generic/generic #dimm 1-0-0
-            #   device i2c 54 on end
-            # end
-            # chip drivers/generic/generic #dimm 1-0-1
-            #   device i2c 55 on end
-            # end
-            # chip drivers/generic/generic #dimm 1-1-0
-            #   device i2c 56 on end
-            # end
-            # chip drivers/generic/generic #dimm 1-1-1
-            #   device i2c 57 on end
-            # end
-          end
-          device pci 2.0 on end			# USB 1.1
-          device pci 2.1 on end			# USB 2
-          device pci 4.0 on end			# Onboard audio (ACI)
-          device pci 4.1 off end		# Onboard modem (MCI), N/A
-          device pci 6.0 on end			# IDE
-          device pci 7.0 on end			# SATA 1
-          device pci 8.0 on end			# SATA 0
-          device pci 9.0 on end			# PCI
-          device pci a.0 on end			# NIC
-          device pci b.0 on end			# PCI E 3
-          device pci c.0 on end			# PCI E 2
-          device pci d.0 on end			# PCI E 1
-          device pci e.0 on end			# PCI E 0
-          register "ide0_enable" = "1"
-          register "ide1_enable" = "1"
-          register "sata0_enable" = "1"
-          register "sata1_enable" = "1"
-          # register "mac_eeprom_smbus" = "3"
-          # register "mac_eeprom_addr" = "0x51"
-        end
-      end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-  end
-end
diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb
deleted file mode 100644
index a03db4b..0000000
--- a/src/mainboard/asus/a8n_e/Options.lb
+++ /dev/null
@@ -1,168 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
-## (Thanks to LSRA University of Mannheim for their support)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_AP_CODE_IN_CAR
-uses CONFIG_MEM_TRAIN_SEQ
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-uses CONFIG_PCI_64BIT_PREF_MEM
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_ID_SECTION_OFFSET
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_FAILOVER_SIZE = 4 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_HAVE_FAILOVER_BOOT = 1
-default CONFIG_HAVE_HARD_RESET = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 13
-default CONFIG_GENERATE_MP_TABLE = 1
-default CONFIG_HAVE_OPTION_TABLE = 1
-# Move the default coreboot CMOS range off of AMD RTC registers.
-default CONFIG_LB_CKS_RANGE_START = 49
-default CONFIG_LB_CKS_RANGE_END = 122
-default CONFIG_LB_CKS_LOC = 123
-# SMP support (only worry about 2 micro processors).
-default CONFIG_SMP = 1
-default CONFIG_MAX_CPUS = 2
-default CONFIG_MAX_PHYSICAL_CPUS = 1
-default CONFIG_LOGICAL_CPUS = 1
-# 1G memory hole.
-default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-# HT Unit ID offset, default is 1, the typical one.
-default CONFIG_HT_CHAIN_UNITID_BASE = 0
-# Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x10
-# Make the SB HT chain on bus 0, default is not (0).
-default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2
-# Only offset for SB chain?, default is yes(1).
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
-# default CONFIG_CONSOLE_BTEXT = 1		# BTEXT console
-default CONFIG_CONSOLE_VGA = 1			# For VGA console
-default CONFIG_PCI_ROM_RUN = 1			# For VGA console
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xc8000
-default CONFIG_DCACHE_RAM_SIZE = 32 * 1024
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024
-default CONFIG_USE_INIT = 0
-default CONFIG_AP_CODE_IN_CAR = 0
-default CONFIG_MEM_TRAIN_SEQ = 2
-default CONFIG_WAIT_BEFORE_CPUS_INIT = 0
-# default CONFIG_ENABLE_APIC_EXT_ID = 0
-# default CONFIG_APIC_ID_OFFSET = 0x10
-# default CONFIG_LIFT_BSP_APIC_ID = 0
-# default CONFIG_PCI_64BIT_PREF_MEM = 1
-default CONFIG_IOAPIC = 1
-default CONFIG_MAINBOARD_PART_NUMBER = "A8N-E"
-default CONFIG_MAINBOARD_VENDOR = "ASUS"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-# Only use the option table in a normal image.
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE)
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_GDB_STUB = 0
-default CONFIG_USE_PRINTK_IN_CAR=1
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
-default CONFIG_ID_SECTION_OFFSET = 0x80
-
-end
diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb
deleted file mode 100644
index 308a1fe..0000000
--- a/src/mainboard/asus/a8v-e_se/Config.lb
+++ /dev/null
@@ -1,190 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
-## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_ROM_PAYLOAD = 1
-
-arch i386 end 
-
-driver mainboard.o
-if CONFIG_GENERATE_ACPI_TABLES
-  object acpi_tables.o
-  makerule dsdt.c
-    depends "$(CONFIG_MAINBOARD)/dsdt.asl"
-    action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
-    action  "mv dsdt.hex dsdt.c"
-  end
-  object ./dsdt.o
-end
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-  if CONFIG_USE_INIT
-    makerule ./cache_as_ram_auto.o
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-    end
-  else
-    makerule ./cache_as_ram_auto.inc
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-      action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-      action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-    end
-  end
-
-if CONFIG_USE_FALLBACK_IMAGE
-  mainboardinit cpu/x86/16bit/entry16.inc
-  ldscript /cpu/x86/16bit/entry16.lds
-  mainboardinit southbridge/via/k8t890/romstrap.inc
-  ldscript /southbridge/via/k8t890/romstrap.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-  if CONFIG_USE_INIT
-    ldscript /cpu/x86/32bit/entry32.lds
-  end
-  if CONFIG_USE_INIT
-    ldscript /cpu/amd/car/cache_as_ram.lds
-  end
-
-if CONFIG_USE_FALLBACK_IMAGE
-  mainboardinit cpu/x86/16bit/reset16.inc
-  ldscript /cpu/x86/16bit/reset16.lds
-else
-  mainboardinit cpu/x86/32bit/reset32.inc
-  ldscript /cpu/x86/32bit/reset32.lds
-end
-
-  mainboardinit cpu/amd/car/cache_as_ram.inc
-
-if CONFIG_USE_FALLBACK_IMAGE
-    ldscript /arch/i386/lib/failover.lds
-end
-
-  if CONFIG_USE_INIT
-    initobject cache_as_ram_auto.o
-  else
-    mainboardinit ./cache_as_ram_auto.inc
-  end
-
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_939			# CPU
-      device apic 0 on end			# APIC
-    end
-  end
-  device pci_domain 0 on			# PCI domain
-    chip northbridge/amd/amdk8			# mc0
-      device pci 18.0 on			# Northbridge
-        # Devices on link 0, link 0 == LDT 0
-        chip southbridge/via/vt8237r		# Southbridge
-          register "ide0_enable" = "1"		# Enable IDE channel 0
-          register "ide1_enable" = "1"		# Enable IDE channel 1
-          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
-          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
-          register "fn_ctrl_lo" = "0"		# Enable SB functions
-          register "fn_ctrl_hi" = "0xad"	# Enable SB functions
-          device pci 0.0 on end			# HT
-          device pci f.1 on end			# IDE
-          device pci 11.0 on			# LPC
-            chip drivers/generic/generic	# DIMM 0-0-0
-              device i2c 50 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-0-1
-              device i2c 51 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-0
-              device i2c 52 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-1
-              device i2c 53 on end
-            end
-            chip superio/winbond/w83627ehg	# Super I/O
-              device pnp 2e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 2e.1 on		# Parallel port
-                io 0x60 = 0x378
-                irq 0x70 = 7
-                drq 0x74 = 3
-              end
-              device pnp 2e.2 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 2e.3 off		# Com2 (N/A on this board)
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 2e.5 off		# PS/2 keyboard (off)
-              end
-              device pnp 2e.106 off		# Serial flash
-                io 0x60 = 0x100
-              end
-              device pnp 2e.007 off		# GPIO 1
-              end
-              device pnp 2e.107 on		# Game port
-                io 0x60 = 0x201
-              end
-              device pnp 2e.207 on		# MIDI
-                io 0x62 = 0x330
-                irq 0x70 = 0xa
-              end
-              device pnp 2e.307 off		# GPIO 6
-              end
-              device pnp 2e.8 off		# WDTO_PLED
-              end
-              device pnp 2e.009 on		# GPIO 2 on LDN 9 is in sio_setup
-              end
-              device pnp 2e.109 off		# GPIO 3
-              end
-              device pnp 2e.209 off		# GPIO 4
-              end
-              device pnp 2e.309 on		# GPIO5
-              end
-              device pnp 2e.a off		# ACPI
-              end
-              device pnp 2e.b on		# Hardware monitor
-                io 0x60 = 0x290
-                irq 0x70 = 0
-              end
-            end
-          end
-          device pci 12.0 off end		# VIA LAN (off, other chip used)
-        end
-        chip southbridge/via/k8t890		# "Southbridge" K8T890
-        end
-      end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-  end
-end
diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb
deleted file mode 100644
index 92c51fe..0000000
--- a/src/mainboard/asus/a8v-e_se/Options.lb
+++ /dev/null
@@ -1,165 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License v2 as published by
-## the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-# uses CONFIG_USE_OPTION_TABLE
-# uses CONFIG_RAMTOP
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-# bx_b005+
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_USE_PRINTK_IN_CAR
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 0
-default CONFIG_GENERATE_MP_TABLE = 1
-default CONFIG_HAVE_OPTION_TABLE = 0	# FIXME
-# Move the default coreboot CMOS range off of AMD RTC registers.
-default CONFIG_LB_CKS_RANGE_START = 49
-default CONFIG_LB_CKS_RANGE_END = 122
-default CONFIG_LB_CKS_LOC = 123
-default CONFIG_SMP = 1
-default CONFIG_MAX_CPUS = 2
-default CONFIG_MAX_PHYSICAL_CPUS = 1
-default CONFIG_LOGICAL_CPUS = 1
-default CONFIG_GENERATE_ACPI_TABLES = 1
-
-# 1G memory hole
-# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
-
-# Opteron K8 1G HT support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
-
-# HT Unit ID offset, default is 1, the typical one.
-default CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-
-# Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-
-# Make the SB HT chain on bus 0, default is not (0).
-# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
-
-# bx_b005+ make the SB HT chain on bus 0.
-default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
-
-# Only offset for SB chain?, default is yes(1).
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
-
-default CONFIG_CONSOLE_VGA = 1		# Needed for VGA.
-default CONFIG_PCI_ROM_RUN = 1		# Needed for VGA.
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xcc000
-default CONFIG_DCACHE_RAM_SIZE = 0x4000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
-default CONFIG_USE_INIT = 0
-default CONFIG_ENABLE_APIC_EXT_ID = 0
-default CONFIG_APIC_ID_OFFSET = 0x10
-default CONFIG_LIFT_BSP_APIC_ID = 0
-default CONFIG_IOAPIC = 1
-default CONFIG_MAINBOARD_VENDOR = "ASUS"
-default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234	# FIXME
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 256 * 1024
-# More 1M for pgtbl.
-# default CONFIG_RAMTOP = 2048*1024
-default CONFIG_RAMBASE = 0x00004000
-# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_GDB_STUB = 0
-default CONFIG_USE_PRINTK_IN_CAR = 1
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
-end
diff --git a/src/mainboard/asus/m2v-mx_se/Config.lb b/src/mainboard/asus/m2v-mx_se/Config.lb
deleted file mode 100644
index 908d1b7..0000000
--- a/src/mainboard/asus/m2v-mx_se/Config.lb
+++ /dev/null
@@ -1,167 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
-## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end 
-
-driver mainboard.o
-if CONFIG_GENERATE_ACPI_TABLES
-  object acpi_tables.o
-  makerule dsdt.c
-    depends "$(CONFIG_MAINBOARD)/dsdt.asl"
-    action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
-    action  "mv dsdt.hex dsdt.c"
-  end
-  object ./dsdt.o
-end
-
-  if CONFIG_USE_INIT
-    makerule ./cache_as_ram_auto.o
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-    end
-  else
-    makerule ./cache_as_ram_auto.inc
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-      action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-      action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-    end
-  end
-
-if CONFIG_USE_FALLBACK_IMAGE
-  mainboardinit cpu/x86/16bit/entry16.inc
-  ldscript /cpu/x86/16bit/entry16.lds
-  mainboardinit southbridge/via/k8t890/romstrap.inc
-  ldscript /southbridge/via/k8t890/romstrap.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-  if CONFIG_USE_INIT
-    ldscript /cpu/x86/32bit/entry32.lds
-  end
-  if CONFIG_USE_INIT
-    ldscript /cpu/amd/car/cache_as_ram.lds
-  end
-
-if CONFIG_USE_FALLBACK_IMAGE
-  mainboardinit cpu/x86/16bit/reset16.inc
-  ldscript /cpu/x86/16bit/reset16.lds
-else
-  mainboardinit cpu/x86/32bit/reset32.inc
-  ldscript /cpu/x86/32bit/reset32.lds
-end
-
-  mainboardinit cpu/amd/car/cache_as_ram.inc
-
-if CONFIG_USE_FALLBACK_IMAGE
-    ldscript /arch/i386/lib/failover.lds
-end
-
-  if CONFIG_USE_INIT
-    initobject cache_as_ram_auto.o
-  else
-    mainboardinit ./cache_as_ram_auto.inc
-  end
-
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_AM2			# CPU
-      device apic 0 on end			# APIC
-    end
-  end
-  device pci_domain 0 on			# PCI domain
-    chip northbridge/amd/amdk8			# mc0
-      device pci 18.0 on			# Northbridge
-        # Devices on link 0, link 0 == LDT 0
-        chip southbridge/via/vt8237r		# Southbridge
-          register "ide0_enable" = "1"		# Enable IDE channel 0
-          register "ide1_enable" = "1"		# Enable IDE channel 1
-          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
-          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
-          register "fn_ctrl_lo" = "0xc0"	# Enable SB functions
-          register "fn_ctrl_hi" = "0x1d"	# Enable SB functions
-          device pci 0.0 on end			# HT
-          device pci f.1 on end			# IDE
-          device pci 11.0 on			# LPC
-            chip drivers/generic/generic	# DIMM 0-0-0
-              device i2c 50 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-0-1
-              device i2c 51 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-0
-              device i2c 52 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-1
-              device i2c 53 on end
-            end
-            chip superio/ite/it8712f		# Super I/O
-              device pnp 2e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 2e.1 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 2e.2 off		# Com2
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 2e.3 on		# Parallel port
-                io 0x60 = 0x378
-                irq 0x70 = 7
-              end
-              device pnp 2e.4 on		# Environment controller
-                io 0x60 = 0x290
-                io 0x62 = 0x230
-                irq 0x70 = 0x00
-              end
-              device pnp 2e.5 off end		# PS/2 keyboard
-              device pnp 2e.6 off end		# PS/2 mouse
-              device pnp 2e.7 off end		# GPIO config
-              device pnp 2e.8 off end		# Midi port
-              device pnp 2e.9 off end		# Game port
-              device pnp 2e.a off end		# IR
-	     end
-	   end
-          device pci 12.0 on end		# VIA LAN
-          device pci 13.0 on end		# br
-          device pci 13.1 on end		# br2 need to have it here to discover it
-        end
-        chip southbridge/via/k8t890		# "Southbridge" K8M890
-        end
-      end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-  end
-end
diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb
deleted file mode 100644
index eaa7168..0000000
--- a/src/mainboard/asus/m2v-mx_se/Options.lb
+++ /dev/null
@@ -1,174 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License v2 as published by
-## the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_RAMTOP
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_HAVE_LOW_TABLES
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_VGA
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-# bx_b005+
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_USE_PRINTK_IN_CAR
-
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_HAVE_HARD_RESET = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 0
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_OPTION_TABLE = 1	# FIXME
-# Move the default coreboot CMOS range off of AMD RTC registers.
-default CONFIG_LB_CKS_RANGE_START = 49
-default CONFIG_LB_CKS_RANGE_END = 122
-default CONFIG_LB_CKS_LOC = 123
-default CONFIG_SMP = 1
-default CONFIG_MAX_CPUS = 2
-default CONFIG_MAX_PHYSICAL_CPUS = 1
-default CONFIG_LOGICAL_CPUS = 1
-default CONFIG_GENERATE_ACPI_TABLES = 1
-default CONFIG_HAVE_MAINBOARD_RESOURCES = 1
-default CONFIG_HAVE_LOW_TABLES = 0
-default CONFIG_HAVE_ACPI_RESUME = 1
-
-# 1G memory hole
-# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
-
-# Opteron K8 1G HT support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
-
-# HT Unit ID offset, default is 1, the typical one.
-default CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-
-# Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-
-# Make the SB HT chain on bus 0, default is not (0).
-# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
-
-# bx_b005+ make the SB HT chain on bus 0.
-default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
-
-# Only offset for SB chain?, default is yes(1).
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
-
-default CONFIG_VGA = 1
-default CONFIG_CONSOLE_VGA = 1		# Needed for VGA.
-default CONFIG_PCI_ROM_RUN = 0		# Needed for VGA.
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xcc000
-default CONFIG_DCACHE_RAM_SIZE = 0x4000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
-default CONFIG_USE_INIT = 0
-default CONFIG_ENABLE_APIC_EXT_ID = 0
-default CONFIG_APIC_ID_OFFSET = 0x10
-default CONFIG_LIFT_BSP_APIC_ID = 0
-default CONFIG_IOAPIC = 1
-default CONFIG_MAINBOARD_VENDOR = "ASUS"
-default CONFIG_MAINBOARD_PART_NUMBER = "M2V-MX SE"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234	# FIXME
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 256 * 1024
-# More 1M for pgtbl.
-default CONFIG_RAMTOP = 32768*1024
-# to 1MB
-default CONFIG_RAMBASE = 0x1F00000
-default CONFIG_USE_OPTION_TABLE = 0
-# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_GDB_STUB = 0
-default CONFIG_USE_PRINTK_IN_CAR=1
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
-
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-end
diff --git a/src/mainboard/asus/mew-am/Config.lb b/src/mainboard/asus/mew-am/Config.lb
deleted file mode 100644
index af6423c..0000000
--- a/src/mainboard/asus/mew-am/Config.lb
+++ /dev/null
@@ -1,135 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
-	action	"../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
-	action	"../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-# TODO: On-board graphics.
-chip northbridge/intel/i82810		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/socket_PGA370	# CPU
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Graphics Memory Controller Hub (GMCH)
-    device pci 1.0 on end		# Chipset Graphics Controller (CGC)
-    chip southbridge/intel/i82801xx	# Southbridge
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-
-      device pci 1e.0 on end		# PCI bridge
-      device pci 1f.0 on		# ISA bridge
-        chip superio/smsc/smscsuperio	# Super I/O
-          device pnp 2e.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 4
-          end
-          device pnp 2e.4 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.5 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.7 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 2e.9 on		# Game port
-            io 0x60 = 0x201
-          end
-          device pnp 2e.a on		# Power-management events (PME)
-            io 0x60 = 0x600
-          end
-          device pnp 2e.b on		# MIDI port (MPU-401)
-            io 0x60 = 0x330
-            irq 0x70 = 5
-          end
-        end
-      end
-      device pci 1f.1 on end		# IDE
-      device pci 1f.2 on end		# USB
-      device pci 1f.3 on end		# SMbus
-      device pci 1f.5 off end		# AC'97 audio (N/A, uses CS4280 chip)
-      device pci 1f.6 off end		# AC'97 modem (N/A)
-    end
-  end
-end
diff --git a/src/mainboard/asus/mew-am/Options.lb b/src/mainboard/asus/mew-am/Options.lb
deleted file mode 100644
index c62bf48..0000000
--- a/src/mainboard/asus/mew-am/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 512 * 1024		# Override this in targets/*/Config.lb.
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 8		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
-default CONFIG_CONSOLE_VGA = 1		# Override this in targets/*/Config.lb.
-default CONFIG_PCI_ROM_RUN = 1		# Override this in targets/*/Config.lb.
-
-end
diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb
deleted file mode 100644
index 3cd4db2..0000000
--- a/src/mainboard/asus/mew-vm/Config.lb
+++ /dev/null
@@ -1,147 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i82810
-	device pci_domain 0 on 
-		device pci 0.0 on end # Host bridge
-		device pci 1.0 on # Onboard Video
-			#	device pci 1.0 on end
-		end
-		chip southbridge/intel/i82801xx # Southbridge
-      			register "ide0_enable" = "1"
-      			register "ide1_enable" = "1"
-
-			device pci 1e.0 on # PCI Bridge
-				#	device pci 1.0 on end
-			end
-			device pci 1f.0 on  # ISA/LPC? Bridge
-				chip superio/smsc/lpc47b272
-					device pnp 2e.0 off # Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.3 off # Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.4 on # Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.5 off # Com2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.7 on # Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1 # Keyboard interrupt
-						irq 0x72 = 12 # Mouse interrupt
-					end
-					device pnp 2e.a off end # ACPI
-				end
-			end
-			device pci 1f.1 on end # IDE
-			device pci 1f.2 on end # USB
-			device pci 1f.3 on end # SMBus
-			device pci 1f.5 off end # AC'97, no header on MEW-VM
-			device pci 1f.6 off end # AC'97 Modem (MC'97)
-		end
-	end
-	chip cpu/intel/socket_PGA370
-	end
-end
-
diff --git a/src/mainboard/asus/mew-vm/Options.lb b/src/mainboard/asus/mew-vm/Options.lb
deleted file mode 100644
index 50f0b54..0000000
--- a/src/mainboard/asus/mew-vm/Options.lb
+++ /dev/null
@@ -1,154 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 512*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE = 0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET = 0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 11
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE = 0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-default CONFIG_UDELAY_TSC=1
-
-end
diff --git a/src/mainboard/asus/p2b-d/Config.lb b/src/mainboard/asus/p2b-d/Config.lb
deleted file mode 100644
index 1170d4c..0000000
--- a/src/mainboard/asus/p2b-d/Config.lb
+++ /dev/null
@@ -1,134 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 1 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 4.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.9 on		# GPIO 3
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 4.1 on	end		# IDE
-      device pci 4.2 on	end		# USB
-      device pci 4.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "1"
-      register "ide0_drive1_udma33_enable" = "1"
-      register "ide1_drive0_udma33_enable" = "1"
-      register "ide1_drive1_udma33_enable" = "1"
-    end
-  end
-end
diff --git a/src/mainboard/asus/p2b-d/Options.lb b/src/mainboard/asus/p2b-d/Options.lb
deleted file mode 100644
index 2ccd3a9..0000000
--- a/src/mainboard/asus/p2b-d/Options.lb
+++ /dev/null
@@ -1,103 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_SMP
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 6		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_SMP = 1
-default CONFIG_MAX_CPUS = 2
-default CONFIG_IOAPIC = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-end
diff --git a/src/mainboard/asus/p2b-ds/Config.lb b/src/mainboard/asus/p2b-ds/Config.lb
deleted file mode 100644
index 4307c39..0000000
--- a/src/mainboard/asus/p2b-ds/Config.lb
+++ /dev/null
@@ -1,135 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 1 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 4.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.9 on		# GPIO 3
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 4.1 on	end		# IDE
-      device pci 4.2 on	end		# USB
-      device pci 4.3 on end		# ACPI
-      device pci 6.0 on end		# Onboard SCSI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "1"
-      register "ide0_drive1_udma33_enable" = "1"
-      register "ide1_drive0_udma33_enable" = "1"
-      register "ide1_drive1_udma33_enable" = "1"
-    end
-  end
-end
diff --git a/src/mainboard/asus/p2b-ds/Options.lb b/src/mainboard/asus/p2b-ds/Options.lb
deleted file mode 100644
index 45214cf..0000000
--- a/src/mainboard/asus/p2b-ds/Options.lb
+++ /dev/null
@@ -1,104 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_SMP
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_SMP = 1
-default CONFIG_MAX_CPUS = 2
-default CONFIG_IOAPIC = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/asus/p2b-f/Config.lb b/src/mainboard/asus/p2b-f/Config.lb
deleted file mode 100644
index 4be4b44..0000000
--- a/src/mainboard/asus/p2b-f/Config.lb
+++ /dev/null
@@ -1,132 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 4.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# Consumer IR
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 4.1 on	end		# IDE
-      device pci 4.2 on	end		# USB
-      device pci 4.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/asus/p2b-f/Options.lb b/src/mainboard/asus/p2b-f/Options.lb
deleted file mode 100644
index 6884393..0000000
--- a/src/mainboard/asus/p2b-f/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/asus/p2b/Config.lb b/src/mainboard/asus/p2b/Config.lb
deleted file mode 100644
index 559694d..0000000
--- a/src/mainboard/asus/p2b/Config.lb
+++ /dev/null
@@ -1,132 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 4.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.9 on		# GPIO 3
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 4.1 on	end		# IDE
-      device pci 4.2 on	end		# USB
-      device pci 4.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/asus/p2b/Options.lb b/src/mainboard/asus/p2b/Options.lb
deleted file mode 100644
index 0d1bb91..0000000
--- a/src/mainboard/asus/p2b/Options.lb
+++ /dev/null
@@ -1,98 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 6		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/asus/p3b-f/Config.lb b/src/mainboard/asus/p3b-f/Config.lb
deleted file mode 100644
index 628c413..0000000
--- a/src/mainboard/asus/p3b-f/Config.lb
+++ /dev/null
@@ -1,133 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-# TODO
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 4.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# Consumer IR
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 4.1 on	end		# IDE
-      device pci 4.2 on	end		# USB
-      device pci 4.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/asus/p3b-f/Options.lb b/src/mainboard/asus/p3b-f/Options.lb
deleted file mode 100644
index 1320c26..0000000
--- a/src/mainboard/asus/p3b-f/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 8		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/axus/tc320/Config.lb b/src/mainboard/axus/tc320/Config.lb
deleted file mode 100644
index e802587..0000000
--- a/src/mainboard/axus/tc320/Config.lb
+++ /dev/null
@@ -1,126 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1		# Northbridge
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 12.0 on		# ISA bridge
-        chip superio/nsc/pc97317	# Super I/O
-          device pnp 2e.0 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.1 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.2 on		# RTC, advanced power control (APC)
-            io 0x60 = 0x70
-            irq 0x70 = 8
-          end
-          device pnp 2e.3 off		# Floppy (N/A on this board)
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.4 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.5 off		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.6 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.7 on		# GPIO
-            io 0x60 = 0xe0
-          end
-          device pnp 2e.8 on		# Power management
-            io 0x60 = 0xe800
-          end
-        end
-      end
-      device pci 12.1 off end		# SMI
-      device pci 12.2 off end		# IDE
-      device pci 12.3 on end		# Audio
-      device pci 12.4 on end		# VGA (onboard)
-      device pci 13.0 on end		# USB
-      # register "ide0_enable" = "1"
-      # register "ide1_enable" = "1"
-    end
-  end
-  chip cpu/amd/model_gx1		# CPU
-  end
-end
diff --git a/src/mainboard/axus/tc320/Options.lb b/src/mainboard/axus/tc320/Options.lb
deleted file mode 100644
index b0fd16e..0000000
--- a/src/mainboard/axus/tc320/Options.lb
+++ /dev/null
@@ -1,103 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_VIDEO_MB
-uses CONFIG_SPLASH_GRAPHIC
-uses CONFIG_GX1_VIDEO
-uses CONFIG_GX1_VIDEOMODE
-uses CONFIG_PIRQ_ROUTE
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-default CONFIG_GX1_VIDEO = 1
-default CONFIG_GX1_VIDEOMODE = 0
-default CONFIG_SPLASH_GRAPHIC = 1
-default CONFIG_VIDEO_MB = 2
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_MAINBOARD_VENDOR = "AXUS"
-default CONFIG_MAINBOARD_PART_NUMBER = "TC320"
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 2	# Soldered NIC, internal USB, no real slots
-default CONFIG_PIRQ_ROUTE = 1
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
-
-end
diff --git a/src/mainboard/azza/pt-6ibd/Config.lb b/src/mainboard/azza/pt-6ibd/Config.lb
deleted file mode 100644
index b4f2224..0000000
--- a/src/mainboard/azza/pt-6ibd/Config.lb
+++ /dev/null
@@ -1,131 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# Consumer IR
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/azza/pt-6ibd/Options.lb b/src/mainboard/azza/pt-6ibd/Options.lb
deleted file mode 100644
index 6884393..0000000
--- a/src/mainboard/azza/pt-6ibd/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/bcom/winnet100/Config.lb b/src/mainboard/bcom/winnet100/Config.lb
deleted file mode 100644
index ccd4fb1..0000000
--- a/src/mainboard/bcom/winnet100/Config.lb
+++ /dev/null
@@ -1,129 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1		# Northbridge
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 0f.0 on end		# Ethernet (onboard)
-      device pci 12.0 on		# ISA bridge
-        chip superio/nsc/pc97317	# Super I/O
-          device pnp 2e.0 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.1 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.2 on		# RTC, Advanced power control (APC)
-            io 0x60 = 0x70
-            irq 0x70 = 8
-          end
-          device pnp 2e.3 off		# Floppy (N/A on this board)
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.4 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.5 on		# COM2 (used for smartcard reader)
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.6 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.7 on		# GPIO
-            io 0x60 = 0xe0
-          end
-          device pnp 2e.8 on		# Power management
-            io 0x60 = 0xe8
-          end
-        end
-      end
-      device pci 12.1 off end		# SMI
-      device pci 12.2 on end		# IDE
-      device pci 12.3 on end		# Audio
-      device pci 12.4 on end		# VGA (onboard)
-      device pci 13.0 on end		# USB
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "0"	# Not available/needed on this board
-    end
-  end
-  chip cpu/amd/model_gx1		# CPU
-  end
-end
diff --git a/src/mainboard/bcom/winnet100/Options.lb b/src/mainboard/bcom/winnet100/Options.lb
deleted file mode 100644
index d241356..0000000
--- a/src/mainboard/bcom/winnet100/Options.lb
+++ /dev/null
@@ -1,103 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_VIDEO_MB
-uses CONFIG_SPLASH_GRAPHIC
-uses CONFIG_GX1_VIDEO
-uses CONFIG_GX1_VIDEOMODE
-uses CONFIG_PIRQ_ROUTE
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-default CONFIG_GX1_VIDEO = 1
-default CONFIG_GX1_VIDEOMODE = 0
-default CONFIG_SPLASH_GRAPHIC = 1
-default CONFIG_VIDEO_MB = 2
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_MAINBOARD_VENDOR = "BCOM"
-default CONFIG_MAINBOARD_PART_NUMBER = "WinNET100"
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 2	# Soldered NIC, internal USB, no real slots
-default CONFIG_PIRQ_ROUTE = 1
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
-
-end
diff --git a/src/mainboard/bcom/winnetp680/Config.lb b/src/mainboard/bcom/winnetp680/Config.lb
deleted file mode 100644
index ed03650..0000000
--- a/src/mainboard/bcom/winnetp680/Config.lb
+++ /dev/null
@@ -1,138 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object dsdt.o
-	object acpi_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-chip northbridge/via/cn700			# Northbridge
-  device pci_domain 0 on			# PCI domain
-    device pci 0.0 on end			# AGP Bridge
-    device pci 0.1 on end			# Error Reporting
-    device pci 0.2 on end			# Host Bus Control
-    device pci 0.3 on end			# Memory Controller
-    device pci 0.4 on end			# Power Management
-    device pci 0.7 on end			# V-Link Controller
-    device pci 1.0 on end			# PCI Bridge
-    chip southbridge/via/vt8237r		# Southbridge
-      # Enable both IDE channels.
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      # Both cables are 40pin.
-      register "ide0_80pin_cable" = "0"
-      register "ide1_80pin_cable" = "0"
-      register "fn_ctrl_lo" = "0x80"
-      register "fn_ctrl_hi" = "0x1d"
-      device pci f.0 on end			# IDE
-      device pci 10.0 on end			# UHCI
-      device pci 10.1 on end			# UHCI
-      device pci 10.2 on end			# UHCI
-      device pci 10.3 on end			# UHCI
-      device pci 10.4 on end			# EHCI
-      device pci 11.0 on			# Southbridge LPC
-        chip superio/winbond/w83697hf		# Super I/O
-          device pnp 2e.0 off			# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on			# Parallel Port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 2e.2 on			# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.3 on			# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.6 off end		# Consumer IR
-          device pnp 2e.7 off end		# Game port, GPIO 1
-          device pnp 2e.8 off end		# MIDI port, GPIO 5
-          device pnp 2e.9 off end		# GPIO 2-4
-          device pnp 2e.a off end		# ACPI
-          device pnp 2e.b on			# HWM
-            io 0x60 = 0x290
-          end
-        end
-      end
-      device pci 11.5 on end			# AC'97 audio
-      device pci 12.0 on end			# Ethernet
-    end
-  end
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/via/model_c7			# VIA C7
-      device apic 0 on end			# APIC
-    end
-  end
-end
diff --git a/src/mainboard/bcom/winnetp680/Options.lb b/src/mainboard/bcom/winnetp680/Options.lb
deleted file mode 100644
index 99bd7f4..0000000
--- a/src/mainboard/bcom/winnetp680/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_VIDEO_MB
-uses CONFIG_SMP
-uses CONFIG_IOAPIC
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_SMP = 1
-default CONFIG_IOAPIC = 1
-default CONFIG_VIDEO_MB = 32
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 10
-default CONFIG_GENERATE_ACPI_TABLES = 0
-default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_USE_FALLBACK_IMAGE = 1
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default HOSTCC = "gcc"
-
-end
diff --git a/src/mainboard/biostar/m6tba/Config.lb b/src/mainboard/biostar/m6tba/Config.lb
deleted file mode 100644
index 20edbc9..0000000
--- a/src/mainboard/biostar/m6tba/Config.lb
+++ /dev/null
@@ -1,126 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/smsc/smscsuperio	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.4 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.5 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.7 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.8 on		# Aux I/O
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/biostar/m6tba/Options.lb b/src/mainboard/biostar/m6tba/Options.lb
deleted file mode 100644
index 6884393..0000000
--- a/src/mainboard/biostar/m6tba/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/broadcom/blast/Config.lb b/src/mainboard/broadcom/blast/Config.lb
deleted file mode 100644
index 238596d..0000000
--- a/src/mainboard/broadcom/blast/Config.lb
+++ /dev/null
@@ -1,235 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE 
-	object get_bus_conf.o
-	object irq_tables.o 
-end
-
-	if CONFIG_USE_INIT
-
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else    
-                
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for broadcom/blast 
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  northbridge 
-                              #  devices on link 0
-                                chip southbridge/broadcom/bcm5780 # HT2000
-                                        device pci 0.0 on end   # PXB 1 0x0130
-                                        device pci 1.0 on       # PXB 2 0x0130
-                                                device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
-                                                device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
-                                        end
-                                        device pci 2.0 on end # PCI E 1  #0x0132
-                                        device pci 3.0 on end # PCI E 2
-                                        device pci 4.0 on end # PCI E 3
-                                        device pci 5.0 on end # PCI E 4
-                                end
-                                chip southbridge/broadcom/bcm5785 # HT1000
-                                        device pci 0.0 on  # HT PXB  0x0036
-                                                device pci d.0 on end # PPBX 0x0104
-                                                device pci e.0 on end # SATA 0x024a
-                                        end
-                                        device pci 1.0 on # Legacy  pci main  0x0205
-                                                chip drivers/i2c/i2cmux2 # pca9554 smbus mux
-                                                        device i2c 71 on end #0 pca9554 0
-							device i2c 71 on end #0 pca9554 1
-							device i2c 71 on end #0 pca9554 2
-							device i2c 71 on end #0 pca9554 3
-							device i2c 71 on end #0 pca9554 4
-							device i2c 71 on end #0 pca9554 5
-                                                        device i2c 71 on #0 pca9554 6
-                                                                chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                        end
-                                                        device i2c 71 on #1 pca9554 7
-                                                                chip drivers/generic/generic #dimm 1-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                        end
-                                                end
-
-					end
-                                        device pci 1.1 on end # IDE        0x0214
-                                        device pci 1.2 on     # LPC        0x0234
-                                                chip superio/nsc/pc87417
-                                                        device  pnp 2e.0 off  # Floppy
-                                                                 io 0x60 = 0x3f0
-                                                                irq 0x70 = 6
-                                                                drq 0x74 = 2
-                                                        end
-                                                        device pnp 2e.1 off  # Parallel Port
-                                                                 io 0x60 = 0x378
-                                                                irq 0x70 = 7
-                                                        end
-                                                        device pnp 2e.2 off # Com 2
-                                                                 io 0x60 = 0x2f8
-                                                                irq 0x70 = 3
-                                                        end
-                                                        device pnp 2e.3 on  # Com 1
-                                                                 io 0x60 = 0x3f8
-                                                                irq 0x70 = 4
-                                                        end
-                                                        device pnp 2e.4 off end # SWC
-                                                        device pnp 2e.5 off end # Mouse
-                                                        device pnp 2e.6 on  # Keyboard
-                                                                 io 0x60 = 0x60
-                                                                 io 0x62 = 0x64
-                                                                irq 0x70 = 1
-                                                        end
-                                                        device pnp 2e.7 off end # GPIO
-                                                        device pnp 2e.f off end # XBUS
-                                                        device pnp 2e.10 on #RTC
-								 io 0x60 = 0x70
-								 io 0x62 = 0x72
-							end 
-                                                end
-                                        end
-                                        device pci 1.3 on end # WDTimer    0x0238
-                                        device pci 1.4 on end # XIOAPIC0   0x0235
-                                        device pci 1.5 on end # XIOAPIC1
-                                        device pci 1.6 on end # XIOAPIC2
-                                        device pci 2.0 on end # USB        0x0223
-                                        device pci 2.1 on end # USB
-                                        device pci 2.2 on end # USB
-                                        device pci 4.0 on end # it is in bcm5785_0 bus
-                                end
-			end #  device pci 18.0
-
-                        device pci 18.0 on end
-                        device pci 18.0 on end  
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-
-
-	end #pci_domain
-#        chip drivers/generic/debug
-#                device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 off end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#                device pnp 0.7 off end # tsc
-#       end
-
-end
-
diff --git a/src/mainboard/broadcom/blast/Options.lb b/src/mainboard/broadcom/blast/Options.lb
deleted file mode 100644
index 208a6c7..0000000
--- a/src/mainboard/broadcom/blast/Options.lb
+++ /dev/null
@@ -1,260 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-#default CONFIG_CONSOLE_VGA=1
-#default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset
-default CONFIG_HT_CHAIN_UNITID_BASE=0x6
-
-#real SB Unit ID
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
-
-#make the SB HT chain on bus 0
-default CONFIG_SB_HT_CHAIN_ON_BUS0=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="blast"
-default CONFIG_MAINBOARD_VENDOR="Broadcom"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
-
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb b/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb
deleted file mode 100644
index 49f1585..0000000
--- a/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb
+++ /dev/null
@@ -1,136 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    device pci a.0 on end		# NIC (onboard)
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 14.0 on		# ISA bridge
-        # chip superio/nsc/pc97307	# Super I/O
-        chip superio/nsc/pc97317	# Super I/O (FIXME: Should be PC97307!)
-          device pnp 15c.0 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 15c.1 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 15c.2 on		# RTC, APC
-            io 0x60 = 0x70
-            irq 0x70 = 8
-          end
-          device pnp 15c.3 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 15c.4 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 15c.5 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 15c.6 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 15c.7 on		# GPIO 1
-          end
-          device pnp 15c.8 on		# Power management
-          end
-        end
-      end
-      device pci 14.1 on end		# IDE
-      device pci 14.2 on end		# USB
-      device pci 14.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb b/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
deleted file mode 100644
index dd8ab02..0000000
--- a/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 5		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb
deleted file mode 100644
index cc0edc6..0000000
--- a/src/mainboard/dell/s1850/Config.lb
+++ /dev/null
@@ -1,174 +0,0 @@
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_HARD_RESET object reset.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/e7520 # mch
-	device pci_domain 0 on 
-		chip southbridge/intel/i82801er # i82801er
-			# USB ports
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.2 on end 
-			device pci 1d.3 on end
-			device pci 1d.7 on end
-		
-			# -> Bridge
-			device pci 1e.0 on end
-		
-			# -> ISA
-			device pci 1f.0 on 
-				chip superio/nsc/pc8374
-					device pnp 2e.0 off end
-					device pnp 2e.1 off end
-					device pnp 2e.2 off end
-					device pnp 2e.3 on 
-						 io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.4 off end
-					device pnp 2e.5 off end
-					device pnp 2e.6 off end
-					device pnp 2e.7 off end
-					device pnp 2e.8 off end
-				end
-			end
-			# -> IDE
-			device pci 1f.1 on end
-			# -> SATA 
-			device pci 1f.2 on end
-			device pci 1f.3 on end
-
-			register "pirq_a_d" = "0x8e8b8f80"
-			register "pirq_e_h" = "0x80808080"
-		end
-		device pci 00.0 on end 
-		device pci 00.1 on end
-		device pci 01.0 on end 
-		device pci 02.0 on 
-			chip southbridge/intel/pxhd # pxhd1
-				# Bus bridges and ioapics usually bus 1
-				device pci 0.0 on 
-				# On board gig e1000
-					chip drivers/generic/generic 
-        		        	        device pci 03.0 on end
-        		        	        device pci 03.1 on end
-        		        	end
-				end
-				device pci 0.1 on end
-				device pci 0.2 on end
-				device pci 0.3 on end
-			end
-		end
-		device pci 04.0 on end
-		device pci 06.0 on end
-	end
-	device apic_cluster 0 on
-		chip cpu/intel/socket_mPGA604 # cpu 0
-			device apic 0 on end
-		end
-		chip cpu/intel/socket_mPGA604 # cpu 1
-			device apic 6 on end
-		end
-	end
-	register "intrline" = "0x00070100"
-end
-
diff --git a/src/mainboard/dell/s1850/Options.lb b/src/mainboard/dell/s1850/Options.lb
deleted file mode 100644
index fb65f8d..0000000
--- a/src/mainboard/dell/s1850/Options.lb
+++ /dev/null
@@ -1,228 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_BTEXT
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1048576
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## Use timer2
-## 
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_LOGICAL_CPUS=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="X6DHR"
-default CONFIG_MAINBOARD_VENDOR=     "Supermicro"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-#default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-##
-## Don't enable the btext console
-##
-default  CONFIG_CONSOLE_BTEXT=0
-
-
-### End Options.lb
-end
diff --git a/src/mainboard/digitallogic/adl855pc/Config.lb b/src/mainboard/digitallogic/adl855pc/Config.lb
deleted file mode 100644
index c203231..0000000
--- a/src/mainboard/digitallogic/adl855pc/Config.lb
+++ /dev/null
@@ -1,159 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-## This does not look right but it is a literal conversion of the
-## old version of this file.
-chip northbridge/intel/i855pm
-	device pci_domain 0 on 
-		device pci 0.0 on end
-		device pci 1.0 on end
-		chip southbridge/intel/i82801dbm
-#			pci 11.0 on end
-#			pci 11.1 on end
-#			pci 11.2 on end
-#			pci 11.3 on end
-#			pci 11.4 on end
-#			pci 11.5 on end
-#			pci 11.6 on end
-#			pci 12.0 on end
-			register "enable_usb" = "0"
-			register "enable_native_ide" = "0"
-			register "enable_usb" = "0"
-			register "enable_native_ide" = "0"
-			chip superio/winbond/w83627hf # link 1
-                	        device pnp 2e.0 on      #  Floppy
-                	                 io 0x60 = 0x3f0
-                	                irq 0x70 = 6
-                	                drq 0x74 = 2
-				end
-                	        device pnp 2e.1 off     #  Parallel Port
-                	                 io 0x60 = 0x378
-                	                irq 0x70 = 7
-				end
-                	        device pnp 2e.2 on      #  Com1
-                	                 io 0x60 = 0x3f8
-                	                irq 0x70 = 4
-				end
-                	        device pnp 2e.3 off     #  Com2
-                	                io 0x60 = 0x2f8
-                	                irq 0x70 = 3
-				end
-                	        device pnp 2e.5 on      #  Keyboard
-                	                 io 0x60 = 0x60
-                	                 io 0x62 = 0x64
-                	                irq 0x70 = 1
-					irq 0x72 = 12
-				end
-                	        device pnp 2e.6 off end #  CIR
-                	        device pnp 2e.7 off end #  GAME_MIDI_GIPO1
-                	        device pnp 2e.8 off end #  GPIO2
-                	        device pnp 2e.9 off end #  GPIO3
-                	        device pnp 2e.a off end #  ACPI
-                	        device pnp 2e.b on      #  HW Monitor
- 					 io 0x60 = 0x290
-				end
-				register "com1" = "{1}"
-			#	register "com1" = "{1, 0, 0x3f8, 4}"
-			#	register "lpt" = "{1}"
-                	end
-		end
-	end
-	device apic_cluster 0 on 
-		chip cpu/intel/socket_mPGA479M
-			device apic 0 on end
-		end
-	end
-end
diff --git a/src/mainboard/digitallogic/adl855pc/Options.lb b/src/mainboard/digitallogic/adl855pc/Options.lb
deleted file mode 100644
index 5c7ee6e..0000000
--- a/src/mainboard/digitallogic/adl855pc/Options.lb
+++ /dev/null
@@ -1,107 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_UDELAY_IO
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 1024*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## use io based udelay function
-##
-default CONFIG_UDELAY_IO=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=5
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-end
diff --git a/src/mainboard/digitallogic/msm586seg/Config.lb b/src/mainboard/digitallogic/msm586seg/Config.lb
deleted file mode 100644
index dbd3e64..0000000
--- a/src/mainboard/digitallogic/msm586seg/Config.lb
+++ /dev/null
@@ -1,111 +0,0 @@
-default CONFIG_ROM_SIZE = 512 * 1024 
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 32 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-
-# VGA console
-if CONFIG_CONSOLE_VGA
-	default CONFIG_PCI_ROM_RUN=1
-end
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-dir /devices
-config chip.h
-
-chip cpu/amd/sc520
-	device pci_domain 0 on 
-		device pci 0.0 on end
-		device pci 12.0 on end # enet
-		device pci 14.0 on end # 69000
-#		register "com1" = "{1}"
-#		register "com1" = "{1, 0, 0x3f8, 4}"
-	end
-
-end
diff --git a/src/mainboard/digitallogic/msm586seg/Options.lb b/src/mainboard/digitallogic/msm586seg/Options.lb
deleted file mode 100644
index 1bd5cae..0000000
--- a/src/mainboard/digitallogic/msm586seg/Options.lb
+++ /dev/null
@@ -1,121 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_COMPRESS
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_USE_INIT
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-
-uses CONFIG_CONSOLE_SERIAL8250
-
-
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-
-# VGA support
-uses CONFIG_CONSOLE_VGA
-#uses CONFIG_LEGACY_VGABIOS
-#uses VGABIOS_START
-uses CONFIG_PCI_ROM_RUN
-
-
-default CONFIG_CONSOLE_SERIAL8250=1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=2
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-end
diff --git a/src/mainboard/digitallogic/msm800sev/Config.lb b/src/mainboard/digitallogic/msm800sev/Config.lb
deleted file mode 100644
index 5965cc1..0000000
--- a/src/mainboard/digitallogic/msm800sev/Config.lb
+++ /dev/null
@@ -1,170 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-	#compile cache_as_ram.c to auto.inc
-	makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-#	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/lx
-  	device pci_domain 0 on 
-    		device pci 1.0 on end
-		device pci 1.1 on end
-      		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
-			# How to get these? Boot linux and do this:
-			# rdmsr 0x51400025
-			register "lpc_serirq_enable" = "0x0000105a"
-			# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
-			register "lpc_serirq_polarity" = "0x0000EFA5"
-			# mode is high 10 bits (determined from code)
-			register "lpc_serirq_mode" = "1"
-			# Don't yet know how to find this.
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "0"	#0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "0"
-			register "com1_address" = "0x3F8"
-			register "com1_irq" = "4"
-			register "com2_enable" = "0"
-			register "com2_address" = "0x2F8"
-			register "com2_irq" = "3"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-        			device pci f.0 on	# ISA Bridge
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 off #  Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.1 off #  Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.2 on #  Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on #  Com2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.5 on #  Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-					device pnp 2e.6 off #  CIR
-						io 0x60 = 0x100
-					end
-					device pnp 2e.7 off #  GAME_MIDI_GIPO1
-						io 0x60 = 0x220
-						io 0x62 = 0x300
-						irq 0x70 = 9
-					end						
-					device pnp 2e.8 off end #  GPIO2
-					device pnp 2e.9 off end #  GPIO3
-					device pnp 2e.a off end #  ACPI
-					device pnp 2e.b on #  HW Monitor
-						io 0x60 = 0x290
-						irq 0x70 = 5
-					end
-				end
-			end
-			device pci f.1 on end	# Flash controller
-			device pci f.2 on end	# IDE controller
-        			device pci f.3 on end 	# Audio
-        			device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-      		end
-	end
-
-	# APIC cluster is late CPU init.
-	device apic_cluster 0 on
-		chip cpu/amd/model_lx
-			device apic 0 on end
-		end
-	end
-
-end
-
diff --git a/src/mainboard/digitallogic/msm800sev/Options.lb b/src/mainboard/digitallogic/msm800sev/Options.lb
deleted file mode 100644
index 88e2a1f..0000000
--- a/src/mainboard/digitallogic/msm800sev/Options.lb
+++ /dev/null
@@ -1,180 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_VIDEO_MB=8
-default CONFIG_PCI_ROM_RUN=0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=9
-default CONFIG_PIRQ_ROUTE=1
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 32768
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/eaglelion/5bcm/Config.lb b/src/mainboard/eaglelion/5bcm/Config.lb
deleted file mode 100644
index 64e833f..0000000
--- a/src/mainboard/eaglelion/5bcm/Config.lb
+++ /dev/null
@@ -1,150 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1
-  device pci_domain 0 on 
-    device pci 0.0 on end
-      chip southbridge/amd/cs5530
-        device pci 12.0 on
-          chip superio/nsc/pc97317
-            device pnp 2e.0 on		# Keyboard
-               io 0x60 = 0x60
-               io 0x62 = 0x64
-              irq 0x70 = 1
-            end
-            device pnp 2e.1 on		# Mouse
-              irq 0x70 = 12
-            end
-            device pnp 2e.2 on		# RTC
-               io 0x60 = 0x70
-              irq 0x70 = 8
-            end
-            device pnp 2e.3 off		# FDC
-            end
-            device pnp 2e.4 on		# Parallel Port
-               io 0x60 = 0x378
-              irq 0x70 = 7
-            end
-            device pnp 2e.5 on		# COM2
-               io 0x60 = 0x2f8
-              irq 0x70 = 3
-            end
-            device pnp 2e.6 on		# COM1
-               io 0x60 = 0x3f8
-              irq 0x70 = 4
-            end
-            device pnp 2e.7 on		# GPIO
-               io 0x60 = 0xe0
-            end
-            device pnp 2e.8 on		# Power Management
-               io 0x60 = 0xe800
-            end
-            register "com1" = "{115200}"
-            register "com2" = "{38400}"
-          end
-        device pci 12.1 off end		# SMI
-        device pci 12.2 on  end		# IDE
-        device pci 12.3 off end 	# Audio
-        device pci 12.4 off end		# VGA
-      end
-    end
-  end
-
-  chip cpu/amd/model_gx1
-  end
-
-end
-
diff --git a/src/mainboard/eaglelion/5bcm/Options.lb b/src/mainboard/eaglelion/5bcm/Options.lb
deleted file mode 100644
index fb2bfae..0000000
--- a/src/mainboard/eaglelion/5bcm/Options.lb
+++ /dev/null
@@ -1,164 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_VIDEO_MB
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=2
-default CONFIG_PIRQ_ROUTE=1
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-default CONFIG_VIDEO_MB = 0
-
-end
diff --git a/src/mainboard/emulation/qemu-x86/Config.lb b/src/mainboard/emulation/qemu-x86/Config.lb
deleted file mode 100644
index 7357648..0000000
--- a/src/mainboard/emulation/qemu-x86/Config.lb
+++ /dev/null
@@ -1,131 +0,0 @@
-## we don't use CONFIG_USE_DCACHE_RAM by default
-default CONFIG_USE_DCACHE_RAM=0
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-default CONFIG_ROM_SIZE = 256 * 1024 
-default CONFIG_ROM_SECTION_SIZE   = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_ROM_SECTION_OFFSET = CONFIG_ROM_SIZE - CONFIG_ROM_SECTION_SIZE
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default CONFIG_ROMBASE      = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
-##
-default CONFIG_XIP_ROM_SIZE=32*1024
-default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-
-## ALL dependencies for CONFIG_USE_DCACHE_RAM go here. 
-## That way, later, we can simply yank them if we wish. 
-## We include the old-fashioned entry code in the ! CONFIG_USE_DCACHE_RAM case. 
-## we do not use failover yet in this case. This is a work in progress. 
-if CONFIG_USE_DCACHE_RAM
-	##
-	##
-	mainboardinit arch/i386/init/entry.S
-	mainboardinit arch/i386/init/car.S
-	ldscript  /arch/i386/init/ldscript.ld
-
-	## The main code for the rom section is called rom.c
-	initobject rom.o
-else
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-		depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
-		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-	end
-	
-	makerule ./failover.inc
-		depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-	end
-	
-	makerule ./auto.E 
-		depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-		action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-	end
-	makerule ./auto.inc 
-		depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-		action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-	end
-	
-	##
-	## Build our 16 bit and 32 bit coreboot entry code
-	##
-	mainboardinit cpu/x86/16bit/entry16.inc
-	mainboardinit cpu/x86/32bit/entry32.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-	ldscript /cpu/x86/32bit/entry32.lds
-
-	##
-	## Build our reset vector (This is where coreboot is entered)
-	##
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-	
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-
-	##
-	## Setup RAM
-	##
-	mainboardinit cpu/x86/fpu_enable.inc
-	mainboardinit ./auto.inc
-	
-	## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future. 
-	##
-	## Include an id string (For safe flashing)
-	##
-	mainboardinit arch/i386/lib/id.inc
-	ldscript /arch/i386/lib/id.lds
-	
-##
-## end of CONFIG_USE_DCACHE_RAM bits. 
-##
-end
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip cpu/emulation/qemu-x86
-	device pci_domain 0 on 
-		device pci 0.0 on end
-
-		chip southbridge/intel/i82371eb # southbridge
-			device pci 01.0 on end
-			device pci 01.1 on end
-			register "ide0_enable" = "1"
-			register "ide1_enable" = "1"
-		end
-
-#		register "com1" = "{1}"
-#		register "com1" = "{1, 0, 0x3f8, 4}"
-	end
-end
diff --git a/src/mainboard/emulation/qemu-x86/Options.lb b/src/mainboard/emulation/qemu-x86/Options.lb
deleted file mode 100644
index e067128..0000000
--- a/src/mainboard/emulation/qemu-x86/Options.lb
+++ /dev/null
@@ -1,140 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_COMPRESS
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_WRITE_HIGH_TABLES
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-
-uses CONFIG_UDELAY_IO
-default CONFIG_UDELAY_IO=1
-
-default CONFIG_CONSOLE_SERIAL8250=1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=6
-
-default CONFIG_WRITE_HIGH_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Option ROM init
-##
-default CONFIG_PCI_ROM_RUN=1
-default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## known-good settings for qemu
-default CONFIG_DCACHE_RAM_BASE=0x8f000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-
-
-
-
-end
diff --git a/src/mainboard/gigabyte/ga-6bxc/Config.lb b/src/mainboard/gigabyte/ga-6bxc/Config.lb
deleted file mode 100644
index 663f58e..0000000
--- a/src/mainboard/gigabyte/ga-6bxc/Config.lb
+++ /dev/null
@@ -1,130 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/ite/it8671f	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.2 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.4 on		# APC
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 3f0.6 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 3f0.7 on		# GPIO
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/gigabyte/ga-6bxc/Options.lb b/src/mainboard/gigabyte/ga-6bxc/Options.lb
deleted file mode 100644
index 8189979..0000000
--- a/src/mainboard/gigabyte/ga-6bxc/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 6		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
deleted file mode 100644
index 6cca586..0000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
+++ /dev/null
@@ -1,270 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
-## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	if CONFIG_USE_INIT
-		makerule ./cache_as_ram_auto.o
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./cache_as_ram_auto.inc
-        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_CPU_OPT) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-        makerule ./apc_auto.o
-                depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-                action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-        end
-        ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit southbridge/sis/sis966/romstrap.inc
-	ldscript /southbridge/sis/sis966/romstrap.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit southbridge/sis/sis966/romstrap.inc
-	ldscript /southbridge/sis/sis966/romstrap.lds
-    end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_AM2
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on
-				#  devices on link 0, link 0 == LDT 0
-			        chip southbridge/sis/sis966
-					device pci 0.0 on end   # Northbridge
-					device pci 1.0 on		# AGP bridge
-						device pci 0.0 on end
-					end
-                			device pci 2.0 on # LPC
-						chip superio/ite/it8716f
-							device pnp 2e.0 off #  Floppy (N/A)
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.2 off #  Com2 (N/A)
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.3 off #  Parallel port (N/A)
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.4 on #  EC
-                	                 			io 0x60 = 0x290
-                	                 			io 0x62 = 0x230
-                	                			irq 0x70 = 9
-							end
-							device pnp 2e.5 off #  PS/2 keyboard (N/A)
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-							end
-							device pnp 2e.6 off #  Mouse (N/A)
-                	                			irq 0x70 = 12
-							end
-                	        			device pnp 2e.8 off #  MIDI (N/A)
-								io 0x60 = 0x300
-								irq 0x70 = 10
-							end
-                	        			device pnp 2e.9 off #  GAME (N/A)
-								io 0x60 = 0x220
-							end
-                	        			device pnp 2e.a off end #  CIR (N/A)
-						end
-					end
-
-                                        device pci 2.5 off end # IDE (SiS5513)
-                                        device pci 2.6 off end # Modem (SiS7013)
-                                        device pci 2.7 off end # Audio (SiS7012)
-                                        device pci 3.0 on end # USB (SiS7001,USB1.1)
-                                        device pci 3.1 on end # USB (SiS7001,USB1.1)
-                                        device pci 3.3 on end # USB (SiS7002,USB2.0)
-                                        device pci 4.0 on end # NIC (SiS191)
-                                        device pci 5.0 on end # SATA (SiS1183,Native Mode)
-                                        device pci 6.0 on end # PCI-e x1
-                                        device pci 7.0 on end # PCI-e x1
-                                        device pci a.0 off end
-                                        device pci b.0 off end
-                                        device pci c.0 off end
-                                        device pci d.0 off end
-                                        device pci e.0 off end
-                                        device pci f.0 off end # HD Audio (SiS7502)
-
-                                        register "ide0_enable" = "1"
-                                        register "ide1_enable" = "1"
-                                        register "sata0_enable" = "1"
-                                        register "sata1_enable" = "1"
-				end
-			end #  device pci 18.0
-			device pci 18.0 on end # Link 1
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end # mc0
-
-	end # PCI domain
-
-#       chip drivers/generic/debug
-#               device pnp 0.0 off end # chip name
-#               device pnp 0.1 on end # pci_regs_all
-#               device pnp 0.2 off end # mem
-#               device pnp 0.3 off end # cpuid
-#               device pnp 0.4 off end # smbus_regs_all
-#               device pnp 0.5 off end # dual core msr
-#               device pnp 0.6 off end # cache size
-#               device pnp 0.7 off end # tsc
-#               device pnp 0.8 off end # io
-#               device pnp 0.9 off end # io
-#       end
-end #root_complex
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
deleted file mode 100644
index 6cbef12..0000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
+++ /dev/null
@@ -1,354 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
-## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_USBDEBUG_DIRECT
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ID_SECTION_OFFSET
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-#default CONFIG_ROM_SIZE=0x100000
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-#FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#FAILOVER: 4K
-default CONFIG_FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=0
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#default CONFIG_USBDEBUG_DIRECT=0
-
-#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default CONFIG_HT_CHAIN_UNITID_BASE=0
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_AP_CODE_IN_CAR=0
-default CONFIG_MEM_TRAIN_SEQ=2
-default CONFIG_WAIT_BEFORE_CPUS_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="ga_2761gxdk"
-default CONFIG_MAINBOARD_VENDOR="GIGABYTE"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-#default CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-### End Options.lb
-end
diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb
deleted file mode 100644
index c84d73c..0000000
--- a/src/mainboard/gigabyte/m57sli/Config.lb
+++ /dev/null
@@ -1,362 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	if CONFIG_USE_INIT
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-	makerule ./apc_auto.o
-		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-	end
-	ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
-	object fanctl.o
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## ACPI Support
-##
-if CONFIG_GENERATE_ACPI_TABLES
-	object acpi_tables.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dsdt.asl"
-		action  "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
-		action  "mv $(CURDIR)/dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_AM2
-			device apic 0 on end
-		end
-end
-device pci_domain 0 on
-	chip northbridge/amd/amdk8 #mc0
-		device pci 18.0 on #  devices on link 0, link 0 == LDT 0
-			chip southbridge/nvidia/mcp55
-				device pci 0.0 on end # HT
-				device pci 1.0 on # LPC
-					chip superio/ite/it8716f
-						# Floppy and any LDN
-						device pnp 2e.0 on
-							# Watchdog from CLKIN, CLKIN = 24 MHz
-							irq 0x23 = 0x11
-							# Serial Flash (SPI only)
-							#0x24 = 0x1a
-							io 0x60 = 0x3f0
-							irq 0x70 = 6
-							drq 0x74 = 2
-						end
-						device pnp 2e.1 on # Com1
-							io 0x60 = 0x3f8
-							irq 0x70 = 4
-						end
-						device pnp 2e.2 off # Com2
-							io 0x60 = 0x2f8
-							irq 0x70 = 3
-						end
-						device pnp 2e.3 on #  Parallel Port
-							io 0x60 = 0x378
-							irq 0x70 = 7
-						end
-						device pnp 2e.4 on #  EC
-							io 0x60 = 0x290
-							io 0x62 = 0x230
-							irq 0x70 = 9
-						end
-						device pnp 2e.5 on #  Keyboard
-							io 0x60 = 0x60
-							io 0x62 = 0x64
-							irq 0x70 = 1
-						end
-						device pnp 2e.6 on #  Mouse
-							irq 0x70 = 12
-						end
-						device pnp 2e.7 on #  GPIO, SPI flash
-						# pin 84 is not GP10
-							irq 0x25 = 0x0
-						# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
-							irq 0x26 = 0x43
-						# pin 13 is GP35
-							irq 0x27 = 0x20
-						# pin 70 is not GP46
-							#irq 0x28 = 0x0
-						# pin 6,3,128,127,126 is GP63,64,65,66,67
-							irq 0x29 = 0x81
-						# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
-							#irq 0x2c = 0x1f
-						# Simple I/O base
-							io 0x62 = 0x800
-						# Serial Flash I/O (SPI only)
-							io 0x64 = 0x820
-						# watch dog force timeout (parallel flash only)
-							#irq 0x71 = 0x1
-						# No WDT interrupt
-							irq 0x72 = 0x0
-						# GPIO pin set 1 disable internal pullup
-							irq 0xb8 = 0x0
-						# GPIO pin set 5 enable internal pullup
-							irq 0xbc = 0x01
-						# SIO pin set 1 alternate function
-							#irq 0xc0 = 0x0
-						# SIO pin set 2 mixed function
-							irq 0xc1 = 0x43
-						# SIO pin set 3 mixed function
-							irq 0xc2 = 0x20
-						# SIO pin set 4 alternate function
-							#irq 0xc3 = 0x0
-						# SIO pin set 1 input mode
-							#irq 0xc8 = 0x0
-						# SIO pin set 2 input mode
-							irq 0xc9 = 0x0
-						# SIO pin set 4 input mode
-							#irq 0xcb = 0x0
-						# Generate SMI# on EC IRQ
-							#irq 0xf0 = 0x10
-						# SMI# level trigger
-							#irq 0xf1 = 0x40
-						# HWMON alert beep pin location
-							irq 0xf6 = 0x28
-						end
-						device pnp 2e.8 off #  MIDI
-							io 0x60 = 0x300
-							irq 0x70 = 10
-						end
-						device pnp 2e.9 off #  GAME
-							io 0x60 = 0x220
-						end
-						device pnp 2e.a off end #  CIR
-					end
-				end
-				device pci 1.1 on # SM 0
-					chip drivers/generic/generic #dimm 0-0-0
-						device i2c 50 on end
-					end
-					chip drivers/generic/generic #dimm 0-0-1
-						device i2c 51 on end
-					end
-					chip drivers/generic/generic #dimm 0-1-0
-						device i2c 52 on end
-					end
-					chip drivers/generic/generic #dimm 0-1-1
-						device i2c 53 on end
-					end
-					chip drivers/generic/generic #dimm 1-0-0
-						device i2c 54 on end
-					end
-					chip drivers/generic/generic #dimm 1-0-1
-						device i2c 55 on end
-					end
-					chip drivers/generic/generic #dimm 1-1-0
-						device i2c 56 on end
-					end
-					chip drivers/generic/generic #dimm 1-1-1
-						device i2c 57 on end
-					end
-				end # SM
-#WTF?!? We already have device pci 1.1 in the section above
-				device pci 1.1 on # SM 1
-					chip drivers/generic/generic #MAC EEPROM
-						device i2c 51 on end
-					end
-				end # SM
-				device pci 2.0 on end # USB 1.1
-				device pci 2.1 on end # USB 2
-				device pci 4.0 on end # IDE
-				device pci 5.0 on end # SATA 0
-				device pci 5.1 on end # SATA 1
-				device pci 5.2 on end # SATA 2
-				device pci 6.0 on end # PCI
-				device pci 6.1 on end # AZA
-				device pci 8.0 on end # NIC
-				device pci 9.0 off end # NIC
-				device pci a.0 on end # PCI E 5
-				device pci b.0 on end # PCI E 4
-				device pci c.0 on end # PCI E 3
-				device pci d.0 on end # PCI E 2
-				device pci e.0 on end # PCI E 1
-				device pci f.0 on end # PCI E 0
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "sata1_enable" = "1"
-					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end #device pci 18.0
-			device pci 18.0 on end # Link 1
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end # mc0
-	end # PCI domain
-
-#	chip drivers/generic/debug
-#		device pnp 0.0 off end # chip name
-#		device pnp 0.1 on end # pci_regs_all
-#		device pnp 0.2 on end # mem
-#		device pnp 0.3 off end # cpuid
-#		device pnp 0.4 on end # smbus_regs_all
-#		device pnp 0.5 off end # dual core msr
-#		device pnp 0.6 off end # cache size
-#		device pnp 0.7 off end # tsc
-#		device pnp 0.8 off  end # io
-#		device pnp 0.9 off end # io
-#	end
-end #root_complex
diff --git a/src/mainboard/gigabyte/m57sli/Options.lb b/src/mainboard/gigabyte/m57sli/Options.lb
deleted file mode 100644
index 3010a2a..0000000
--- a/src/mainboard/gigabyte/m57sli/Options.lb
+++ /dev/null
@@ -1,364 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_USBDEBUG_DIRECT
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_WRITE_HIGH_TABLES
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
-
-uses CONFIG_ID_SECTION_OFFSET
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-#default CONFIG_ROM_SIZE=0x100000
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-#FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#FAILOVER: 4K
-default CONFIG_FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Set-up automatic fan control
-##
-default CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL=1
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## HIGH tables support
-default CONFIG_WRITE_HIGH_TABLES=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#default CONFIG_USBDEBUG_DIRECT=1
-
-#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default CONFIG_HT_CHAIN_UNITID_BASE=0
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_AP_CODE_IN_CAR=0
-default CONFIG_MEM_TRAIN_SEQ=2
-default CONFIG_WAIT_BEFORE_CPUS_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="m57sli"
-default CONFIG_MAINBOARD_VENDOR="GIGABYTE"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-#default CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/hp/dl145_g3/Config.lb b/src/mainboard/hp/dl145_g3/Config.lb
deleted file mode 100644
index 6c0508e..0000000
--- a/src/mainboard/hp/dl145_g3/Config.lb
+++ /dev/null
@@ -1,210 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## Copyright (C) 2007 University of Mannheim
-## Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
-##
-## Copyright (C) 2009 University of Heidelberg
-## Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-	makerule ./auto.o
-		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-	end
-else
-	makerule ./auto.inc
-		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-
-# config for hp/dl145_g3
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_F
-			device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8  # northbridge
-			device pci 18.0 on  # devices on link 0
-				chip southbridge/broadcom/bcm21000 # HT2100
-					device pci 0.0 on
-					end   # bridge to slot PCI-E 4x ??
-					device pci 1.0 on
-					end
-					device pci 2.0 on
-					end  # unused
-					device pci 3.0 on  	# bridge to slot PCI-E 16x ??
-					end
-					device pci 4.0 on
-					end  # unused
-					device pci 5.0 on
-						device pci 4.0 on end # BCM5715 NIC
-						device pci 4.1 on end # BCM5715 NIC
-					end
-				end
-				chip southbridge/broadcom/bcm5785 # HT1000
-					device pci 0.0 on  # HT PXB  0x0036
-						device pci d.0 on end # PCI/PCI-X bridge 0x0104
-						device pci e.0 on end # SATA 0x024a
-					end
-					device pci 1.0 on end # Legacy  pci main  0x0205
-					device pci 1.1 on end # IDE	0x0214
-					device pci 1.2 on     # LPC	0x0234
-						chip superio/nsc/pc87417
-							device  pnp 4e.0 off  # Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 4e.1 off  # Parallel Port
-									io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 4e.2 off # Com 2
-									io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 4e.3 off  # Com 1
-									io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 4e.4 off end # SWC
-							device pnp 4e.5 off end # Mouse
-							device pnp 4e.6 off  # Keyboard
-									io 0x60 = 0x60
-									io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 4e.7 off end # GPIO
-							device pnp 4e.f off end # XBUS
-							device pnp 4e.10 on #RTC
-								io 0x60 = 0x70
-								io 0x62 = 0x72
-							end
-						end # end superio
-					end # end pci 1.2
-					device pci 1.3 off end # WDTimer    0x0238
-					device pci 1.4 on end # XIOAPIC0   0x0235
-					device pci 1.5 on end # XIOAPIC1
-					device pci 1.6 on end # XIOAPIC2
-					device pci 2.0 on end # USB	0x0223
-					device pci 2.1 on end # USB
-					device pci 2.2 on end # USB
-					device pci 3.0 on end # VGA
-				end
-			end
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-      end # amdk8
-
-   end #pci_domain
-end
-
-
diff --git a/src/mainboard/hp/dl145_g3/Options.lb b/src/mainboard/hp/dl145_g3/Options.lb
deleted file mode 100644
index 5ae7fb2..0000000
--- a/src/mainboard/hp/dl145_g3/Options.lb
+++ /dev/null
@@ -1,328 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## Copyright (C) 2007 University of Mannheim
-## Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for Uni Mannheim
-## Copyright (C) 2009 University of Heidelberg
-## Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=15
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x8
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=0
-
-#HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0x06
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcc000
-default CONFIG_DCACHE_RAM_SIZE=0x04000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="DL145 G3"
-default CONFIG_MAINBOARD_VENDOR="HP"
-#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-#enabel printk in CAR by default
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/hp/e_vectra_p2706t/Config.lb b/src/mainboard/hp/e_vectra_p2706t/Config.lb
deleted file mode 100644
index c158b81..0000000
--- a/src/mainboard/hp/e_vectra_p2706t/Config.lb
+++ /dev/null
@@ -1,128 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-# TODO: i810E actually!
-chip northbridge/intel/i82810			# Northbridge
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/intel/socket_PGA370		# CPU
-      device apic 0 on end			# APIC
-    end
-  end
-  device pci_domain 0 on
-    device pci 0.0 on end			# Host bridge
-    device pci 1.0 on end			# Onboard VGA
-    chip southbridge/intel/i82801xx		# Southbridge
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-
-      device pci 1e.0 on end			# PCI bridge
-      device pci 1f.0 on			# ISA/LPC bridge
-        # TODO: PC87364 actually!
-        # TODO: Check Super I/O settings and compare to superiotool -d.
-        chip superio/nsc/pc87360		# Super I/O
-          device pnp 2e.0 on			# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on			# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 2e.2 on			# Com2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.3 on			# Com1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.4 off end		# SWC
-          device pnp 2e.5 off end		# PS/2 mouse
-          device pnp 2e.6 on			# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.7 off end		# GPIO
-          device pnp 2e.8 off end		# ACB
-          device pnp 2e.9 off end		# FSCM
-          device pnp 2e.a off end		# WDT
-        end
-      end
-      device pci 1f.1 on end			# IDE
-      device pci 1f.2 on end			# USB
-      device pci 1f.3 on end			# SMBus
-      device pci 1f.5 on end			# AC'97 audio
-      device pci 1f.6 off end			# AC'97 modem (N/A ?)
-    end
-  end
-end
-
diff --git a/src/mainboard/hp/e_vectra_p2706t/Options.lb b/src/mainboard/hp/e_vectra_p2706t/Options.lb
deleted file mode 100644
index ff43b4f..0000000
--- a/src/mainboard/hp/e_vectra_p2706t/Options.lb
+++ /dev/null
@@ -1,101 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VGA_ROM_RUN
-uses CONFIG_WRITE_HIGH_TABLES
-uses CONFIG_VIDEO_MB
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 3
-default CONFIG_MAINBOARD_VENDOR = "HP"
-default CONFIG_MAINBOARD_PART_NUMBER = "e-Vectra P2706T"
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-default CONFIG_VGA_ROM_RUN = 1
-default CONFIG_WRITE_HIGH_TABLES = 1
-default CONFIG_VIDEO_MB = 1
-end
diff --git a/src/mainboard/ibm/e325/Config.lb b/src/mainboard/ibm/e325/Config.lb
deleted file mode 100644
index ad37aba..0000000
--- a/src/mainboard/ibm/e325/Config.lb
+++ /dev/null
@@ -1,185 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-
-chip northbridge/amd/amdk8/root_complex
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on end # LDT 0
-			device pci 18.0 on     # LDT 1
-				chip southbridge/amd/amd8131
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 on end
-						device pci 1.0 off end
-					end
-					device pci 1.0 on
-						chip superio/nsc/pc87366
-							device	pnp 2e.0 off  # Floppy 
-								 io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off  # Parallel Port
-								 io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 off # Com 2
-								 io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.3 on  # Com 1
-								 io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.4 off end # SWC
-							device pnp 2e.5 off end # Mouse
-							device pnp 2e.6 on  # Keyboard
-								 io 0x60 = 0x60
-								 io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 2e.7 off end # GPIO
-							device pnp 2e.8 off end # ACB
-							device pnp 2e.9 off end # FSCM
-							device pnp 2e.a off end # WDT  
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on end
-					device pci 1.5 off end
-					device pci 1.6 off end
-				end
-			end #  device pci 18.0 
-			device pci 18.0 on end # LDT2
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-		chip northbridge/amd/amdk8
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-		end
-	end 
-	device apic_cluster 0 on
-		chip cpu/amd/socket_940
-			device apic 0 on end
-		end
-		chip cpu/amd/socket_940
-			device apic 1 on end
-		end
-	end
-end
-
diff --git a/src/mainboard/ibm/e325/Options.lb b/src/mainboard/ibm/e325/Options.lb
deleted file mode 100644
index a745e18..0000000
--- a/src/mainboard/ibm/e325/Options.lb
+++ /dev/null
@@ -1,221 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=12
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=1
-default CONFIG_MAX_PHYSICAL_CPUS=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
- 
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="E325"
-default CONFIG_MAINBOARD_VENDOR="IBM"
-#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/ibm/e326/Config.lb b/src/mainboard/ibm/e326/Config.lb
deleted file mode 100644
index 08109ee..0000000
--- a/src/mainboard/ibm/e326/Config.lb
+++ /dev/null
@@ -1,178 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_940
-			device apic 0 on end
-		end
-	end
-
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on end # LDT 0
-			device pci 18.0 on     # LDT 1
-				chip southbridge/amd/amd8131
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 on end
-						device pci 1.0 off end
-                                               device pci 5.0 on end # ATI Rage XL
-					end
-					device pci 1.0 on
-						chip superio/nsc/pc87366
-							device	pnp 2e.0 off  # Floppy 
-								 io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off  # Parallel Port
-								 io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 off # Com 2
-								 io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.3 on  # Com 1
-								 io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.4 off end # SWC
-							device pnp 2e.5 off end # Mouse
-							device pnp 2e.6 on  # Keyboard
-								 io 0x60 = 0x60
-								 io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 2e.7 off end # GPIO
-							device pnp 2e.8 off end # ACB
-							device pnp 2e.9 off end # FSCM
-							device pnp 2e.a off end # WDT  
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on end
-					device pci 1.5 off end
-					device pci 1.6 off end
-					register "ide0_enable" = "1"
-					register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0 
-			device pci 18.0 on end # LDT2
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-	end 
-end
-
diff --git a/src/mainboard/ibm/e326/Options.lb b/src/mainboard/ibm/e326/Options.lb
deleted file mode 100644
index 265ae75..0000000
--- a/src/mainboard/ibm/e326/Options.lb
+++ /dev/null
@@ -1,227 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=12
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-#VGA
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
- 
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="E326"
-default CONFIG_MAINBOARD_VENDOR="IBM"
-#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/iei/juki-511p/Config.lb b/src/mainboard/iei/juki-511p/Config.lb
deleted file mode 100644
index c87ea5c..0000000
--- a/src/mainboard/iei/juki-511p/Config.lb
+++ /dev/null
@@ -1,157 +0,0 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-default CONFIG_ROM_SIZE = 256 * 1024 
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default CONFIG_ROMBASE      = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
-##
-default CONFIG_XIP_ROM_SIZE=65536
-default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-mainboardinit cpu/x86/16bit/reset16.inc 
-ldscript /cpu/x86/16bit/reset16.lds 
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-#dir /pc80
-#config chip.h
-
-chip northbridge/amd/gx1
-  device pci_domain 0 on
-    device pci 0.0 on end
-      chip southbridge/amd/cs5530
-
-        device pci 12.0 on
-          chip superio/winbond/w83977f
-            device pnp 3f0.0 on		# FDC
-              irq 0x70 = 6
-            end
-            device pnp 3f0.1 on		# Parallel port
-              io 0x60 = 0x378
-              irq 0x70 = 7
-            end
-            device pnp 3f0.2 on		# COM1
-              io 0x60 = 0x3f8
-              irq 0x70 = 4
-            end
-            register "com1" = "{115200}"
-            device pnp 3f0.3 on		# COM2
-              io 0x60 = 0x2f8
-              irq 0x70 = 3
-            end
-            register "com2" = "{115200}"
-            device pnp 3f0.4 on		# RTC
-              io 0x60 = 0x070
-              irq 0x70 = 8
-            end
-            device pnp 3f0.5 on		# Keyboard
-              io 0x60 = 0x60
-              io 0x62 = 0x64
-              irq 0x70 = 1		# Int  1 for PS/2 keyboard
-              irq 0x72 = 12		# Int 12 for PS/2 mouse
-            end
-            device pnp 3f0.6 off	# IR
-            end
-            device pnp 3f0.7 off	# GPIO1
-            end
-            device pnp 3f0.8 off	# GPIO
-            end
-          end
-        device pci 12.1 on end		# SMI
-        device pci 12.2 on end		# IDE
-        device pci 12.3 on end		# Audio
-        device pci 12.4 on end		# VGA onboard
-
-      end
-
-      device pci 0e.0 on end		# ETH0
-      device pci 13.0 on end		# USB
-
-    end
-  end
-
-  chip cpu/amd/model_gx1
-  end
-
-end
-
diff --git a/src/mainboard/iei/juki-511p/Options.lb b/src/mainboard/iei/juki-511p/Options.lb
deleted file mode 100644
index d7fde57..0000000
--- a/src/mainboard/iei/juki-511p/Options.lb
+++ /dev/null
@@ -1,145 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_UDELAY_IO
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_COMPRESS
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_VIDEO_MB
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-default CONFIG_UDELAY_IO=1
-##
-## Build code to export a programmable irq routing table
-##
-# FIXME: There's an irq_tables.c file, but CONFIG_GENERATE_PIRQ_TABLE is 0.
-default CONFIG_GENERATE_PIRQ_TABLE=0
-default CONFIG_IRQ_SLOT_COUNT=2
-default CONFIG_PIRQ_ROUTE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-default CONFIG_VIDEO_MB = 0
-
-end
diff --git a/src/mainboard/iei/nova4899r/Config.lb b/src/mainboard/iei/nova4899r/Config.lb
deleted file mode 100644
index 3fd6ce7..0000000
--- a/src/mainboard/iei/nova4899r/Config.lb
+++ /dev/null
@@ -1,163 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-#dir /pc80
-#config chip.h
-
-chip northbridge/amd/gx1
-  device pci_domain 0 on
-    device pci 0.0 on end
-      chip southbridge/amd/cs5530
-        device pci 0a.0 on  end		# ETH0
-        device pci 0b.0 off end		# ETH1
-        device pci 0c.0 on  end		# ETH2
-        device pci 0f.0 on  end		# PCI slot
-        device pci 12.0 on
-          chip superio/winbond/w83977tf
-            device pnp 2e.0 on		# FDC
-              irq 0x70 = 6
-            end
-            device pnp 2e.1 on		# Parallel Port
-               io 0x60 = 0x378
-              irq 0x70 = 7
-            end
-            device pnp 2e.2 on		# COM1
-               io 0x60 = 0x3f8
-              irq 0x70 = 4
-            end
-            register "com1" = "{115200}"
-            device pnp 2e.3 on		# COM2
-               io 0x60 = 0x2f8
-              irq 0x70 = 3
-            end
-            register "com2" = "{115200}"
-            device pnp 2e.4 off		# Reserved
-            end
-            device pnp 2e.5 on		# Keyboard
-               io 0x60 = 0x60
-               io 0x62 = 0x64
-              irq 0x70 = 0x01		# Int  1 for PS/2 keyboard
-              irq 0x72 = 0x0c		# Int 12 for PS/2 mouse
-            end
-            device pnp 2e.6 on		# IR
-               io 0x60 = 0x2e8
-              irq 0x70 = 3
-            end
-            device pnp 2e.7 on		# GAME/MIDI/GPIO1
-               io 0x60 = 0x290
-            end
-            device pnp 2e.8 on		# GPIO2
-               io 0x60 = 0x110
-            end
-            device pnp 2e.9 on		# GPIO3
-               io 0x60 = 0x120
-            end
-            device pnp 2e.A on		# Power Management
-               io 0x60 = 0xe800
-            end
-          end
-        device pci 12.1 on  end		# SMI
-        device pci 12.2 on  end		# IDE
-        device pci 12.3 on  end		# Audio
-        device pci 12.4 on  end		# VGA onboard
-      end
-      device pci 13.0 on end		# USB
-    end
-  end
-
-  chip cpu/amd/model_gx1
-  end
-
-end
-
diff --git a/src/mainboard/iei/nova4899r/Options.lb b/src/mainboard/iei/nova4899r/Options.lb
deleted file mode 100644
index 564a441..0000000
--- a/src/mainboard/iei/nova4899r/Options.lb
+++ /dev/null
@@ -1,172 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_VIDEO_MB
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=0
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=5
-default CONFIG_PIRQ_ROUTE=1
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-default CONFIG_VIDEO_MB = 0
-
-end
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb
deleted file mode 100644
index 39fc0df..0000000
--- a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb
+++ /dev/null
@@ -1,136 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-	# Compile cache_as_ram.c to auto.inc.
-	makerule ./cache_as_ram_auto.inc
-			# depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-#	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-dir /pc80
-config chip.h
-
-chip northbridge/amd/lx
-	device pci_domain 0 on
-		device pci 1.0 on end				# Northbridge
-		device pci 1.1 on end				# Graphics
-		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
-			register "lpc_serirq_enable" = "0x0000105a"
-			register "lpc_serirq_polarity" = "0x0000EFA5"
-			register "lpc_serirq_mode" = "1"
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0"	# 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "1"	# 0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "0"
-			register "com1_address" = "0x3F8"
-			register "com1_irq" = "4"
-			register "com2_enable" = "0"
-			register "com2_address" = "0x2F8"
-			register "com2_irq" = "3"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci 9.0 on end			# Slot1
-			device pci a.0 on end			# Slot2
-			device pci b.0 on end			# Slot3
-			device pci c.0 on end			# Slot4
-			device pci e.0 on end			# Ethernet 0
-			device pci 10.0 on end			# Ethernet 1
-			device pci 11.0 on end			# SATA
-			device pci f.0 on			# ISA Bridge
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 off	# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.1 off	# Parallel port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.2 on	# Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on	# Com2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.5 on	# Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-					device pnp 2e.6 off end	# CIR
-					device pnp 2e.7 off end	# GAME_MIDI_GIPO1
-					device pnp 2e.8 off end	# GPIO2
-					device pnp 2e.9 off end	# GPIO3
-					device pnp 2e.a off end	# ACPI
-					device pnp 2e.b off end	# HW Monitor
-				end
-			end
-			device pci f.2 on end			# IDE Controller
-			device pci f.3 on end			# Audio
-			device pci f.4 on end			# OHCI
-			device pci f.5 on end			# EHCI
-		end
-	end
-	# APIC cluster is late CPU init.
-	device apic_cluster 0 on
-		chip cpu/amd/model_lx
-			device apic 0 on end
-		end
-	end
-end
-
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Options.lb b/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
deleted file mode 100644
index 6ff46bf..0000000
--- a/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
+++ /dev/null
@@ -1,106 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESS
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_IO
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_VIDEO_MB = 8
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_IO = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 9
-default CONFIG_PIRQ_ROUTE = 1
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_ROM_IMAGE_SIZE = 32 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xc8000
-default CONFIG_DCACHE_RAM_SIZE = 32 * 1024
-default CONFIG_USE_PRINTK_IN_CAR=1
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/intel/d945gclf/Config.lb b/src/mainboard/intel/d945gclf/Config.lb
deleted file mode 100644
index 6671471..0000000
--- a/src/mainboard/intel/d945gclf/Config.lb
+++ /dev/null
@@ -1,228 +0,0 @@
-##
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-## 
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Image size calculation
-##
-
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-driver rtl8168.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object acpi_tables.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dsdt.asl"
-		action  "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD)  $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl"
-		action  "iasl -p dsdt -tc $(CURDIR)/dsdt.asl"
-		action  "mv $(CURDIR)/dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
-	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I.  -c $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-else
-
-makerule ./auto.inc
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
-	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
-	action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-	action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-if CONFIG_USE_INIT
-	ldscript /cpu/x86/32bit/entry32.lds
-	ldscript /cpu/x86/car/cache_as_ram.lds
-end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-        mainboardinit cpu/x86/16bit/reset16.inc
-        ldscript /cpu/x86/16bit/reset16.lds
-else
-        mainboardinit cpu/x86/32bit/reset32.inc
-        ldscript /cpu/x86/32bit/reset32.lds
-end
-
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/intel/model_106cx/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i945
-
-        device apic_cluster 0 on
-                chip cpu/intel/socket_441
-                        device apic 0 on end
-                end
-        end
-
-        device pci_domain 0 on 
-                device pci 00.0 on end # host bridge
-		device pci 01.0 off end # i945 PCIe root port
-		device pci 02.0 on end # vga controller
-		device pci 02.1 on end # display controller
-
-                chip southbridge/intel/i82801gx
-			register "pirqa_routing" = "0x05"
-			register "pirqb_routing" = "0x07"
-			register "pirqc_routing" = "0x05"
-			register "pirqd_routing" = "0x07"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x06"
-
-			# GPI routing
-			#  0 No effect (default)
-			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
-			#  2 SCI (if corresponding GPIO_EN bit is also set)
-			register "gpi13_routing" = "1"
-			register "gpe0_en" = "0x20000601"
-
-                        register "ide_legacy_combined" = "0x1"
-                        register "ide_enable_primary" = "0x1"
-                        register "ide_enable_secondary" = "0x0"
-                        register "sata_ahci" = "0x0"
-
-                	device pci 1b.0 on end # High Definition Audio
-                	device pci 1c.0 on end # PCIe
-                	device pci 1c.1 on end # PCIe
-                	device pci 1c.2 on end # PCIe
-			#device pci 1c.3 off end # PCIe port 4
-			#device pci 1c.4 off end # PCIe port 5
-			#device pci 1c.5 off end # PCIe port 6
-                	device pci 1d.0 on end # USB UHCI
-                	device pci 1d.1 on end # USB UHCI
-                	device pci 1d.2 on end # USB UHCI
-                	device pci 1d.3 on end # USB UHCI
-                	device pci 1d.7 on end # USB2 EHCI
-                	device pci 1e.0 on end # PCI bridge
-			#device pci 1e.2 off end # AC'97 Audio 
-			#device pci 1e.3 off end # AC'97 Modem
-                        device pci 1f.0 on # LPC bridge
-                                chip superio/smsc/lpc47m15x
-					device pnp 2e.0 off		# Floppy
-					end
-					device pnp 2e.3 off		# Parport
-					end
-                                        device pnp 2e.4 on
-                                                 io 0x60 = 0x3f8
-                                                irq 0x70 = 4
-                                        end
-                                        device pnp 2e.5 on
-                                                 io 0x60 = 0x2f8
-                                                irq 0x70 = 3
-						irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
-                                        end
-					device pnp 2e.7 on		# Keyboard+Mouse
-						 io 0x60 = 0x60
-						 io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-						irq 0xf0 = 0x82		# HW accel A20.
-					end
-					device pnp 2e.8 on		# GAME
-						# all default
-					end
-					device pnp 2e.a on		# PME
-					end
-					device pnp 2e.b on		# MPU
-					end
-                                end
-                        end
-			#device pci 1f.1 off end # IDE
-                        device pci 1f.2 on end  # SATA
-                        device pci 1f.3 on end  # SMBus
-			#device pci 1f.4 off end # Realtek ID Codec
-                end
-        end
-end
diff --git a/src/mainboard/intel/d945gclf/Options.lb b/src/mainboard/intel/d945gclf/Options.lb
deleted file mode 100644
index 9660b9f..0000000
--- a/src/mainboard/intel/d945gclf/Options.lb
+++ /dev/null
@@ -1,329 +0,0 @@
-##
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-# Tables
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-# SMP
-uses CONFIG_SMP
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_AP_IN_SIPI_WAIT
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-# Image Size
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-# Payload
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-# Build Internals
-uses CONFIG_RAMBASE
-uses CONFIG_ROMBASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_SMI_HANDLER
-uses CONFIG_PCIE_CONFIGSPACE_HOLE
-uses CONFIG_MMCONF_SUPPORT
-uses CONFIG_MMCONF_BASE_ADDRESS
-uses CONFIG_GFXUMA
-
-#
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-# Timers
-uses CONFIG_UDELAY_LAPIC
-# Console
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_VGA_ROM_RUN
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_DEBUG
-# Toolchain
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-# Tweaks
-uses CONFIG_GDB_STUB
-uses CONFIG_MAX_REBOOT_CNT
-uses CONFIG_USE_WATCHDOG_ON_BOOT
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-
-###
-### Build options
-###
-
-##
-##
-default CONFIG_MAX_REBOOT_CNT=3
-
-##
-## Use the watchdog to break out of a lockup condition
-##
-default CONFIG_USE_WATCHDOG_ON_BOOT=0
-
-##
-## ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=CONFIG_FALLBACK_SIZE*2
-
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## 
-default CONFIG_UDELAY_LAPIC=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build SMI handler
-##
-default CONFIG_HAVE_SMI_HANDLER=1
-
-##
-## Leave a hole for mmapped PCIe config space
-##
-
-default CONFIG_PCIE_CONFIGSPACE_HOLE=1
-default CONFIG_MMCONF_SUPPORT=1
-default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
-
-##
-## UMA
-##
-default CONFIG_GFXUMA=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=18
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to provide ACPI support
-##
-default CONFIG_GENERATE_ACPI_TABLES=1
-default CONFIG_HAVE_MAINBOARD_RESOURCES=1
-default CONFIG_HAVE_ACPI_RESUME=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default CONFIG_coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-# There are some network option roms that don't work with
-# coreboot's x86emu. Thus, we only execute the VGA option rom
-# for now:
-default CONFIG_VGA_ROM_RUN=1
-default CONFIG_PCI_ROM_RUN=0
-default CONFIG_DEBUG=0
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-default CONFIG_AP_IN_SIPI_WAIT=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_DCACHE_RAM_BASE=0xffed8000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Execute In Place settings
-##
-
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
-default CONFIG_MAINBOARD_VENDOR=     "INTEL"
-
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x464c
-
-###
-### coreboot layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 0xb800
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
-## At a maximum only compile in this level of debugging
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/intel/eagleheights/Config.lb b/src/mainboard/intel/eagleheights/Config.lb
deleted file mode 100644
index ea76cad..0000000
--- a/src/mainboard/intel/eagleheights/Config.lb
+++ /dev/null
@@ -1,212 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-##
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object acpi_tables.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
-		action  "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
-		action  "mv $(CURDIR)/dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-if CONFIG_HAVE_HARD_RESET object reset.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
-	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-else
-
-makerule ./auto.inc
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
-	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
-	action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-	action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-if CONFIG_USE_INIT
-	ldscript /cpu/x86/32bit/entry32.lds
-	ldscript /cpu/x86/car/cache_as_ram.lds
-end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/reset16.inc
-        ldscript /cpu/x86/16bit/reset16.lds
-else
-        mainboardinit cpu/x86/32bit/reset32.inc
-        ldscript /cpu/x86/32bit/reset32.lds
-end
-
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-## Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
-mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i3100
-        device pci_domain 0 on
-                device pci 00.0 on end # IMCH
-                device pci 00.1 on end # IMCH error status
-                device pci 01.0 on end # IMCH EDMA engine
-                device pci 02.0 on end # PCIe port A/A0
-                device pci 03.0 on end # PCIe port A1
-                chip southbridge/intel/i3100
-                        # PIRQ line -> legacy IRQ mappings
-			register "pirq_a_d" = "0x8b808a8a"
-                        register "pirq_e_h" = "0x85808080"
-
-                        device pci 1c.0 on end # PCIe port B0
-                        device pci 1c.1 off end # PCIe port B1
-                        device pci 1c.2 off end # PCIe port B2
-                        device pci 1c.3 off end # PCIe port B3
-                        device pci 1d.0 on end # USB (UHCI) 1
-                        device pci 1d.1 on end # USB (UHCI) 2
-                        device pci 1d.7 on end # USB (EHCI)
-                        device pci 1e.0 on end # PCI bridge
-                        device pci 1f.0 on     # LPC bridge
-                                chip superio/intel/i3100
-                                        device pnp 4e.4 on # Com1
-                                                 io 0x60 = 0x3f8
-                                                irq 0x70 = 4
-                                        end
-                                        device pnp 4e.5 on # Com2
-                                                 io 0x60 = 0x2f8
-                                                irq 0x70 = 3
-                                        end
-                                end
-				chip superio/smsc/smscsuperio
-					device pnp 2e.0 off	# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.2 off	# Serial Port 4
-						io 0x60 = 0x2e8
-						irq 0x70 = 3
-					end
-					device pnp 2e.3 on	# Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-						drq 0x74 = 2
-					end
-					device pnp 2e.4 off	# Serial Port 3
-						io 0x60 = 0x3e8
-						irq 0x70 = 4
-					end
-					device pnp 2e.7 on	# PS/2 Keyboard / Mouse
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1    # PS/2 keyboard interrupt
-						irq 0x72 = 12   # PS/2 mouse interrupt
-					end
-					device pnp 2e.a off     # Runtime registers
-					       io 0x60 = 0x600
-					end
-				end
-                        end
-                        device pci 1f.2 on end # SATA
-                        device pci 1f.3 on end # SMBus
-			device pci 1f.4 on end # Performance counters
-                end
-        end
-        device apic_cluster 0 on
-                chip cpu/intel/bga956
-                        device apic 0 on end
-                end
-        end
-end
-
diff --git a/src/mainboard/intel/eagleheights/Options.lb b/src/mainboard/intel/eagleheights/Options.lb
deleted file mode 100644
index 3a2e7b6..0000000
--- a/src/mainboard/intel/eagleheights/Options.lb
+++ /dev/null
@@ -1,323 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-# Tables
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-# SMP
-uses CONFIG_SMP
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_AP_IN_SIPI_WAIT
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-# Image Size
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-# Payload
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-# Build Internals
-uses CONFIG_RAMBASE
-uses CONFIG_ROMBASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_SMI_HANDLER
-uses CONFIG_PCIE_CONFIGSPACE_HOLE
-uses CONFIG_MMCONF_SUPPORT
-uses CONFIG_MMCONF_BASE_ADDRESS
-#
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-# Timers
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-# Console
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_VGA_ROM_RUN
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_DEBUG
-uses CONFIG_VGA
-uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
-# Toolchain
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-# Tweaks
-uses CONFIG_GDB_STUB
-uses CONFIG_MAX_REBOOT_CNT
-uses CONFIG_USE_WATCHDOG_ON_BOOT
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-
-###
-### Build options
-###
-
-##
-##
-default CONFIG_MAX_REBOOT_CNT=3
-
-##
-## Use the watchdog to break out of a lockup condition
-##
-default CONFIG_USE_WATCHDOG_ON_BOOT=0
-
-##
-## ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1024*1024
-
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## Use timer2
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build SMI handler
-##
-default CONFIG_HAVE_SMI_HANDLER=0
-
-##
-## Leave a hole for mmapped PCIe config space
-##
-default CONFIG_PCIE_CONFIGSPACE_HOLE=1
-default CONFIG_MMCONF_SUPPORT=1
-default CONFIG_MMCONF_BASE_ADDRESS=0xE0000000
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to provide ACPI support
-##
-default CONFIG_GENERATE_ACPI_TABLES=1
-default CONFIG_HAVE_MAINBOARD_RESOURCES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=0
-# There are some network option roms that don't work with
-# coreboot's x86emu. Thus, we only execute the VGA option rom
-# for now:
-default CONFIG_VGA_ROM_RUN=0
-default CONFIG_PCI_ROM_RUN=0
-default CONFIG_DEBUG=0
-
-#default CONFIG_VGA=0
-#default CONFIG_PCI_OPTION_ROM_RUN_YABEL=0
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-default CONFIG_AP_IN_SIPI_WAIT=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024)
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="EagleHeights"
-default CONFIG_MAINBOARD_VENDOR=     "Intel"
-
-###
-### coreboot layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-default CONFIG_PRECOMPRESSED_PAYLOAD=1
-default CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-#default CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-## At a maximum only compile in this level of debugging
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb
deleted file mode 100644
index 722ba40..0000000
--- a/src/mainboard/intel/jarrell/Config.lb
+++ /dev/null
@@ -1,182 +0,0 @@
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_HARD_RESET object reset.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/e7520
-	device pci_domain 0 on 
-		device pci 00.0 on end
-		device pci 00.1 on end
-		device pci 01.0 on end
-		device pci 02.0 on 
-			chip southbridge/intel/pxhd # pxhd1
-				device pci 00.0 on end
-				device pci 00.1 on end
-				device pci 00.2 on
-					chip drivers/generic/generic
-						device pci 04.0 on end
-						device pci 04.1 on end
-					end
-				end
-				device pci 00.3 on end
-			end
-		end
-		device pci 06.0 on end
-		chip southbridge/intel/i82801er # i82801er
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.2 on end
-			device pci 1d.3 off end
-			device pci 1d.7 on end
-			device pci 1e.0 on
-				chip drivers/ati/ragexl
-					device pci 0c.0 on end
-				end
-			end
-			device pci 1f.0 on 
-				chip superio/nsc/pc87427
-					device pnp 2e.0 off end
-					device pnp 2e.2 on
-#						 io 0x60 = 0x2f8
-#						irq 0x70 = 3
-						 io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on
-#						 io 0x60 = 0x3f8
-#						irq 0x70 = 4
-						 io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.4 off end
-					device pnp 2e.5 off end
-					device pnp 2e.6 on
-						 io 0x60 = 0x60
-						 io 0x62 = 0x64
-						irq 0x70 = 1
-					end
-					device pnp 2e.7 off end
-					device pnp 2e.9 off end
-					device pnp 2e.a off end
-					device pnp 2e.f on end
-					device pnp 2e.10 off end
-					device pnp 2e.14 off end
-				end
-			end
-			device pci 1f.1 on end
-			device pci 1f.2 off end
-			device pci 1f.3 on end 
-			device pci 1f.5 off end
-			device pci 1f.6 off end
-			register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
-			register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW"
-			register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
-		end
-	end
-	device apic_cluster 0 on
-		chip cpu/intel/socket_mPGA604 # cpu 0
-			device apic 0 on end
-		end
-		chip cpu/intel/socket_mPGA604 # cpu 1
-			device apic 6 on end
-		end
-	end
-end
diff --git a/src/mainboard/intel/jarrell/Options.lb b/src/mainboard/intel/jarrell/Options.lb
deleted file mode 100644
index 91927ee..0000000
--- a/src/mainboard/intel/jarrell/Options.lb
+++ /dev/null
@@ -1,242 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_BTEXT
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-uses CONFIG_MAX_REBOOT_CNT
-uses CONFIG_USE_WATCHDOG_ON_BOOT
-
-
-###
-### Build options
-###
-
-##
-## Because we do the stutter start we need more attempts
-##
-default CONFIG_MAX_REBOOT_CNT=8
-
-##
-## Use the watchdog to break out of a lockup condition
-##
-default CONFIG_USE_WATCHDOG_ON_BOOT=1
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=2097152
-
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## Use timer2
-## 
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=18
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_LOGICAL_CPUS=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="SE7520JR22D"
-default CONFIG_MAINBOARD_VENDOR=     "Intel"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079
-#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-##
-## Don't enable the btext console
-##
-default  CONFIG_CONSOLE_BTEXT=0
-
-
-### End Options.lb
-end
diff --git a/src/mainboard/intel/mtarvon/Config.lb b/src/mainboard/intel/mtarvon/Config.lb
deleted file mode 100644
index 026c45d..0000000
--- a/src/mainboard/intel/mtarvon/Config.lb
+++ /dev/null
@@ -1,160 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-        action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-        action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/reset16.inc
-        ldscript /cpu/x86/16bit/reset16.lds
-else
-        mainboardinit cpu/x86/32bit/reset32.inc
-        ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-        ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i3100
-        device pci_domain 0 on
-                device pci 00.0 on end # IMCH
-                device pci 00.1 on end # IMCH error status
-                device pci 01.0 on end # IMCH EDMA engine
-                device pci 02.0 on end # PCIe port A/A0
-                device pci 03.0 on end # PCIe port A1
-                chip southbridge/intel/i3100
-                        # PIRQ line -> legacy IRQ mappings
-                        register "pirq_a_d" = "0x0b070a05"
-                        register "pirq_e_h" = "0x0a808080"
-
-                        device pci 1c.0 on end # PCIe port B0
-                        device pci 1c.1 on end # PCIe port B1
-                        device pci 1c.2 on end # PCIe port B2
-                        device pci 1c.3 on end # PCIe port B3
-                        device pci 1d.0 on end # USB (UHCI) 1
-                        device pci 1d.1 on end # USB (UHCI) 2
-                        device pci 1d.7 on end # USB (EHCI)
-                        device pci 1e.0 on end # PCI bridge
-                        device pci 1e.2 on end # audio
-                        device pci 1e.3 on end # modem
-                        device pci 1f.0 on     # LPC bridge
-                                chip superio/intel/i3100
-                                        device pnp 4e.4 on # Com1
-                                                 io 0x60 = 0x3f8
-                                                irq 0x70 = 4
-                                        end
-                                        device pnp 4e.5 on # Com2
-                                                 io 0x60 = 0x2f8
-                                                irq 0x70 = 3
-                                        end
-                                end
-                        end
-                        device pci 1f.2 on end # SATA
-                        device pci 1f.3 on end # SMBus
-                end
-        end
-        device apic_cluster 0 on
-                chip cpu/intel/socket_mPGA479M
-                        device apic 0 on end
-                end
-        end
-end
diff --git a/src/mainboard/intel/mtarvon/Options.lb b/src/mainboard/intel/mtarvon/Options.lb
deleted file mode 100644
index 7d99620..0000000
--- a/src/mainboard/intel/mtarvon/Options.lb
+++ /dev/null
@@ -1,225 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE = 2 * 1024 * 1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## Use timer2
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=1
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_LOGICAL_CPUS=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="Mt. Arvon"
-default CONFIG_MAINBOARD_VENDOR=     "Intel"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
-
-###
-### Coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/intel/truxton/Config.lb b/src/mainboard/intel/truxton/Config.lb
deleted file mode 100644
index 5e03248..0000000
--- a/src/mainboard/intel/truxton/Config.lb
+++ /dev/null
@@ -1,170 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-        action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-        action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/reset16.inc
-        ldscript /cpu/x86/16bit/reset16.lds
-else
-        mainboardinit cpu/x86/32bit/reset32.inc
-        ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-        ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i3100
-        device pci_domain 0 on
-                device pci 00.0 on end # IMCH
-                device pci 00.1 on end # IMCH error status
-                device pci 01.0 on end # IMCH EDMA engine
-                device pci 02.0 on end # PCIe port A/A0
-                device pci 03.0 on end # PCIe port A1
-                device pci 04.0 on end # ?
-                device pci 08.0 off end # must be off to boot
-                device pci 0d.0 off end # must be off to boot
-                device pci 0d.1 off end # must be off to boot
-                chip southbridge/intel/i3100
-                        # PIRQ line -> legacy IRQ mappings
-                        register "pirq_a_d" = "0x0b070a05"
-                        register "pirq_e_h" = "0x0a808080"
-
-                        device pci 1d.0 on end  # USB (UHCI)
-                        device pci 1d.7 on end  # USB (EHCI)
-                        device pci 1f.0 on      # LPC bridge
-                                chip superio/intel/i3100
-                                        device pnp 4e.4 on # Com1
-                                                 io 0x60 = 0x3f8
-                                                irq 0x70 = 4
-                                        end
-                                        device pnp 4e.5 on # Com2
-                                                 io 0x60 = 0x2f8
-                                                irq 0x70 = 3
-                                        end
-				end
-				chip superio/smsc/smscsuperio
-					device pnp 2e.0 off end
-					device pnp 2e.3 off end
-					device pnp 2e.4 off end
-					device pnp 2e.5 off end
-					device pnp 2e.7 on # PS/2 keyboard / mouse
-            					io 0x60 = 0x60
-            					io 0x62 = 0x64
-            					irq 0x70 = 1	# PS/2 keyboard interrupt
-            					irq 0x72 = 12	# PS/2 mouse interrupt
-					end
-					device pnp 2e.a off end
-                                end
-                        end
-                        device pci 1f.2 on end  # SATA
-                        device pci 1f.3 on end  # SMBus
-                        device pci 1f.4 on end  # ?
-                end
-        end
-        device apic_cluster 0 on
-                chip cpu/intel/ep80579
-                        device apic 0 on end
-                end
-        end
-end
diff --git a/src/mainboard/intel/truxton/Options.lb b/src/mainboard/intel/truxton/Options.lb
deleted file mode 100644
index dab3f45..0000000
--- a/src/mainboard/intel/truxton/Options.lb
+++ /dev/null
@@ -1,236 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_RAMTOP
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE = 2 * 1024 * 1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## Use timer2
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=1
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_LOGICAL_CPUS=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="Truxton"
-default CONFIG_MAINBOARD_VENDOR=     "Intel"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
-
-###
-### Coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## in order to have coreboot running at 0x100000, RAMTOP has to be set
-##
-default CONFIG_RAMTOP = 2*1024*1024
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-# Enable the VGA console.
-default CONFIG_CONSOLE_VGA=1
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-
-end
diff --git a/src/mainboard/intel/xe7501devkit/Config.lb b/src/mainboard/intel/xe7501devkit/Config.lb
deleted file mode 100644
index 1f0534c..0000000
--- a/src/mainboard/intel/xe7501devkit/Config.lb
+++ /dev/null
@@ -1,174 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE 		object mptable.o 	 end
-if CONFIG_GENERATE_PIRQ_TABLE 		object irq_tables.o	 end
-if CONFIG_GENERATE_ACPI_TABLES 	object acpi_tables.o end
-if CONFIG_HAVE_HARD_RESET object reset.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FALLBACK_BOOT
-    if CONFIG_USE_FALLBACK_IMAGE 
-	    mainboardinit cpu/x86/16bit/reset16.inc 
-	    ldscript /cpu/x86/16bit/reset16.lds
-    else
-	    mainboardinit cpu/x86/32bit/reset32.inc 
-	    ldscript /cpu/x86/32bit/reset32.lds 
-    end
-else
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-
-config chip.h
-
-# based on sample config for tyan/s2735
-chip northbridge/intel/e7501
-	device pci_domain 0 on
-		device pci 0.0 on end # Chipset host controller
-		device pci 0.1 on end # Host RASUM controller
-		device pci 2.0 on # Hub interface B
-			chip southbridge/intel/i82870 # P64H2
-				device pci 1c.0 on end # IOAPIC - bus B
-				device pci 1d.0 on end # Hub to PCI-B bridge
-				device pci 1e.0 on end # IOAPIC - bus A
-				device pci 1f.0 on end # Hub to PCI-A bridge
-			end
-		end
-		device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
-		device pci 4.0 on # Hub interface D
-			chip southbridge/intel/i82870 # P64H2
-				device pci 1c.0 on end # IOAPIC - bus B
-				device pci 1d.0 on end # Hub to PCI-B bridge
-				device pci 1e.0 on end # IOAPIC - bus A
-				device pci 1f.0 on end # Hub to PCI-A bridge
-			end
-		end
-		device pci 6.0 on end # E7501 Power management registers? (undocumented)
-		chip southbridge/intel/i82801ca
-			device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
-			device pci 1d.1 off end # USB (not populated)
-			device pci 1d.2 off end # USB (not populated)
-			device pci 1e.0 on # Hub to PCI bridge
-				device pci 0.0 on end
-			end
-			device pci 1f.0 on # LPC bridge
-				chip superio/smsc/lpc47b272
-					device pnp 2e.0 off # Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.3 off # Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.4 on # Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.5 off # Com2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.7 on # Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1 # Keyboard interrupt
-						irq 0x72 = 12 # Mouse interrupt
-					end
-					device pnp 2e.a off end # ACPI
-				end
-			end
-			device pci 1f.1 on end # IDE
-			device pci 1f.3 on end # SMBus
-			device pci 1f.5 off end # AC97 Audio
-			device pci 1f.6 off end # AC97 Modem
-		end # SB
-	end # PCI_DOMAIN
-	device apic_cluster 0 on
-		chip cpu/intel/socket_mPGA604
-			device apic 0 on end
-		end
-		chip cpu/intel/socket_mPGA604
-			device apic 6 on end
-		end
-	end
-end
diff --git a/src/mainboard/intel/xe7501devkit/Options.lb b/src/mainboard/intel/xe7501devkit/Options.lb
deleted file mode 100644
index 6968f31..0000000
--- a/src/mainboard/intel/xe7501devkit/Options.lb
+++ /dev/null
@@ -1,238 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAX_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_DEBUG
-#uses CONFIG_CPU_OPT
-
-## These are defined in target Config.lb, don't add here
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_FALLBACK_SIZE
-uses COREBOOT_EXTRA_VERSION
-
-## These are defined in mainboard Config.lb, don't add here
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-
-uses CONFIG_HAVE_HARD_RESET
-
-default CONFIG_HAVE_HARD_RESET = 1
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=2097152
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Build code for the fallback boot?
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=12
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## Build code to export ACPI tables?
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table?
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-## CMOS checksum definitions (units == bytes)
-## These must match the checksum record in cmos.layout
-default CONFIG_LB_CKS_RANGE_START=128
-default CONFIG_LB_CKS_RANGE_END=130
-default CONFIG_LB_CKS_LOC=131
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs,
-##		 so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4.
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_LOGICAL_CPUS=0
-default CONFIG_MAX_PHYSICAL_CPUS=2
-
-# VGA Console
-# NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS
-#	    to VGA.rom
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_PCI_ROM_RUN=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Motherboard identification
-##
-default CONFIG_MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT"
-default CONFIG_MAINBOARD_VENDOR="Intel"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480
-
-###
-### coreboot layout values
-###
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## CMOS settings not currently supported due to conflicts with factory BIOS
-##
-default CONFIG_USE_OPTION_TABLE = 0
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_DEBUG=1
-# default CONFIG_CPU_OPT="-g"
-
-### End Options.lb
-end
diff --git a/src/mainboard/iwill/dk8_htx/Config.lb b/src/mainboard/iwill/dk8_htx/Config.lb
deleted file mode 100644
index c501918..0000000
--- a/src/mainboard/iwill/dk8_htx/Config.lb
+++ /dev/null
@@ -1,337 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE 
-	object mptable.o 
-end
-
-if CONFIG_GENERATE_PIRQ_TABLE 
-	object irq_tables.o 
-end
-
-#if CONFIG_GENERATE_ACPI_TABLES
-#       object acpi_tables.o
-#       object fadt.o
-#       if CONFIG_SB_HT_CHAIN_ON_BUS0
-#               object dsdt_bus0.o
-#       else
-#               object dsdt.o
-#       end
-#       object ssdt.o
-#       if CONFIG_ACPI_SSDTX_NUM
-#                if CONFIG_SB_HT_CHAIN_ON_BUS0
-#                 object ssdt2_bus0.o
-#                else
-#                 object ssdt2.o
-#                end
-#       end
-#end
-
-if CONFIG_GENERATE_ACPI_TABLES
-        object acpi_tables.o
-        object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "mv dsdt_lb.hex dsdt.c"
-	end
-        object ./dsdt.o
-
-	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
-	
-        if CONFIG_ACPI_SSDTX_NUM
-            makerule ssdt2.c
-                        depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
-                        action  "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
-                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
-                        action  "mv pci2.hex ssdt2.c"
-            end
-            object ./ssdt2.o
-            makerule ssdt3.c
-                        depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
-                        action  "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
-                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
-                        action  "mv pci3.hex ssdt3.c"
-            end
-            object ./ssdt3.o
-            makerule ssdt4.c
-                        depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
-                        action  "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
-                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
-                        action  "mv pci4.hex ssdt4.c"
-            end
-            object ./ssdt4.o
-            makerule ssdt5.c
-                        depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
-                        action  "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
-                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
-                        action  "mv pci5.hex ssdt5.c"
-            end
-            object ./ssdt5.o
-        end
-end
-
-	if CONFIG_USE_INIT
-		# compile cache_as_ram.c to auto.o
-		makerule ./cache_as_ram_auto.o
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else   
-		#compile cache_as_ram.c to auto.inc 
-		makerule ./cache_as_ram_auto.inc
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-	makerule ./apc_auto.o
-		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-	end
-	ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-dir /southbridge/amd/amd8132
-
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.0 on #  northbridge 
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 off #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	        			device pnp 2e.6 off #  CIR
-								io 0x60 = 0x100
-							end
-                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end						
-							device pnp 2e.8 on #  GPIO2
-								io 0x07 = 0x08ff
-								io 0x30 = 0x01ff
-								io 0x2b = 0xd0ff
-								io 0xf0 = 0xef16
-							end
-                	        			device pnp 2e.9 off end #  GPIO3
-                	        			device pnp 2e.a off end #  ACPI
-                	        			device pnp 2e.b on #  HW Monitor
- 					 			io 0x60 = 0x290
-								irq 0x70 = 5
-                					end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end
-						chip drivers/generic/generic #dimm 1-0-0
-							device i2c 54 on end
-						end
-						chip drivers/generic/generic #dimm 1-0-1
-							device i2c 55 on end
-						end
-						chip drivers/generic/generic #dimm 1-1-0
-							device i2c 56 on end
-						end
-						chip drivers/generic/generic #dimm 1-1-1
-							device i2c 57 on end
-						end
-					end # acpi
-					device pci 1.5 off end
-					device pci 1.6 off end
-                	                register "ide0_enable" = "1"
-                	                register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0
-
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-
-	end #pci_domain
-#        chip drivers/generic/debug
-#        	device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 off end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#                device pnp 0.7 off end # tsc
-#       end
-
-end
-
-
diff --git a/src/mainboard/iwill/dk8_htx/Options.lb b/src/mainboard/iwill/dk8_htx/Options.lb
deleted file mode 100644
index f35afb4..0000000
--- a/src/mainboard/iwill/dk8_htx/Options.lb
+++ /dev/null
@@ -1,326 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-#FALLBACK: 256K-8K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#FAILOVER: 8K
-default CONFIG_FAILOVER_SIZE=0x02000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-## extra SSDT num
-default CONFIG_ACPI_SSDTX_NUM=3
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0xa
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc4000
-default CONFIG_DCACHE_RAM_SIZE=0x0c000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-##
-## for rev F training on AP purpose
-##
-#default CONFIG_AP_CODE_IN_CAR=1
-#default CONFIG_MEM_TRAIN_SEQ=1
-#default CONFIG_WAIT_BEFORE_CPUS_INIT=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="dk8_htx"
-default CONFIG_MAINBOARD_VENDOR="IWILL"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/iwill/dk8s2/Config.lb b/src/mainboard/iwill/dk8s2/Config.lb
deleted file mode 100644
index a5fee1b..0000000
--- a/src/mainboard/iwill/dk8s2/Config.lb
+++ /dev/null
@@ -1,196 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-## ATI Rage XL framebuffering graphics driver
-dir /drivers/ati/ragexl
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# config for iwill/dk8s2
-chip northbridge/amd/amdk8/root_complex
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on # LDT 0
-				chip southbridge/amd/amd8131
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 on end
-						device pci 1.0 off end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp  2e.0 on      # Floppy
-								 io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp  2e.1 off     # Parallel Port
-								 io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp  2e.2 on      # Com1
-								 io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp  2e.3 off     # Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp  2e.5 on      # Keyboard
-								 io 0x60 = 0x60
-								 io 0x62 = 0x64
-							       irq 0x70 = 1
-								irq 0x72 = 12
-							end
-							device pnp  2e.6 off end # CIR
-							device pnp  2e.7 off end # GAME_MIDI_GIPO1
-							device pnp  2e.8 off end # GPIO2
-							device pnp  2e.9 off end # GPIO3
-							device pnp  2e.a off end # ACPI
-							device pnp  2e.b on      # HW Monitor
-								 io 0x60 = 0x290
-							end
-							register "com1" = "{1}"
-						#	register "com1" = "{1, 0, 0x3f8, 4}"
-						#	register "lpt" = "{1}"
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on end
-					device pci 1.5 off end
-					device pci 1.6 off end
-				end
-			end # LDT0
-			device pci 18.0 on end # LDT1
-			device pci 18.0 on end # LDT2
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-		chip northbridge/amd/amdk8
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-		end
-	end
-	device apic_cluster 0 on
-		chip cpu/amd/socket_940
-			device apic 0 on end
-		end
-		chip cpu/amd/socket_940
-			device apic 1 on end
-		end
-	end
-end
-
diff --git a/src/mainboard/iwill/dk8s2/Options.lb b/src/mainboard/iwill/dk8s2/Options.lb
deleted file mode 100644
index 911a54b..0000000
--- a/src/mainboard/iwill/dk8s2/Options.lb
+++ /dev/null
@@ -1,228 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE=524288
-
-###
-### Build options
-###
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=12
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
- 
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="HDAMA"
-default CONFIG_MAINBOARD_VENDOR="ARIMA"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
-
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-#default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-#default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/iwill/dk8x/Config.lb b/src/mainboard/iwill/dk8x/Config.lb
deleted file mode 100644
index 478074e..0000000
--- a/src/mainboard/iwill/dk8x/Config.lb
+++ /dev/null
@@ -1,171 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  northbridge 
-				#  devices on link 0, link 0 == LDT 0 
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 on end
-						device pci 1.0 off end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627thf
-							device pnp 2e.0 on end
-							device pnp 2e.1 on end
-							device pnp 2e.2 on end
-							device pnp 2e.3 on end
-							device pnp 2e.4 on end
-							device pnp 2e.5 on end
-							device pnp 2e.6 on end
-							device pnp 2e.7 on end 
-							device pnp 2e.8 on end 
-							device pnp 2e.9 on end 
-							device pnp 2e.a on end 
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on end 
-					device pci 1.5 off end
-					device pci 1.6 off end
-				end
-			end # LDT0
-			device pci 18.0 on end # LDT1
-			device pci 18.0 on end # LDT2
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-		chip northbridge/amd/amdk8
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-		end
-	end 
-	device apic_cluster 0 on
-		chip cpu/amd/socket_940
-			device apic 0 on end
-		end
-		chip cpu/amd/socket_940
-			device apic 1 on end
-		end
-	end
-end
-
diff --git a/src/mainboard/iwill/dk8x/Options.lb b/src/mainboard/iwill/dk8x/Options.lb
deleted file mode 100644
index 5cc8161..0000000
--- a/src/mainboard/iwill/dk8x/Options.lb
+++ /dev/null
@@ -1,227 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE=524288
-
-###
-### Build options
-###
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
- 
-##
-## Clean up the motherboard id strings
-##
-#default CONFIG_MAINBOARD_PART_NUMBER="HDAMA"
-#default CONFIG_MAINBOARD_VENDOR="ARIMA"
-#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-#default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-#default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/jetway/j7f24/Config.lb b/src/mainboard/jetway/j7f24/Config.lb
deleted file mode 100644
index 8e0b498..0000000
--- a/src/mainboard/jetway/j7f24/Config.lb
+++ /dev/null
@@ -1,136 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object dsdt.o
-	object acpi_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-chip northbridge/via/cn700			# Northbridge
-  device pci_domain 0 on			# PCI domain
-    device pci 0.0 on end			# AGP Bridge
-    device pci 0.1 on end			# Error Reporting
-    device pci 0.2 on end			# Host Bus Control
-    device pci 0.3 on end			# Memory Controller
-    device pci 0.4 on end			# Power Management
-    device pci 0.7 on end			# V-Link Controller
-    device pci 1.0 on end			# PCI Bridge
-    chip southbridge/via/vt8237r		# Southbridge
-      # Enable both IDE channels.
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      # Both cables are 40pin.
-      register "ide0_80pin_cable" = "0"
-      register "ide1_80pin_cable" = "0"
-      register "fn_ctrl_lo" = "0x80"
-      register "fn_ctrl_hi" = "0x1d"
-      device pci a.0 on end			# Firewire
-      device pci f.0 on end			# SATA
-      device pci f.1 on end			# IDE
-      device pci 10.0 on end			# OHCI
-      device pci 10.1 on end			# OHCI
-      device pci 10.2 on end			# OHCI
-      device pci 10.3 on end			# OHCI
-      device pci 10.4 on end			# EHCI
-      device pci 11.0 on			# Southbridge LPC
-        chip superio/fintek/f71805f		# Super I/O
-          device pnp 2e.0 off			# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on			# Parallel Port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 2e.2 on			# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.3 on			# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.b on			# HWM
-            io 0x60 = 0xec00
-          end
-        end
-      end
-      device pci 11.5 on end			# AC'97 audio
-      # device pci 11.6 off end			# AC'97 Modem
-      device pci 12.0 on end			# Ethernet
-    end
-  end
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/via/model_c7			# VIA C7
-      device apic 0 on end			# APIC
-    end
-  end
-end
diff --git a/src/mainboard/jetway/j7f24/Options.lb b/src/mainboard/jetway/j7f24/Options.lb
deleted file mode 100644
index e65706d..0000000
--- a/src/mainboard/jetway/j7f24/Options.lb
+++ /dev/null
@@ -1,96 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_VIDEO_MB
-uses CONFIG_IOAPIC
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_IOAPIC = 1
-default CONFIG_VIDEO_MB = 32
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 10
-default CONFIG_GENERATE_ACPI_TABLES = 0
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_USE_FALLBACK_IMAGE = 1
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-#default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default HOSTCC = "gcc"
-
-end
diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb
deleted file mode 100644
index 66ada57..0000000
--- a/src/mainboard/kontron/986lcd-m/Config.lb
+++ /dev/null
@@ -1,270 +0,0 @@
-##
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-## 
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Image size calculation
-##
-
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-driver rtl8168.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object acpi_tables.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dsdt.asl"
-		action  "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD)  $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl"
-		action  "iasl -p dsdt -tc $(CURDIR)/dsdt.asl"
-		action  "mv $(CURDIR)/dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
-	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-else
-
-makerule ./auto.inc
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
-	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
-	action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-	action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-if CONFIG_USE_INIT
-	ldscript /cpu/x86/32bit/entry32.lds
-	ldscript /cpu/x86/car/cache_as_ram.lds
-end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-        mainboardinit cpu/x86/16bit/reset16.inc
-        ldscript /cpu/x86/16bit/reset16.lds
-else
-        mainboardinit cpu/x86/32bit/reset32.inc
-        ldscript /cpu/x86/32bit/reset32.lds
-end
-
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i945
-
-        device apic_cluster 0 on
-                chip cpu/intel/socket_mFCPGA478
-                        device apic 0 on end
-                end
-        end
-
-        device pci_domain 0 on 
-                device pci 00.0 on end # host bridge
-		# autodetect 0:1.0 because it might or might not be there.
-		# device pci 01.0 off end # i945 PCIe root port
-		device pci 02.0 on end # vga controller
-		device pci 02.1 on end # display controller
-
-                chip southbridge/intel/i82801gx
-			register "pirqa_routing" = "0x05"
-			register "pirqb_routing" = "0x07"
-			register "pirqc_routing" = "0x05"
-			register "pirqd_routing" = "0x07"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x06"
-
-			# GPI routing
-			#  0 No effect (default)
-			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
-			#  2 SCI (if corresponding GPIO_EN bit is also set)
-			register "gpi13_routing" = "1"
-			register "gpe0_en" = "0x00000400"
-
-                        register "ide_legacy_combined" = "0x1"
-                        register "ide_enable_primary" = "0x1"
-                        register "ide_enable_secondary" = "0x1"
-                        register "sata_ahci" = "0x0"
-
-                	device pci 1b.0 on end # High Definition Audio
-                	device pci 1c.0 on end # PCIe
-                	device pci 1c.1 on end # PCIe
-                	device pci 1c.2 on end # PCIe
-			#device pci 1c.3 off end # PCIe port 4
-			#device pci 1c.4 off end # PCIe port 5
-			#device pci 1c.5 off end # PCIe port 6
-                	device pci 1d.0 on end # USB UHCI
-                	device pci 1d.1 on end # USB UHCI
-                	device pci 1d.2 on end # USB UHCI
-                	device pci 1d.3 on end # USB UHCI
-                	device pci 1d.7 on end # USB2 EHCI
-                	device pci 1e.0 on end # PCI bridge
-			#device pci 1e.2 off end # AC'97 Audio 
-			#device pci 1e.3 off end # AC'97 Modem
-                        device pci 1f.0 on # LPC bridge
-                                chip superio/winbond/w83627thg
-					device pnp 2e.0 off		# Floppy
-					end
-					device pnp 2e.1 off		# Parport
-					end
-                                        device pnp 2e.2 on
-                                                 io 0x60 = 0x3f8
-                                                irq 0x70 = 4
-                                        end
-                                        device pnp 2e.3 on
-                                                 io 0x60 = 0x2f8
-                                                irq 0x70 = 3
-						irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
-                                        end
-					device pnp 2e.5 on		# Keyboard+Mouse
-						 io 0x60 = 0x60
-						 io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-						irq 0xf0 = 0x82		# HW accel A20.
-					end
-					device pnp 2e.7 on		# GPIO1, GAME, MIDI
-						 io 0x62 = 0x330
-						irq 0x70 = 9
-					end
-					device pnp 2e.8 on		# GPIO2
-						# all default
-					end
-					device pnp 2e.9 on		# GPIO3/4
-						irq 0x30 = 0x03		# does this work?
-						irq 0xf0 = 0xfb		# set inputs/outputs
-						irq 0xf1 = 0x66
-					end
-					device pnp 2e.a off		# ACPI
-					end
-					device pnp 2e.b on		# HWM
-						 io 0x60 = 0xa00
-						irq 0x70 = 0
-					end
-
-                                end
-                                chip superio/winbond/w83627thg
-                                        device pnp 4e.0 off		# Floppy
-					end
-					device pnp 4e.1 off		# Parport
-					end
-                                        device pnp 4e.2 on		# COM3
-                                                 io 0x60 = 0x3e8
-                                                irq 0x70 = 11
-                                        end
-                                        device pnp 4e.3 on		# COM4
-                                                 io 0x60 = 0x2e8
-                                                irq 0x70 = 10
-                                        end
-					device pnp 4e.5 off		# Keyboard
-					end
-					device pnp 4e.7 off		# GPIO1, GAME, MIDI
-					end
-					device pnp 4e.8 off		# GPIO2
-					end
-					device pnp 4e.9 off		# GPIO3/4
-					end
-					device pnp 4e.a off		# ACPI
-					end
-					device pnp 4e.b off		# HWM
-					end
-                                end
-
-                        end
-			#device pci 1f.1 off end # IDE
-                        device pci 1f.2 on end  # SATA
-                        device pci 1f.3 on end  # SMBus
-			#device pci 1f.4 off end # Realtek ID Codec
-                end
-        end
-end
diff --git a/src/mainboard/kontron/986lcd-m/Options.lb b/src/mainboard/kontron/986lcd-m/Options.lb
deleted file mode 100644
index 811d8ef..0000000
--- a/src/mainboard/kontron/986lcd-m/Options.lb
+++ /dev/null
@@ -1,328 +0,0 @@
-##
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-# Tables
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-# SMP
-uses CONFIG_SMP
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_AP_IN_SIPI_WAIT
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-# Image Size
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-# Payload
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-# Build Internals
-uses CONFIG_RAMBASE
-uses CONFIG_ROMBASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_SMI_HANDLER
-uses CONFIG_PCIE_CONFIGSPACE_HOLE
-uses CONFIG_MMCONF_SUPPORT
-uses CONFIG_MMCONF_BASE_ADDRESS
-uses CONFIG_GFXUMA
-
-#
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-# Timers
-uses CONFIG_UDELAY_LAPIC
-# Console
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_VGA_ROM_RUN
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_DEBUG
-# Toolchain
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-# Tweaks
-uses CONFIG_GDB_STUB
-uses CONFIG_MAX_REBOOT_CNT
-uses CONFIG_USE_WATCHDOG_ON_BOOT
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-
-###
-### Build options
-###
-
-##
-##
-default CONFIG_MAX_REBOOT_CNT=3
-
-##
-## Use the watchdog to break out of a lockup condition
-##
-default CONFIG_USE_WATCHDOG_ON_BOOT=0
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1024*1024
-
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## 
-default CONFIG_UDELAY_LAPIC=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build SMI handler
-##
-default CONFIG_HAVE_SMI_HANDLER=1
-
-##
-## Leave a hole for mmapped PCIe config space
-##
-
-default CONFIG_PCIE_CONFIGSPACE_HOLE=1
-default CONFIG_MMCONF_SUPPORT=1
-default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
-
-##
-## UMA
-##
-default CONFIG_GFXUMA=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=18
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to provide ACPI support
-##
-default CONFIG_GENERATE_ACPI_TABLES=1
-default CONFIG_HAVE_MAINBOARD_RESOURCES=1
-default CONFIG_HAVE_ACPI_RESUME=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-# There are some network option roms that don't work with
-# coreboot's x86emu. Thus, we only execute the VGA option rom
-# for now:
-default CONFIG_VGA_ROM_RUN=1
-default CONFIG_PCI_ROM_RUN=0
-default CONFIG_DEBUG=0
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-default CONFIG_AP_IN_SIPI_WAIT=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024)
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Execute In Place settings
-##
-
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="986LCD-M"
-default CONFIG_MAINBOARD_VENDOR=     "KONTRON"
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 0x10000
-
-##
-## Use a small 32K stack
-##
-default CONFIG_STACK_SIZE=0x8000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/kontron/kt690/Config.lb b/src/mainboard/kontron/kt690/Config.lb
deleted file mode 100644
index 3cddb51..0000000
--- a/src/mainboard/kontron/kt690/Config.lb
+++ /dev/null
@@ -1,262 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE
-	object get_bus_conf.o
-	object irq_tables.o
-end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object acpi_tables.o
-	object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-	if CONFIG_USE_INIT
-
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else
-
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript      /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-#The variables belong to mainboard are defined here.
-
-#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-#					   1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_S1G1
-		device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  southbridge
-				chip southbridge/amd/rs690
-					device pci 0.0 on end # HT  	0x7910
-					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						device pci 5.0 on end	# Internal Graphics 0x791F
-					end
-					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
-					device pci 3.0 off end # PCIE P2P bridge	0x791b
-					device pci 4.0 on end # PCIE P2P bridge 0x7914
-					device pci 5.0 on end # PCIE P2P bridge 0x7915
-					device pci 6.0 on end # PCIE P2P bridge 0x7916
-					device pci 7.0 on end # PCIE P2P bridge 0x7917
-					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "gpp_configuration" = "4"
-					register "port_enable" = "0xfc"
-					register "gfx_dev2_dev3" = "1"
-					register "gfx_dual_slot" = "0"
-					register "gfx_lane_reversal" = "0"
-					register "gfx_tmds" = "0"
-					register "gfx_compliance" = "0"
-					register "gfx_reconfiguration" = "1"
-					register "gfx_link_width" = "0"
-				end
-				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
-					device pci 12.0 on end # SATA  0x4380
-					device pci 13.0 on end # USB   0x4387
-					device pci 13.1 on end # USB   0x4388
-					device pci 13.2 on end # USB   0x4389
-					device pci 13.3 on end # USB   0x438a
-					device pci 13.4 on end # USB   0x438b
-					device pci 13.5 on end # USB 2 0x4386
-	 				device pci 14.0 on # SM        0x4385
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end
-					end # SM
-					device pci 14.1 on end # IDE    0x438c
-					device pci 14.2 on end # HDA    0x4383
-					device pci 14.3 on # LPC	0x438d
-						chip superio/winbond/w83627dhg
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 on #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							#device pnp 2e.6 off #  SPI
-							#end
-							device pnp 2e.7 off #  GPIO
-							end
-							device pnp 2e.8 on #  WDTO#, PLED
-							end
-							device pnp 2e.9 off #  GPIO
-							end
-							device pnp 2e.a off #  ACPI
-							end
-							device pnp 2e.b on # HWM
-								io 0x60 = 0xa10
-							end
-							device pnp 2e.c off # PECI, SST
-							end
-						end	#superio/winbond/w83627dhg
-						#chip superio/smsc/fdc37n972
-						# seems this chip is not used?
-						#end
-					end		#LPC
-					device pci 14.4 on end # PCI 0x4384
-					device pci 14.5 on end # ACI 0x4382
-					device pci 14.6 on end # MCI 0x438e
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "hda_viddid" = "0x10ec0888"
-				end	#southbridge/amd/sb600
-			end #  device pci 18.0
-
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end		#northbridge/amd/amdk8
-	end #pci_domain
-end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/kontron/kt690/Options.lb b/src/mainboard/kontron/kt690/Options.lb
deleted file mode 100644
index 6e3ad13..0000000
--- a/src/mainboard/kontron/kt690/Options.lb
+++ /dev/null
@@ -1,301 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-## Copyright (C) 2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_VIDEO_MB
-uses CONFIG_GFXUMA
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#256K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-# BTDC: Only one HT device on Herring.
-#HT Unit ID offset
-#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-
-#real SB Unit ID
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
-
-#make the SB HT chain on bus 0
-default CONFIG_SB_HT_CHAIN_ON_BUS0=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="KT690"
-default CONFIG_MAINBOARD_VENDOR="KONTRON"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1488
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6900
-
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 32K stack
-##
-default CONFIG_STACK_SIZE=0x8000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_VIDEO_MB=1
-default CONFIG_GFXUMA=1
-default CONFIG_HAVE_MAINBOARD_RESOURCES=1
-
-end
diff --git a/src/mainboard/lippert/frontrunner/Config.lb b/src/mainboard/lippert/frontrunner/Config.lb
deleted file mode 100644
index 06147ed..0000000
--- a/src/mainboard/lippert/frontrunner/Config.lb
+++ /dev/null
@@ -1,112 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx2
-  device pci_domain 0 on 
-    device pci 0.0 on end
-      chip southbridge/amd/cs5535
-        device pci 12.0 on
-        device pci 12.1 off end		# SMI
-        device pci 12.2 on  end		# IDE
-        device pci 12.3 off end 	# Audio
-        device pci 12.4 off end		# VGA
-      end
-    end
-  end
-
-  chip cpu/amd/model_gx2
-  end
-
-end
-
diff --git a/src/mainboard/lippert/frontrunner/Options.lb b/src/mainboard/lippert/frontrunner/Options.lb
deleted file mode 100644
index e6a9b48..0000000
--- a/src/mainboard/lippert/frontrunner/Options.lb
+++ /dev/null
@@ -1,159 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=2
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/lippert/roadrunner-lx/Config.lb b/src/mainboard/lippert/roadrunner-lx/Config.lb
deleted file mode 100644
index ed6d61e..0000000
--- a/src/mainboard/lippert/roadrunner-lx/Config.lb
+++ /dev/null
@@ -1,198 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-	# compile cache_as_ram.c to auto.inc
-	makerule ./cache_as_ram_auto.inc
-		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		action "perl -e 's/.rodata/.rom.data/g' -pi $@"
-		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-#	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-
-##
-## Include the secondary configuration files
-##
-dir /pc80
-config chip.h
-
-# Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED.
-register "sio_gp1x_config" = "0x20"
-
-chip northbridge/amd/lx
-  device pci_domain 0 on
-    device pci 1.0 on end		# Northbridge
-    device pci 1.1 on end		# Graphics
-    device pci 1.2 on end		# AES
-    chip southbridge/amd/cs5536		# Southbridge
-      # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
-      # SIRQ Mode = Active(Quiet) mode. Save power...
-      # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
-      # UARTs, etc IRQs. OK
-      register "lpc_serirq_enable"        = "0x000012DA"  # 00010010 11011010
-      register "lpc_serirq_polarity"      = "0x0000ED25"  # inverse of above
-      register "lpc_serirq_mode"          = "1"
-      register "enable_gpio_int_route"    = "0x0D0C0700"
-      register "enable_ide_nand_flash"    = "0"  # 0:ide mode, 1:flash
-      register "enable_USBP4_device"      = "0"  # 0: host, 1:device
-      register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-      register "com1_enable"              = "0"
-      register "com1_address"             = "0x3E8"
-      register "com1_irq"                 = "6"
-      register "com2_enable"              = "0"
-      register "com2_address"             = "0x2E8"
-      register "com2_irq"                 = "6"
-      register "unwanted_vpci[0]"         = "0"  # End of list has a zero
-      device pci 8.0 on end		# Slot4
-      device pci 9.0 on end		# Slot3
-      device pci a.0 on end		# Slot2
-      device pci b.0 on end		# Slot1
-      device pci c.0 on end		# IT8888
-      device pci e.0 on end		# Ethernet
-      device pci f.0 on			# ISA bridge
-        chip superio/ite/it8712f
-          device pnp 2e.0 off		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on		# Com1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.2 on		# Com2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.4 on		# EC
-            io 0x60 = 0x290
-            io 0x62 = 0x230
-            irq 0x70 = 9
-          end
-          device pnp 2e.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.6 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.7 on		# GPIO
-            io 0x62 = 0x1220
-            # io 0x64 = 0x1200
-          end
-          device pnp 2e.8 off		# MIDI
-            io 0x60 = 0x300
-            irq 0x70 = 9
-          end
-          device pnp 2e.9 off		# Game port
-            io 0x60 = 0x220
-          end
-          device pnp 2e.a off end	# CIR
-        end
-      end
-      device pci f.2 on end		# IDE controller
-      device pci f.3 on end		# Audio
-      device pci f.4 on end		# OHCI
-      device pci f.5 on end		# EHCI
-    end
-  end
-  # APIC cluster is late CPU init.
-  device apic_cluster 0 on
-    chip cpu/amd/model_lx
-      device apic 0 on end
-    end
-  end
-end
diff --git a/src/mainboard/lippert/roadrunner-lx/Options.lb b/src/mainboard/lippert/roadrunner-lx/Options.lb
deleted file mode 100644
index b9ca9db..0000000
--- a/src/mainboard/lippert/roadrunner-lx/Options.lb
+++ /dev/null
@@ -1,206 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## Based on Options.lb from AMD's DB800 mainboard.
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESS
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEBUG
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE = 512 * 1024
-
-###
-### Build options
-###
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_VIDEO_MB = 8
-default CONFIG_PCI_ROM_RUN = 0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE = 0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET = 0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7
-default CONFIG_PIRQ_ROUTE = 1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE = 0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xc8000
-default CONFIG_DCACHE_RAM_SIZE = 0x08000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE = 8 * 1024
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE = 16 * 1024
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250 = 1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD = 115200
-#default CONFIG_TTYS0_BAUD = 57600
-#default CONFIG_TTYS0_BAUD = 38400
-#default CONFIG_TTYS0_BAUD = 19200
-#default CONFIG_TTYS0_BAUD = 9600
-#default CONFIG_TTYS0_BAUD = 4800
-#default CONFIG_TTYS0_BAUD = 2400
-#default CONFIG_TTYS0_BAUD = 1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE = 0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS = 0x3
-
-# Compile extra debugging code
-default CONFIG_DEBUG = 1
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
-
-end
diff --git a/src/mainboard/lippert/spacerunner-lx/Config.lb b/src/mainboard/lippert/spacerunner-lx/Config.lb
deleted file mode 100644
index 8d2052b..0000000
--- a/src/mainboard/lippert/spacerunner-lx/Config.lb
+++ /dev/null
@@ -1,199 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-	# compile cache_as_ram.c to auto.inc
-	makerule ./cache_as_ram_auto.inc
-		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an ID string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup.
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-#	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-
-##
-## Include the secondary configuration files
-##
-dir /pc80
-config chip.h
-
-# See also SMC_CONFIG in cache_as_ram_auto.c.
-# Bit0 turns off Live LED, bit1 switches Com1 to RS485, bit2 same for Com2.
-register "sio_gp1x_config" = "0x01"
-
-chip northbridge/amd/lx
-  device pci_domain 0 on
-    device pci 1.0 on end				# Northbridge
-    device pci 1.1 on end				# Graphics
-    device pci 1.2 on end				# AES
-    chip southbridge/amd/cs5536
-      # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
-      # SIRQ Mode = Active(Quiet) mode. Save power....
-      # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
-      # UARTs, etc IRQs. OK
-      register "lpc_serirq_enable"        = "0x000012DA" # 00010010 11011010
-      register "lpc_serirq_polarity"      = "0x0000ED25" # inverse of above
-      register "lpc_serirq_mode"          = "1"
-      register "enable_gpio_int_route"    = "0x0D0C0700"
-      register "enable_ide_nand_flash"    = "0" # 0:ide mode, 1:flash
-      register "enable_USBP4_device"      = "0" # 0:host, 1:device
-      register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-      register "com1_enable"              = "0"
-      register "com1_address"             = "0x3E8"
-      register "com1_irq"                 = "6"
-      register "com2_enable"              = "0"
-      register "com2_address"             = "0x2E8"
-      register "com2_irq"                 = "6"
-      register "unwanted_vpci[0]"         = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8
-      register "unwanted_vpci[1]"         = "0" # End of list has a zero
-      device pci 8.0 on end		# Slot4
-      device pci 9.0 on end		# Slot3
-      device pci a.0 on end		# Slot2
-      device pci b.0 on end		# Slot1
-      device pci c.0 on end		# IT8888
-      device pci e.0 on end		# Ethernet
-      device pci f.0 on			# ISA Bridge
-        chip superio/ite/it8712f
-          device pnp 2e.0 off		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on		# Com1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.2 on		# Com2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.4 on		# EC
-            io 0x60 = 0x290
-            io 0x62 = 0x230
-            irq 0x70 = 9
-          end
-          device pnp 2e.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.6 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.7 on		# GPIO
-            io 0x62 = 0x1220
-            io 0x64 = 0x1200
-          end
-          device pnp 2e.8 off		# MIDI
-            io 0x60 = 0x300
-            irq 0x70 = 9
-          end
-          device pnp 2e.9 off		# Game port
-            io 0x60 = 0x220
-          end
-          device pnp 2e.a off end	# CIR
-        end
-      end
-      device pci f.2 on end		# IDE
-      device pci f.3 off end		# Audio
-      device pci f.4 on end		# OHCI
-      device pci f.5 on end		# EHCI
-    end
-  end
-  # APIC cluster is late CPU init.
-  device apic_cluster 0 on
-    chip cpu/amd/model_lx
-      device apic 0 on end
-    end
-  end
-end
diff --git a/src/mainboard/lippert/spacerunner-lx/Options.lb b/src/mainboard/lippert/spacerunner-lx/Options.lb
deleted file mode 100644
index 5bb104b..0000000
--- a/src/mainboard/lippert/spacerunner-lx/Options.lb
+++ /dev/null
@@ -1,206 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## Based on Options.lb from AMD's DB800 mainboard.
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESS
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEBUG
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE = 512*1024
-
-###
-### Build options
-###
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_VIDEO_MB = 8
-default CONFIG_PCI_ROM_RUN = 0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE = 0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET = 0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7
-default CONFIG_PIRQ_ROUTE = 1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE = 0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xc8000
-default CONFIG_DCACHE_RAM_SIZE = 0x08000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE = 0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE = 0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250 = 1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD = 115200
-#default CONFIG_TTYS0_BAUD = 57600
-#default CONFIG_TTYS0_BAUD = 38400
-#default CONFIG_TTYS0_BAUD = 19200
-#default CONFIG_TTYS0_BAUD = 9600
-#default CONFIG_TTYS0_BAUD = 4800
-#default CONFIG_TTYS0_BAUD = 2400
-#default CONFIG_TTYS0_BAUD = 1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE = 0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS = 0x3
-
-# Compile extra debugging code
-default CONFIG_DEBUG = 1
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
-
-end
diff --git a/src/mainboard/mitac/6513wu/Config.lb b/src/mainboard/mitac/6513wu/Config.lb
deleted file mode 100644
index a6480bd..0000000
--- a/src/mainboard/mitac/6513wu/Config.lb
+++ /dev/null
@@ -1,138 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
-	action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
-	action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i82810           # Northbridge
-  device apic_cluster 0 on              # APIC cluster
-    chip cpu/intel/socket_PGA370        # CPU
-      device apic 0 on end              # APIC
-    end
-  end
-  device pci_domain 0 on                # PCI domain
-    device pci 0.0 on end               # Graphics Memory Controller Hub (GMCH)
-    device pci 1.0 on end
-    chip southbridge/intel/i82801xx     # Southbridge
-      register "pirqa_routing" = "0x03"
-      register "pirqb_routing" = "0x05"
-      register "pirqc_routing" = "0x09"
-      register "pirqd_routing" = "0x0b"
-
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-
-      device pci 1e.0 on                # PCI bridge
-        device pci 5.0 on end           # Audio controller (ESS ES1988)
-      end
-      device pci 1f.0 on                # ISA bridge
-        chip superio/smsc/smscsuperio   # Super I/O (SMSC LPC47U332)
-          device pnp 4e.0 on            # Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 4e.3 on            # Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 4e.4 on            # COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 4e.5 on            # MIDI port (MPU-401)
-            io 0x60 = 0x330
-            irq 0x70 = 10
-          end
-          device pnp 4e.7 on            # PS/2 keyboard / mouse
-            io 0x60 = 0x60              # XXX: not relocatable
-            io 0x62 = 0x64              # XXX: not relocatable
-            irq 0x70 = 1                # PS/2 keyboard interrupt
-            irq 0x72 = 12               # PS/2 mouse interrupt
-          end
-          device pnp 4e.9 on            # Game port
-            io 0x60 = 0x201
-          end
-          device pnp 4e.a on            # Runtime registers
-            io 0x60 = 0x400
-          end
-          device pnp 4e.b off end       # SMBus
-        end
-      end
-      device pci 1f.1 on end            # IDE
-      device pci 1f.2 on end            # USB
-      device pci 1f.3 on end            # SMbus
-      device pci 1f.5 off end           # Audio controller
-      device pci 1f.6 off end           # Modem
-    end
-  end
-end
diff --git a/src/mainboard/mitac/6513wu/Options.lb b/src/mainboard/mitac/6513wu/Options.lb
deleted file mode 100644
index 0dac44b..0000000
--- a/src/mainboard/mitac/6513wu/Options.lb
+++ /dev/null
@@ -1,108 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CC
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_OBJCOPY
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_RAMBASE
-uses CONFIG_ROMBASE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_VIDEO_MB
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_XIP_ROM_SIZE
-uses COREBOOT_EXTRA_VERSION
-uses HOSTCC
-
-# Motherboard info, tables, etc.
-default CONFIG_MAINBOARD_VENDOR = "Mitac"
-default CONFIG_MAINBOARD_PART_NUMBER = "6513WU"
-default CONFIG_IRQ_SLOT_COUNT = 8
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_USE_OPTION_TABLE = 0
-
-# ROM layout
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_ROM_PAYLOAD = 1
-
-# RAM layout
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-
-# Misc. settings
-default CONFIG_USE_INIT = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-
-# Compiler setup
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-
-# Console settings
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3     # 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 7  # No debugging/spew
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-# Enable onboard video
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-default CONFIG_VIDEO_MB = 1
-
-end
diff --git a/src/mainboard/msi/ms6119/Config.lb b/src/mainboard/msi/ms6119/Config.lb
deleted file mode 100644
index 79bc904..0000000
--- a/src/mainboard/msi/ms6119/Config.lb
+++ /dev/null
@@ -1,133 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.9 on		# GPIO 3
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/msi/ms6119/Options.lb b/src/mainboard/msi/ms6119/Options.lb
deleted file mode 100644
index 7930819..0000000
--- a/src/mainboard/msi/ms6119/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/msi/ms6147/Config.lb b/src/mainboard/msi/ms6147/Config.lb
deleted file mode 100644
index 73f79cb..0000000
--- a/src/mainboard/msi/ms6147/Config.lb
+++ /dev/null
@@ -1,141 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Mats Erik Andersson <mats.andersson@gisladisker.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.9 off		# GPIO 3
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 7.1 on end		# IDE
-      device pci 7.2 on end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "1"
-      register "ide0_drive1_udma33_enable" = "1"
-      register "ide1_drive0_udma33_enable" = "1"
-      register "ide1_drive1_udma33_enable" = "1"
-    end
-  end
-end
diff --git a/src/mainboard/msi/ms6147/Options.lb b/src/mainboard/msi/ms6147/Options.lb
deleted file mode 100644
index e6ccb87..0000000
--- a/src/mainboard/msi/ms6147/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Mats Erik Andersson <mats.andersson@gisladisker.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 8		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/msi/ms6156/Config.lb b/src/mainboard/msi/ms6156/Config.lb
deleted file mode 100644
index 0a93cc7..0000000
--- a/src/mainboard/msi/ms6156/Config.lb
+++ /dev/null
@@ -1,134 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 off		# GPIO 1
-          end
-          device pnp 3f0.8 off		# GPIO 2
-          end
-          device pnp 3f0.9 off		# GPIO 3
-          end
-          device pnp 3f0.a off		# ACPI
-          end
-        end
-      end
-      device pci 7.1 on end		# IDE
-      device pci 7.2 on end		# USB
-      device pci 7.3 on end		# ACPI
-      device pci 14.0 on end		# Onboard audio (Ensoniq ES1371)
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "1"
-      register "ide0_drive1_udma33_enable" = "1"
-      register "ide1_drive0_udma33_enable" = "1"
-      register "ide1_drive1_udma33_enable" = "1"
-    end
-  end
-end
diff --git a/src/mainboard/msi/ms6156/Options.lb b/src/mainboard/msi/ms6156/Options.lb
deleted file mode 100644
index 8d6de68..0000000
--- a/src/mainboard/msi/ms6156/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7
-default CONFIG_MAINBOARD_VENDOR = "MSI"
-default CONFIG_MAINBOARD_PART_NUMBER = "MS-6156"
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/msi/ms6178/Config.lb b/src/mainboard/msi/ms6178/Config.lb
deleted file mode 100644
index 3f77f30..0000000
--- a/src/mainboard/msi/ms6178/Config.lb
+++ /dev/null
@@ -1,133 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i82810			# Northbridge
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/intel/socket_PGA370		# CPU
-      device apic 0 on end			# APIC
-    end
-  end
-  device pci_domain 0 on
-    device pci 0.0 on end			# Host bridge
-    device pci 1.0 on end			# Onboard VGA
-    chip southbridge/intel/i82801xx		# Southbridge
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-
-      device pci 1e.0 on end			# PCI bridge
-      device pci 1f.0 on			# ISA/LPC bridge
-        chip superio/winbond/w83627hf		# Super I/O
-          device pnp 2e.0 on			# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on			# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 2e.2 on			# Com1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.3 on			# Com2 (only header on board)
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.5 on			# PS/2 keyboard/mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1			# Keyboard interrupt
-            irq 0x72 = 12			# Mouse interrupt
-          end
-          device pnp 2e.6 off end		# Consumer IR (TODO)
-          device pnp 2e.7 on			# Game port / MIDI / GPIO 1
-            io 0x60 = 0x201
-            io 0x62 = 0x330
-            irq 0x70 = 9
-          end
-          device pnp 2e.8 on end		# GPIO 2
-          device pnp 2e.9 on end		# GPIO 3
-          device pnp 2e.a on end		# ACPI
-          device pnp 2e.b on			# Hardware monitor
-            io 0x60 = 0x290
-            irq 0x70 = 5
-          end
-        end
-      end
-      device pci 1f.1 on end			# IDE
-      device pci 1f.2 on end			# USB
-      device pci 1f.3 on end			# SMBus
-      device pci 1f.5 on end			# AC'97 audio
-      device pci 1f.6 on end			# AC'97 modem
-    end
-  end
-end
-
diff --git a/src/mainboard/msi/ms6178/Options.lb b/src/mainboard/msi/ms6178/Options.lb
deleted file mode 100644
index 04660f0..0000000
--- a/src/mainboard/msi/ms6178/Options.lb
+++ /dev/null
@@ -1,99 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_WRITE_HIGH_TABLES
-uses CONFIG_VIDEO_MB
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 4		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-default CONFIG_WRITE_HIGH_TABLES = 1
-default CONFIG_VIDEO_MB = 1
-end
diff --git a/src/mainboard/msi/ms7135/Config.lb b/src/mainboard/msi/ms7135/Config.lb
deleted file mode 100644
index adc58a9..0000000
--- a/src/mainboard/msi/ms7135/Config.lb
+++ /dev/null
@@ -1,241 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
-## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
-## (Thanks to LSRA University of Mannheim for their support)
-## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/ati/ragexl
-
-# Needed by irq_tables and mptable and acpi_tables.
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE
-	object mptable.o
-end
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-	if CONFIG_USE_INIT
-		makerule ./auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code.
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit cpu/x86/16bit/entry16.inc
-		ldscript /cpu/x86/16bit/entry16.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit cpu/x86/16bit/entry16.inc
-		ldscript /cpu/x86/16bit/entry16.lds
-	end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (this is where coreboot is entered).
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit cpu/x86/16bit/reset16.inc
-		ldscript /cpu/x86/16bit/reset16.lds
-	else
-		mainboardinit cpu/x86/32bit/reset32.inc
-		ldscript /cpu/x86/32bit/reset32.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit cpu/x86/16bit/reset16.inc
-		ldscript /cpu/x86/16bit/reset16.lds
-	else
-		mainboardinit cpu/x86/32bit/reset32.inc
-		ldscript /cpu/x86/32bit/reset32.lds
-	end
-end
-
-##
-## Include an ID string (for safe flashing).
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for CK804
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit southbridge/nvidia/ck804/romstrap.inc
-		ldscript /southbridge/nvidia/ck804/romstrap.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit southbridge/nvidia/ck804/romstrap.inc
-		ldscript /southbridge/nvidia/ck804/romstrap.lds
-	end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup.
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-			ldscript /arch/i386/lib/failover_failover.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-			ldscript /arch/i386/lib/failover.lds
-	end
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-##
-## Include the secondary configuration files
-##
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_754			# Socket 754 CPU
-      device apic 0 on end			# APIC
-    end
-  end
-
-  device pci_domain 0 on			# PCI domain
-    chip northbridge/amd/amdk8			# mc0
-      device pci 18.0 on			# Northbridge
-        # Devices on link 0, link 0 == LDT 0
-        chip southbridge/nvidia/ck804		# Southbridge
-          device pci 0.0 on end			# HT
-          device pci 1.0 on			# LPC
-            chip superio/winbond/w83627thf	# Super I/O
-              device pnp 4e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 4e.1 on		# Parallel port
-                io 0x60 = 0x378
-                irq 0x70 = 7
-              end
-              device pnp 4e.2 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 4e.3 on		# Com2
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 4e.5 on		# PS/2 keyboard
-                io 0x60 = 0x60
-                io 0x62 = 0x64
-                irq 0x70 = 1
-                irq 0x72 = 12
-              end
-              device pnp 4e.7 off end		# Game, MIDI, GPIO 1, GPIO 5
-              device pnp 4e.8 off end		# GPIO 2
-              device pnp 4e.9 off end		# GPIO 3, GPIO 4
-              device pnp 4e.a off end		# ACPI
-              device pnp 4e.b on		# Hardware monitor
-                io 0x60 = 0x290
-                irq 0x70 = 0
-              end
-            end
-          end
-          device pci 1.1 on end			# SMbus
-          device pci 2.0 on end			# USB 1.1
-          device pci 2.1 on end			# USB 2
-          device pci 4.0 on end			# Onboard audio (ACI)
-          device pci 4.1 off end		# Onboard modem (MCI) -- not wired out
-          device pci 6.0 on end			# IDE
-          device pci 7.0 on end			# SATA 1
-          device pci 8.0 on end			# SATA 0
-          device pci 9.0 on end			# PCI
-          device pci a.0 on end			# NIC
-          device pci b.0 off end		# PCI E 3 -- not wired out
-          device pci c.0 off end		# PCI E 2 -- not wired out
-          device pci d.0 on end			# PCI E 1
-          device pci e.0 on end			# PCI E 0
-          register "ide0_enable" = "1"
-          register "ide1_enable" = "1"
-          register "sata0_enable" = "1"
-          register "sata1_enable" = "1"
-          # register "mac_eeprom_smbus" = "3"
-          # register "mac_eeprom_addr" = "0x51"
-        end
-      end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-  end
-end
diff --git a/src/mainboard/msi/ms7135/Options.lb b/src/mainboard/msi/ms7135/Options.lb
deleted file mode 100644
index b3b2b4b..0000000
--- a/src/mainboard/msi/ms7135/Options.lb
+++ /dev/null
@@ -1,321 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
-## (Thanks to LSRA University of Mannheim for their support)
-## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_AP_CODE_IN_CAR
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_MEM_TRAIN_SEQ
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_ID_SECTION_OFFSET
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-## ---> 512 Kbytes 
-default CONFIG_ROM_SIZE=(512*1024)
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-#FAILOVER: 4K
-default CONFIG_FAILOVER_SIZE=(4*1024)
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=13
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-##HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0
-
-##real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x10
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-##only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#BTEXT Console
-#default CONFIG_CONSOLE_BTEXT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-#default CONFIG_DCACHE_RAM_BASE=0xcf000
-#default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_AP_CODE_IN_CAR=0
-default CONFIG_MEM_TRAIN_SEQ=2
-default CONFIG_WAIT_BEFORE_CPUS_INIT=0
-
-## APIC stuff
-#default CONFIG_ENABLE_APIC_EXT_ID=0
-#default CONFIG_APIC_ID_OFFSET=0x10
-#default CONFIG_LIFT_BSP_APIC_ID=0
-
-
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="K8N Neo3 (MS-7135)"
-default CONFIG_MAINBOARD_VENDOR="MSI"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x7135
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = (64*1024) - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#efault CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/msi/ms7260/Config.lb b/src/mainboard/msi/ms7260/Config.lb
deleted file mode 100644
index f420731..0000000
--- a/src/mainboard/msi/ms7260/Config.lb
+++ /dev/null
@@ -1,288 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-driver mainboard.o
-object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables).
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-  if CONFIG_USE_INIT
-    makerule ./cache_as_ram_auto.o
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-    end
-  else
-    makerule ./cache_as_ram_auto.inc
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-      action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-      action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-    end
-  end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-  if CONFIG_AP_CODE_IN_CAR
-    makerule ./apc_auto.o
-      depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-    end
-    ldscript /arch/i386/init/ldscript_apc.lb
-  end
-end
-
-if CONFIG_HAVE_FAILOVER_BOOT
-  if CONFIG_USE_FAILOVER_IMAGE
-    mainboardinit cpu/x86/16bit/entry16.inc
-    ldscript /cpu/x86/16bit/entry16.lds
-  end
-else
-  if CONFIG_USE_FALLBACK_IMAGE
-    mainboardinit cpu/x86/16bit/entry16.inc
-    ldscript /cpu/x86/16bit/entry16.lds
-  end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-  if CONFIG_USE_INIT
-    ldscript /cpu/x86/32bit/entry32.lds
-  end
-  if CONFIG_USE_INIT
-    ldscript /cpu/amd/car/cache_as_ram.lds
-  end
-
-if CONFIG_HAVE_FAILOVER_BOOT
-  if CONFIG_USE_FAILOVER_IMAGE
-    mainboardinit cpu/x86/16bit/reset16.inc
-    ldscript /cpu/x86/16bit/reset16.lds
-  else
-    mainboardinit cpu/x86/32bit/reset32.inc
-    ldscript /cpu/x86/32bit/reset32.lds
-  end
-else
-  if CONFIG_USE_FALLBACK_IMAGE
-    mainboardinit cpu/x86/16bit/reset16.inc
-    ldscript /cpu/x86/16bit/reset16.lds
-  else
-    mainboardinit cpu/x86/32bit/reset32.inc
-    ldscript /cpu/x86/32bit/reset32.lds
-  end
-end
-
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-# ROMSTRAP table for MCP55.
-if CONFIG_HAVE_FAILOVER_BOOT
-  if CONFIG_USE_FAILOVER_IMAGE
-    mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-    ldscript /southbridge/nvidia/mcp55/romstrap.lds
-  end
-else
-  if CONFIG_USE_FALLBACK_IMAGE
-    mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-    ldscript /southbridge/nvidia/mcp55/romstrap.lds
-  end
-end
-
-  mainboardinit cpu/amd/car/cache_as_ram.inc
-
-if CONFIG_HAVE_FAILOVER_BOOT
-  if CONFIG_USE_FAILOVER_IMAGE
-      ldscript /arch/i386/lib/failover_failover.lds
-  end
-else
-  if CONFIG_USE_FALLBACK_IMAGE
-      ldscript /arch/i386/lib/failover.lds
-  end
-end
-
-  if CONFIG_USE_INIT
-    initobject cache_as_ram_auto.o
-  else
-    mainboardinit ./cache_as_ram_auto.inc
-  end
-
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_AM2			# CPU
-      device apic 0 on end			# APIC
-    end
-  end
-  device pci_domain 0 on			# PCI domain
-    chip northbridge/amd/amdk8			# Northbridge / mc0
-      device pci 18.0 on
-        # Devices on link 0, link 0 == LDT 0
-        chip southbridge/nvidia/mcp55		# Southbridge
-          device pci 0.0 on end			# HT
-          device pci 1.0 on			# LPC
-            chip superio/winbond/w83627ehg	# Super I/O
-              device pnp 4e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 4e.1 on		# Parallel port
-                io 0x60 = 0x378
-                irq 0x70 = 7
-              end
-              device pnp 4e.2 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 4e.3 on		# Com2 / IrDA
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 4e.5 on		# PS/2 keyboard
-                io 0x60 = 0x60
-                io 0x62 = 0x64
-                irq 0x70 = 1			# PS/2 keyboard IRQ
-                irq 0x72 = 12			# PS/2 mouse IRQ
-              end
-              device pnp 4e.6 off		# Serial flash interface
-                # io 0x62 = 0x100
-              end
-              device pnp 4e.7 off		# GPIO1/6, game port, MIDI port
-                # io 0x60 = 0x220		# Datasheet: 0x201
-                # io 0x62 = 0x300		# Datasheet: 0x330
-                # irq 0x70 = 9
-              end
-              device pnp 4e.8 off		# WDTO#, PLED
-              end
-              device pnp 4e.9 off		# GPIO2/3/4/5, SUSLED
-              end
-              device pnp 4e.a off		# ACPI
-              end
-              device pnp 4e.b on		# HWM (for lm-sensors)
-                io 0x60 = 0xa10
-              end
-            end
-          end
-          device pci 1.1 on			# SM 0
-            chip drivers/generic/generic	# DIMM 0-0-0
-              device i2c 50 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-0-1
-              device i2c 51 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-0
-              device i2c 52 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-1
-              device i2c 53 on end
-            end
-            # TODO: Needed?
-            # chip drivers/generic/generic	# DIMM 1-0-0
-            #   device i2c 54 on end
-            # end
-            # chip drivers/generic/generic	# DIMM 1-0-1
-            #   device i2c 55 on end
-            # end
-            # chip drivers/generic/generic	# DIMM 1-1-0
-            #   device i2c 56 on end
-            # end
-            # chip drivers/generic/generic	# DIMM 1-1-1
-            #   device i2c 57 on end
-            # end
-          end
-          # TODO: Check if the stuff below is correct / needed.
-          device pci 1.1 on			# SM 1
-            # PCI device SMBus address will depend on addon PCI device,
-            # do we need to scan_smbus_bus?
-
-            # chip drivers/generic/generic	# PCIXA Slot1
-            #   device i2c 50 on end
-            # end
-            # chip drivers/generic/generic	# PCIXB Slot1
-            #   device i2c 51 on end
-            # end
-            # chip drivers/generic/generic	# PCIXB Slot2
-            #   device i2c 52 on end
-            # end
-            # chip drivers/generic/generic	# PCI Slot1
-            #   device i2c 53 on end
-            # end
-            # chip drivers/generic/generic	# Master MCP55 PCI-E
-            #   device i2c 54 on end
-            # end
-            # chip drivers/generic/generic	# Slave MCP55 PCI-E
-            #   device i2c 55 on end
-            # end
-            chip drivers/generic/generic	# MAC EEPROM
-              device i2c 51 on end
-            end
-          end
-          device pci 2.0 on end			# USB 1.1
-          device pci 2.1 on end			# USB 2
-          device pci 4.0 on end			# IDE
-          device pci 5.0 on end			# SATA 0
-          device pci 5.1 on end			# SATA 1
-          device pci 5.2 off end		# SATA 2 (N/A on this board)
-          device pci 6.0 on end			# PCI
-          device pci 6.1 on end			# AZA (HD Audio)
-          device pci 8.0 on end			# NIC
-          device pci 9.0 off end		# NIC (N/A on this board)
-          device pci a.0 off end		# PCI E 5 (N/A on this board?)
-          device pci b.0 on end			# PCI E 4
-          device pci c.0 on end			# PCI E 3
-          device pci d.0 on end			# PCI E 2
-          device pci e.0 on end			# PCI E 1
-          device pci f.0 on end			# PCI E 0
-          register "ide0_enable" = "1"
-          register "sata0_enable" = "1"
-          register "sata1_enable" = "1"
-          # TODO: Check the two lines below.
-          register "mac_eeprom_smbus" = "3"	# 1: SMBus under 2e.8, 2: SM0 3: SM1
-          register "mac_eeprom_addr" = "0x51"
-        end
-      end
-      device pci 18.0 on end			# Link 1
-      device pci 18.0 on end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-  end
-
-# TODO
-#  chip drivers/generic/debug
-#    device pnp 0.0 off end			# chip name
-#    device pnp 0.1 on end			# pci_regs_all
-#    device pnp 0.2 on end			# mem
-#    device pnp 0.3 off end			# cpuid
-#    device pnp 0.4 on end			# smbus_regs_all
-#    device pnp 0.5 off end			# dual core msr
-#    device pnp 0.6 off end			# cache size
-#    device pnp 0.7 off end			# tsc
-#    device pnp 0.8 off end			# io
-#    device pnp 0.9 off end			# io
-#  end
-
-end
diff --git a/src/mainboard/msi/ms7260/Options.lb b/src/mainboard/msi/ms7260/Options.lb
deleted file mode 100644
index 1be372a..0000000
--- a/src/mainboard/msi/ms7260/Options.lb
+++ /dev/null
@@ -1,188 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER			# ?
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_USBDEBUG_DIRECT
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_SERIAL_CPU_INIT
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-uses CONFIG_PCI_64BIT_PREF_MEM
-uses CONFIG_RAMTOP
-uses CONFIG_AP_CODE_IN_CAR
-uses CONFIG_MEM_TRAIN_SEQ
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_ID_SECTION_OFFSET
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_FAILOVER_SIZE = 4 * 1024
-default CONFIG_RAMTOP = 2048*1024	# 1MB more for pgtbl.
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_HAVE_FAILOVER_BOOT = 1
-default CONFIG_HAVE_HARD_RESET = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 11		# TODO: Check if correct.
-default CONFIG_GENERATE_MP_TABLE = 1		# TODO: Check if correct.
-default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_SMP = 1
-default CONFIG_MAX_CPUS = 2
-default CONFIG_MAX_PHYSICAL_CPUS = 1
-default CONFIG_LOGICAL_CPUS = 1
-# default CONFIG_SERIAL_CPU_INIT = 0
-default CONFIG_ENABLE_APIC_EXT_ID = 0
-default CONFIG_APIC_ID_OFFSET = 0x10
-default CONFIG_LIFT_BSP_APIC_ID = 1
-
-# Move the default coreboot CMOS range off of AMD RTC registers.
-default CONFIG_LB_CKS_RANGE_START = 49
-default CONFIG_LB_CKS_RANGE_END = 122
-default CONFIG_LB_CKS_LOC = 123
-
-# Memory hole size. 0 means disable, others will enable the hole. In that
-# case, if it is smaller than mmio_basek, it will use mmio_basek instead.
-# default CONFIG_HW_MEM_HOLE_SIZEK = 0x200000	# 2GB
-default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000	# 1GB
-# default CONFIG_HW_MEM_HOLE_SIZEK = 0x80000	# 512MB
-
-# Make auto increase hole size to avoid hole_startk equal to basek so as
-# to make some kernel happy.
-# default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC = 1
-
-# Opteron K8 1G HT support.
-default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
-
-# HT Unit ID offset, default is 1, the typical one, 0 means only one HT device.
-default CONFIG_HT_CHAIN_UNITID_BASE = 0
-
-# Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-
-# Make the SB HT chain on bus 0, default is not (0).
-default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2
-
-# Only offset for SB chain? Default is yes (1).
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
-
-# Allow capable device use that above 4GB.
-# default CONFIG_PCI_64BIT_PREF_MEM = 1
-
-default CONFIG_CONSOLE_VGA = 1		# Needed for VGA.
-default CONFIG_PCI_ROM_RUN = 1		# Needed for VGA.
-default CONFIG_USBDEBUG_DIRECT = 0
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xc8000
-default CONFIG_DCACHE_RAM_SIZE = 0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
-default CONFIG_USE_INIT = 0
-default CONFIG_AP_CODE_IN_CAR = 0
-default CONFIG_MEM_TRAIN_SEQ = 2
-default CONFIG_WAIT_BEFORE_CPUS_INIT = 0
-default CONFIG_IOAPIC = 1
-default CONFIG_MAINBOARD_PART_NUMBER = "K9N Neo (MS-7260)"
-default CONFIG_MAINBOARD_VENDOR = "MSI"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-default CONFIG_STACK_SIZE = 0x2000
-default CONFIG_HEAP_SIZE = 0x8000
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE)
-default CONFIG_RAMBASE = 0x00100000
-default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_USE_PRINTK_IN_CAR = 1
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-end
diff --git a/src/mainboard/msi/ms9185/Config.lb b/src/mainboard/msi/ms9185/Config.lb
deleted file mode 100644
index c3bddcf..0000000
--- a/src/mainboard/msi/ms9185/Config.lb
+++ /dev/null
@@ -1,231 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## Copyright (C) 2006 MSI
-## Written by bxshi <bingxunshi@gmail.com> for MSI.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE
-       object mptable.o
-end
-
-if CONFIG_GENERATE_PIRQ_TABLE
-       object irq_tables.o
-end
-
-       if CONFIG_USE_INIT
-               # compile cache_as_ram.c to auto.o
-               makerule ./cache_as_ram_auto.o
-                       depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-               end
-
-       else
-               #compile cache_as_ram.c to auto.inc
-               makerule ./cache_as_ram_auto.inc
-                       depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-                       action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-                       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-               end
-
-       end
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-
-if CONFIG_USE_FALLBACK_IMAGE
-       mainboardinit cpu/x86/16bit/entry16.inc
-       ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-       mainboardinit cpu/x86/16bit/reset16.inc
-       ldscript /cpu/x86/16bit/reset16.lds
-else
-       mainboardinit cpu/x86/32bit/reset32.inc
-       ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-       ##
-       ## Setup Cache-As-Ram
-       ##
-       mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-               ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-       if CONFIG_USE_INIT
-               initobject cache_as_ram_auto.o
-       else
-               mainboardinit ./cache_as_ram_auto.inc
-       end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-# sample config for amd/serengeti_cheetah
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_F
-                        device apic 0 on end
-                end
-        end
-       device pci_domain 0 on
-               chip northbridge/amd/amdk8
-                       device pci 18.0 on end
-                       device pci 18.0 on end
-                       device pci 18.0 on #  northbridge
-                              #  devices on link 0
-                                chip southbridge/broadcom/bcm5780 # HT2000
-                                        device pci 0.0 on end   # PXB 1 0x0130
-                                        device pci 1.0 on       # PXB 2 0x0130
-                                                device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
-                                                device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
-                                        end
-                                        device pci 2.0 on end # PCI E 1  #0x0132
-                                       device pci 3.0 on end # PCI E 2
-                                       device pci 4.0 on end # PCI E 3
-                                       device pci 5.0 on end # PCI E 4
-                                end
-                                chip southbridge/broadcom/bcm5785 # HT1000
-                                        device pci 0.0 on  # HT PXB  0x0036
-                                                device pci d.0 on end # PPBX 0x0104
-                                                device pci e.0 on end # SATA 0x024a
-                                                device pci e.1 on end # SATA 0x024a bx_a001
-                                                device pci e.2 on end # SATA 0x024a bx_a001
-                                                device pci e.3 on end # SATA 0x024a bx_a001
-                                        end
-                                        device pci 1.0 on # Legacy  pci main  0x0205
-                                       end
-                                        device pci 1.1 on end # IDE        0x0214
-                                        device pci 1.2 on     # LPC        0x0234
-                                                chip superio/nsc/pc87417
-                                                        device  pnp 2e.0 off  # Floppy
-                                                                 io 0x60 = 0x3f0
-                                                                irq 0x70 = 6
-                                                                drq 0x74 = 2
-                                                        end
-                                                        device pnp 2e.1 off  # Parallel Port
-                                                                 io 0x60 = 0x378
-                                                                irq 0x70 = 7
-                                                        end
-                                                        device pnp 2e.2 off # Com 2
-                                                                 io 0x60 = 0x2f8
-                                                                irq 0x70 = 3
-                                                        end
-                                                        device pnp 2e.3 on  # Com 1
-                                                                 io 0x60 = 0x3f8
-                                                                irq 0x70 = 4
-                                                        end
-                                                        device pnp 2e.4 off end # SWC
-                                                        device pnp 2e.5 off end # Mouse
-                                                        device pnp 2e.6 on  # Keyboard
-                                                                 io 0x60 = 0x60
-                                                                 io 0x62 = 0x64
-                                                                irq 0x70 = 1
-                                                        end
-                                                        device pnp 2e.7 off end # GPIO
-                                                        device pnp 2e.f off end # XBUS
-                                                        device pnp 2e.10 on #RTC
-                                                                io 0x60 = 0x70
-                                                                io 0x62 = 0x72
-                                                       end
-                                                end
-                                        end
-                                        device pci 1.3 on end # WDTimer    0x0238
-                                        device pci 1.4 on end # XIOAPIC0   0x0235
-                                        device pci 1.5 on end # XIOAPIC1
-                                        device pci 1.6 on end # XIOAPIC2
-                                        device pci 2.0 on end # USB        0x0223
-                                        device pci 2.1 on end # USB
-                                        device pci 2.2 on end # USB
-                                        device pci 3.0 on end # it is in bcm5785_0 bus
-                                end
-                       end #  device pci 18.0
-                       device pci 18.1 on end
-                       device pci 18.2 on end
-                       device pci 18.3 on end
-               end # amdk8
-       end #pci_domain
-#        chip drivers/generic/debug
-#              device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 off end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#                device pnp 0.7 off end # tsc
-#       end
-
-end
-
-
diff --git a/src/mainboard/msi/ms9185/Options.lb b/src/mainboard/msi/ms9185/Options.lb
deleted file mode 100644
index d3423f5..0000000
--- a/src/mainboard/msi/ms9185/Options.lb
+++ /dev/null
@@ -1,327 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## Copyright (C) 2006 MSI
-## Written by bxshi <bingxunshi@gmail.com> for MSI.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-#default CONFIG_GENERATE_ACPI_TABLES=1
-## extra SSDT num
-#default CONFIG_ACPI_SSDTX_NUM=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x8
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0x06
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcc000
-default CONFIG_DCACHE_RAM_SIZE=0x04000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="MS9185"
-default CONFIG_MAINBOARD_VENDOR="MSI"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/msi/ms9282/Config.lb b/src/mainboard/msi/ms9282/Config.lb
deleted file mode 100644
index ec1211e..0000000
--- a/src/mainboard/msi/ms9282/Config.lb
+++ /dev/null
@@ -1,322 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## Copyright (C) 2006 MSI
-## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_ROM_PAYLOAD = 1
-
-arch i386 end
-
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/ati/ragexl
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else
-
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-       action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-       if CONFIG_USE_INIT
-               ldscript /cpu/x86/32bit/entry32.lds
-       end
-
-       if CONFIG_USE_INIT
-               ldscript      /cpu/amd/car/cache_as_ram.lds
-       end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-       mainboardinit cpu/x86/16bit/reset16.inc
-       ldscript /cpu/x86/16bit/reset16.lds
-else
-       mainboardinit cpu/x86/32bit/reset32.inc
-       ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_USE_FALLBACK_IMAGE
-       mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-       ldscript /southbridge/nvidia/mcp55/romstrap.lds
-end
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-
-# sample config for msi/ms9282
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_F
-                        device apic 0 on end
-                end
-        end
-
-       device pci_domain 0 on
-               chip northbridge/amd/amdk8 #mc0
-                       device pci 18.0 on #  northbridge
-                               #  devices on link 0, link 0 == LDT 0
-                               chip southbridge/nvidia/mcp55
-                                       device pci 0.0 on end   # HT
-                                       device pci 1.0 on # LPC
-                                               chip superio/winbond/w83627ehg
-                                                       device pnp 2e.0 on #  Floppy
-                                                               io 0x60 = 0x3f0
-                                                               irq 0x70 = 6
-                                                               drq 0x74 = 2
-                                                       end
-                                                       device pnp 2e.1 off #  Parallel Port
-                                                               io 0x60 = 0x378
-                                                               irq 0x70 = 7
-                                                       end
-                                                       device pnp 2e.2 on #  Com1
-                                                               io 0x60 = 0x3f8
-                                                               irq 0x70 = 4
-                                                       end
-                                                       device pnp 2e.3 off #  Com2
-                                                               io 0x60 = 0x2f8
-                                                               irq 0x70 = 3
-                                                       end
-                                                       device pnp 2e.5 on #  Keyboard
-                                                               io 0x60 = 0x60
-                                                               io 0x62 = 0x64
-                                                               irq 0x70 = 1
-                                                               irq 0x72 = 12
-                                                       end
-                                                       device pnp 2e.6 off #  SERIAL_FALSH
-                                                               io 0x60 = 0x100
-                                                       end
-                                                       device pnp 2e.7 off #  GAME_MIDI_GIPO1
-                                                               io 0x60 = 0x220
-                                                               io 0x62 = 0x300
-                                                               irq 0x70 = 9
-                                                       end
-                                                       device pnp 2e.8 off end #  WDTO_PLED
-                                                       device pnp 2e.9 off end #  GPIO2_GPIO3_GPIO4_GPIO5
-                                                       device pnp 2e.a off end #  ACPI
-                                                       device pnp 2e.b on #  HW Monitor
-                                                               io 0x60 = 0x290
-                                                               irq 0x70 = 5
-                                                       end
-                                               end
-                                       end
-                                        device pci 1.1 on # SM 0
-                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
-                                                       device i2c 70 on  #0 pca9554 1
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 54 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 55 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 56 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 57 on end
-                                                                end
-                                                       end
-                                                       device i2c 70 on  #0 pca9554 2
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 54 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 55 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 56 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 57 on end
-                                                                end
-                                                       end
-                                               end
-                                       end
-                                       device pci 1.1 on # SM 1
-                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
-                                                       device i2c 72 on     #pca9554 channle1
-                                                               chip drivers/i2c/adm1027   #HWM ADT7476 1
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                                       device i2c 72 on     #pca9545 channel 2
-                                                               chip drivers/i2c/adm1027   #HWM ADT7463
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                                       device i2c 72 on end  #pca9545 channel 3
-                                                       device i2c 72 on      #pca9545 channel 4
-                                                               chip drivers/i2c/adm1027   #HWM ADT7476 2
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                               end
-                                       end
-
-                                       device pci 2.0 on end # USB 1.1
-                                       device pci 2.1 on end # USB 2
-                                       device pci 4.0 on  end # IDE
-                                               device pci 5.0 on  end # SATA 0
-                                       device pci 5.1 on  end # SATA 1
-                                       device pci 5.2 on  end # SATA 2
-                                       device pci 6.0 on  #P2P
-                                               device pci 4.0 on end
-                                       end # P2P
-                                       device pci 7.0 on end # reserve
-                                       device pci 8.0 on end # MAC0
-                                       device pci 9.0 on end # MAC1
-                                       device pci a.0 on
-                                               device pci 0.0 on
-                                                       device pci 4.0 on end  #pci_E lan1
-                                                       device pci 4.1 on end  #pci_E lan2
-                                               end
-                                       end # 0x376
-                                               device pci b.0 on  end # PCI E 0x374
-                                       device pci c.0 on  end
-                                       device pci d.0 on   #SAS
-                                               device pci 0.0 on end
-                                       end # PCI E 1 0x378
-                                       device pci e.0 on end # PCI E 0 0x375
-                                       device pci f.0 on end   #PCI E 0x377  pci_E slot
-                                       register "ide0_enable" = "1"
-                                       register "ide1_enable" = "1"
-                                       register "sata0_enable" = "1"
-                                       register "sata1_enable" = "1"
-                               end
-                       end #  device pci 18.0
-                       device pci 18.0 on end # Link 1
-                       device pci 18.0 on end
-                       device pci 18.1 on end
-                       device pci 18.2 on end
-                       device pci 18.3 on end
-               end #mc0
-
-       end # pci_domain
-
-#        chip drivers/generic/debug
-#                device pnp 0.0 off end
-#                device pnp 0.1 off end
-#                device pnp 0.2 off end
-#                device pnp 0.3 off end
-#                device pnp 0.4 off end
-#              device pnp 0.5 on end
-#        end
-end # root_complex
diff --git a/src/mainboard/msi/ms9282/Options.lb b/src/mainboard/msi/ms9282/Options.lb
deleted file mode 100644
index ee8be01..0000000
--- a/src/mainboard/msi/ms9282/Options.lb
+++ /dev/null
@@ -1,311 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## Copyright (C) 2006 MSI
-## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-#bx_b001- uses K8_HW_MEM_HOLE_SIZEK
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-#bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-#bx_b005+
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-
-# stepan 2007-04-12
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ID_SECTION_OFFSET
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-#512K bytes
-default CONFIG_ROM_SIZE=524288
-
-#1M bytes
-#bx- default CONFIG_ROM_SIZE=1048576
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-##HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-##real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0
-
-#make the SB HT chain on bus 0, default is not (0)
-#bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2
-
-##bx_b005+ make the SB HT chain on bus 0
-default CONFIG_SB_HT_CHAIN_ON_BUS0=1
-
-##only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#VGA
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcc000
-default CONFIG_DCACHE_RAM_SIZE=0x4000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=1
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="ms9282"
-default CONFIG_MAINBOARD_VENDOR="MSI"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/nec/powermate2000/Config.lb b/src/mainboard/nec/powermate2000/Config.lb
deleted file mode 100644
index e63b147..0000000
--- a/src/mainboard/nec/powermate2000/Config.lb
+++ /dev/null
@@ -1,123 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i82810			# Northbridge
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/intel/socket_PGA370		# CPU
-      device apic 0 on end			# APIC
-    end
-  end
-  device pci_domain 0 on
-    device pci 0.0 on end			# Host bridge
-    device pci 1.0 off end			# Onboard video
-    chip southbridge/intel/i82801xx		# Southbridge
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-
-      device pci 1e.0 on end			# PCI bridge
-      device pci 1f.0 on			# ISA/LPC bridge
-        chip superio/smsc/smscsuperio		# Super I/O (SMSC LPC47B27x)
-          device pnp 2e.0 on			# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.3 on			# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 2e.4 on			# Com1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.5 off end		# Com2 (N/A)
-          device pnp 2e.7 on			# PS/2 keyboard
-            irq 0x70 = 1
-            irq 0x72 = 0
-          end
-          device pnp 2e.9 off end		# Game port (N/A)
-          device pnp 2e.a on			# Power-management events (PME)
-            io 0x60 = 0x800
-          end
-          device pnp 2e.b on			# MIDI port
-            io 0x60 = 0x330
-            irq 0x70 = 5
-          end
-        end
-      end
-      device pci 1f.1 on end			# IDE
-      device pci 1f.2 on end			# USB
-      device pci 1f.3 on end			# SMBus
-      device pci 1f.5 on end			# AC'97 audio
-      device pci 1f.6 off end			# AC'97 modem (N/A)
-    end
-  end
-end
-
diff --git a/src/mainboard/nec/powermate2000/Options.lb b/src/mainboard/nec/powermate2000/Options.lb
deleted file mode 100644
index 735f30c..0000000
--- a/src/mainboard/nec/powermate2000/Options.lb
+++ /dev/null
@@ -1,96 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 5		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/newisys/khepri/Config.lb b/src/mainboard/newisys/khepri/Config.lb
deleted file mode 100644
index f053e66..0000000
--- a/src/mainboard/newisys/khepri/Config.lb
+++ /dev/null
@@ -1,192 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_940
-			device apic 0 on end
-		end
-		chip cpu/amd/socket_940
-			device apic 1 on end
-		end
-	end
-
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on end # LDT 0 
-			device pci 18.0 on     # LDT 1
-				chip southbridge/amd/amd8131
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 on end
-						device pci 1.0 on end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 on #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 on #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	        			device pnp 2e.6 off #  CIR
-								io 0x60 = 0x100
-							end
-                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end						
-                	        			device pnp 2e.8 off end #  GPIO2
-                	        			device pnp 2e.9 off end #  GPIO3
-                	        			device pnp 2e.a off end #  ACPI
-                	        			device pnp 2e.b on #  HW Monitor
- 					 			io 0x60 = 0x290
-								irq 0x70 = 5
-                					end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on end 
-					device pci 1.5 on end
-					device pci 1.6 on end
-				end
-			end # LDT1
-			device pci 18.0 on end # LDT2
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-		chip northbridge/amd/amdk8
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-		end
-	end 
-end
-
diff --git a/src/mainboard/newisys/khepri/Options.lb b/src/mainboard/newisys/khepri/Options.lb
deleted file mode 100644
index ad54dc6..0000000
--- a/src/mainboard/newisys/khepri/Options.lb
+++ /dev/null
@@ -1,243 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="Khepri"
-default CONFIG_MAINBOARD_VENDOR="Newisys"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/nvidia/l1_2pvv/Config.lb b/src/mainboard/nvidia/l1_2pvv/Config.lb
deleted file mode 100644
index ba30037..0000000
--- a/src/mainboard/nvidia/l1_2pvv/Config.lb
+++ /dev/null
@@ -1,373 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object acpi_tables.o
-	object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "mv dsdt_lb.hex dsdt.c"
-	end
-	object ./dsdt.o
-
-	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
-
-	if CONFIG_ACPI_SSDTX_NUM
-	    makerule ssdt6.c
-			depends "$(CONFIG_MAINBOARD)/dx/pci6.asl"
-			action  "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci6.asl"
-			action  "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
-			action  "mv pci6.hex ssdt6.c"
-	    end
-	    object ./ssdt6.o
-	    makerule ssdt5.c
-			depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
-			action  "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
-			action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
-			action  "mv pci5.hex ssdt5.c"
-	    end
-	    object ./ssdt5.o
-	end
-end
-
-	if CONFIG_USE_INIT
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-	makerule ./apc_auto.o
-		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-	end
-	ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_F
-			device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on
-				#  devices on link 0, link 0 == LDT 0
-				chip southbridge/nvidia/mcp55
-					device pci 0.0 on end   # HT
-					device pci 1.0 on # LPC
-						chip superio/winbond/w83627ehg
-							device pnp 2e.0 off #  Floppy
-					 			io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off #  Parallel Port
-					 			io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on #  Com1
-					 			io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 off #  Com2
-					 			io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.5 on #  Keyboard
-					 			io 0x60 = 0x60
-					 			io 0x62 = 0x64
-								irq 0x70 = 1
-								irq 0x72 = 12
-							end
-							device pnp 2e.6 off  # SFI
-					 			io 0x62 = 0x100
-							end
-							device pnp 2e.7 off #  GPIO_GAME_MIDI
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end
-							device pnp 2e.8 off end #  WDTO_PLED
-							device pnp 2e.9 off end #  GPIO_SUSLED
-							device pnp 2e.a off end #  ACPI
-							device pnp 2e.b on #  HW Monitor
- 					 			io 0x60 = 0x290
-								irq 0x70 = 5
-							end
-						end
-					end
-					device pci 1.1 on # SM 0
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end
-						chip drivers/generic/generic #dimm 1-0-0
-							device i2c 54 on end
-						end
-						chip drivers/generic/generic #dimm 1-0-1
-							device i2c 55 on end
-						end
-						chip drivers/generic/generic #dimm 1-1-0
-							device i2c 56 on end
-						end
-						chip drivers/generic/generic #dimm 1-1-1
-							device i2c 57 on end
-						end
-					end # SM
-					device pci 1.1 on # SM 1
-#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#						chip drivers/generic/generic #PCIXA Slot1
-#							device i2c 50 on end
-#						end
-#						chip drivers/generic/generic #PCIXB Slot1
-#							device i2c 51 on end
-#						end
-#						chip drivers/generic/generic #PCIXB Slot2
-#							device i2c 52 on end
-#						end
-#						chip drivers/generic/generic #PCI Slot1
-#							device i2c 53 on end
-#						end
-#						chip drivers/generic/generic #Master MCP55 PCI-E
-#							device i2c 54 on end
-#						end
-#						chip drivers/generic/generic #Slave MCP55 PCI-E
-#							device i2c 55 on end
-#						end
-						chip drivers/generic/generic #MAC EEPROM
-							device i2c 51 on end
-						end
-
-					end # SM
-					device pci 2.0 on end # USB 1.1
-					device pci 2.1 on end # USB 2
-					device pci 4.0 on end # IDE
-					device pci 5.0 on end # SATA 0
-					device pci 5.1 on end # SATA 1
-					device pci 5.2 on end # SATA 2
-					device pci 6.0 on end # PCI
-					device pci 6.1 on end # AZA
-					device pci 8.0 on end # NIC
-					device pci 9.0 on end # NIC
-		       			device pci a.0 on end # PCI E 5
-		       			device pci b.0 off end # PCI E 4
-					device pci c.0 off end # PCI E 3
-					device pci d.0 on end # PCI E 2
-					device pci e.0 off end # PCI E 1
-		       			device pci f.0 on end # PCI E 0
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "sata1_enable" = "1"
-					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end #  device pci 18.0
-			device pci 18.0 on end # Link 1
-			device pci 18.0 on
-				#  devices on link 2, link 2 == LDT 2
-				chip southbridge/nvidia/mcp55
-					device pci 0.0 on end   # HT
-					device pci 1.0 on end  # LPC
-					device pci 1.1 on end # SM 0
-					device pci 2.0 off end # USB 1.1
-					device pci 2.1 off end # USB 2
-					device pci 4.0 off end # IDE
-					device pci 5.0 on end # SATA 0
-					device pci 5.1 on end # SATA 1
-					device pci 5.2 on end # SATA 2
-					device pci 6.0 off end # PCI
-					device pci 6.1 off end # AZA
-					device pci 8.0 on end # NIC
-					device pci 9.0 on end # NIC
-		       			device pci a.0 on end # PCI E 5
-		       			device pci b.0 off end # PCI E 4
-					device pci c.0 off end # PCI E 3
-					device pci d.0 on end # PCI E 2
-					device pci e.0 on end # PCI E 1
-		       			device pci f.0 on end # PCI E 0
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "sata1_enable" = "1"
-					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end # device pci 18.0
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end # mc0
-
-	end # PCI domain
-
-#       chip drivers/generic/debug
-#		device pnp 0.0 off end # chip name
-#		device pnp 0.1 on end # pci_regs_all
-#		device pnp 0.2 on end # mem
-#		device pnp 0.3 off end # cpuid
-#		device pnp 0.4 on end # smbus_regs_all
-#		device pnp 0.5 off end # dual core msr
-#		device pnp 0.6 off end # cache size
-#		device pnp 0.7 off end # tsc
-#		device pnp 0.8 off  end # io
-#		device pnp 0.9 off end # io
-#       end
-end #root_complex
diff --git a/src/mainboard/nvidia/l1_2pvv/Options.lb b/src/mainboard/nvidia/l1_2pvv/Options.lb
deleted file mode 100644
index 00efb92..0000000
--- a/src/mainboard/nvidia/l1_2pvv/Options.lb
+++ /dev/null
@@ -1,353 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_USBDEBUG_DIRECT
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ID_SECTION_OFFSET
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-#default CONFIG_ROM_SIZE=0x100000
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-#FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#FAILOVER: 4K
-default CONFIG_FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=0
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#default CONFIG_USBDEBUG_DIRECT=1
-
-#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default CONFIG_HT_CHAIN_UNITID_BASE=0
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_AP_CODE_IN_CAR=0
-default CONFIG_MEM_TRAIN_SEQ=1
-default CONFIG_WAIT_BEFORE_CPUS_INIT=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="l1_2pvv"
-default CONFIG_MAINBOARD_VENDOR="NVIDIA"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-#default CONFIG_COMPRESSED_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/olpc/btest/Config.lb b/src/mainboard/olpc/btest/Config.lb
deleted file mode 100644
index 9edcbd0..0000000
--- a/src/mainboard/olpc/btest/Config.lb
+++ /dev/null
@@ -1,139 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx2
-	register "irqmap" = "0xaa5b"
-	register "setupflash" = "0"
-	device apic_cluster 0 on
-		chip cpu/amd/model_gx2
-			device apic 0 on end
-		end
-	end
-  	device pci_domain 0 on 
-    		device pci 1.0 on end
-		device pci 1.1 on end
-      		chip southbridge/amd/cs5536
-		# 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002
-		# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-		# 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080.
-		# Frame Pulse Width = 4clocks
-		# IRQ Data Frames = 17Frames
-		# SIRQ Mode = continous , It would be better if the EC could operate in
-		# Active(Quiet) mode. Save power....
-		# SIRQ Enable = Enabled
-		# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK 
-			#register "lpc_irq" = "0x00001002"
-			#register "lpc_serirq_enable" = "0xEFFD0080"
-			#register "enable_gpio0_inta" = "1"
-			#register "enable_ide_nand_flash" = "1"
-			#register "enable_uarta" = "1"
-			#register "enable_USBP4_host" = "1"
-			#register "audio_irq" = "5"
-			#register "usbf4_irq" = "10"
-			#register "usbf5_irq" = "10"
-			#register "usbf6_irq" = "0"
-			#register "usbf7_irq" = "0"
-        		device pci d.0 on end	# Realtek 8139 LAN
-        		device pci f.0 on end	# ISA Bridge
-        		device pci f.2 on end	# IDE Controller
-        		device pci f.3 on end 	# Audio
-        		device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-			register "unwanted_vpci[0]" = "0x80007E00"	# USB/UDC
-			register "unwanted_vpci[1]" = "0x80007F00"	# USB/OTG
-			register "unwanted_vpci[2]" = "0"	# End of list has a zero
-      		end
-    	end
-end
-
diff --git a/src/mainboard/olpc/btest/Options.lb b/src/mainboard/olpc/btest/Options.lb
deleted file mode 100644
index ab05e04..0000000
--- a/src/mainboard/olpc/btest/Options.lb
+++ /dev/null
@@ -1,160 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=2
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb
deleted file mode 100644
index 9edcbd0..0000000
--- a/src/mainboard/olpc/rev_a/Config.lb
+++ /dev/null
@@ -1,139 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx2
-	register "irqmap" = "0xaa5b"
-	register "setupflash" = "0"
-	device apic_cluster 0 on
-		chip cpu/amd/model_gx2
-			device apic 0 on end
-		end
-	end
-  	device pci_domain 0 on 
-    		device pci 1.0 on end
-		device pci 1.1 on end
-      		chip southbridge/amd/cs5536
-		# 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002
-		# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-		# 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080.
-		# Frame Pulse Width = 4clocks
-		# IRQ Data Frames = 17Frames
-		# SIRQ Mode = continous , It would be better if the EC could operate in
-		# Active(Quiet) mode. Save power....
-		# SIRQ Enable = Enabled
-		# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK 
-			#register "lpc_irq" = "0x00001002"
-			#register "lpc_serirq_enable" = "0xEFFD0080"
-			#register "enable_gpio0_inta" = "1"
-			#register "enable_ide_nand_flash" = "1"
-			#register "enable_uarta" = "1"
-			#register "enable_USBP4_host" = "1"
-			#register "audio_irq" = "5"
-			#register "usbf4_irq" = "10"
-			#register "usbf5_irq" = "10"
-			#register "usbf6_irq" = "0"
-			#register "usbf7_irq" = "0"
-        		device pci d.0 on end	# Realtek 8139 LAN
-        		device pci f.0 on end	# ISA Bridge
-        		device pci f.2 on end	# IDE Controller
-        		device pci f.3 on end 	# Audio
-        		device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-			register "unwanted_vpci[0]" = "0x80007E00"	# USB/UDC
-			register "unwanted_vpci[1]" = "0x80007F00"	# USB/OTG
-			register "unwanted_vpci[2]" = "0"	# End of list has a zero
-      		end
-    	end
-end
-
diff --git a/src/mainboard/olpc/rev_a/Options.lb b/src/mainboard/olpc/rev_a/Options.lb
deleted file mode 100644
index ab05e04..0000000
--- a/src/mainboard/olpc/rev_a/Options.lb
+++ /dev/null
@@ -1,160 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=2
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/pcengines/alix1c/Config.lb b/src/mainboard/pcengines/alix1c/Config.lb
deleted file mode 100644
index 38da739..0000000
--- a/src/mainboard/pcengines/alix1c/Config.lb
+++ /dev/null
@@ -1,190 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006-2007 Ronald G. Minnich <rminnich@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-	#compile cache_as_ram.c to auto.inc
-	makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-#	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/lx
-  	device pci_domain 0 on 
-    		device pci 1.0 on end
-		device pci 1.1 on end
-      		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
-			# How to get these? Boot linux and do this:
-			# rdmsr 0x51400025
-			register "lpc_serirq_enable" = "0x0000105a"
-			# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
-			register "lpc_serirq_polarity" = "0x0000EFA5"
-			# mode is high 10 bits (determined from code)
-			register "lpc_serirq_mode" = "1"
-			# Don't yet know how to find this.
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "0"	#0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "0"
-			register "com1_address" = "0x3F8"
-			register "com1_irq" = "4"
-			register "com2_enable" = "0"
-			register "com2_address" = "0x2F8"
-			register "com2_irq" = "3"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-        			device pci f.0 on	# ISA Bridge
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 off #  Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.1 on #  Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.2 on #  Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on #  Com2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.5 on #  Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-					device pnp 2e.6 off #  CIR
-						io 0x60 = 0x100
-					end
-					device pnp 2e.7 off #  GAME_MIDI_GIPO1
-						io 0x60 = 0x220
-						io 0x62 = 0x300
-						irq 0x70 = 9
-					end						
-					device pnp 2e.8 on end #  GPIO2
-					device pnp 2e.9 on end #  GPIO3
-					device pnp 2e.a on end #  ACPI
-					device pnp 2e.b on #  HW Monitor
-						io 0x60 = 0x290
-						irq 0x70 = 5
-					end
-				end
-			end
-			device pci f.1 on end	# Flash controller
-			device pci f.2 on end	# IDE controller
-        			device pci f.3 on end 	# Audio
-        			device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-      		end
-	end
-
-	# APIC cluster is late CPU init.
-	device apic_cluster 0 on
-		chip cpu/amd/model_lx
-			device apic 0 on end
-		end
-	end
-
-end
-
diff --git a/src/mainboard/pcengines/alix1c/Options.lb b/src/mainboard/pcengines/alix1c/Options.lb
deleted file mode 100644
index 37fa14a..0000000
--- a/src/mainboard/pcengines/alix1c/Options.lb
+++ /dev/null
@@ -1,198 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006-2007 Ronald G. Minnich <rminnich@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 512*1024
-
-###
-### Build options
-###
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_VIDEO_MB=8
-default CONFIG_PCI_ROM_RUN=0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=5
-default CONFIG_PIRQ_ROUTE=1
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/rca/rm4100/Config.lb b/src/mainboard/rca/rm4100/Config.lb
deleted file mode 100644
index 648be34..0000000
--- a/src/mainboard/rca/rm4100/Config.lb
+++ /dev/null
@@ -1,144 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object dsdt.o
-	object acpi_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i82830		# Northbridge
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    chip southbridge/intel/i82801xx	# Southbridge
-      register "pirqa_routing" = "0x05"
-      register "pirqb_routing" = "0x06"
-      register "pirqc_routing" = "0x07"
-      register "pirqd_routing" = "0x09"
-      register "pirqe_routing" = "0x0a"
-      register "pirqf_routing" = "0x80"
-      register "pirqg_routing" = "0x80"
-      register "pirqh_routing" = "0x0b"
-
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-
-      device pci 1d.0 on end		# USB UHCI Controller #1
-      device pci 1d.1 on end		# USB UHCI Controller #2
-      device pci 1d.2 on end		# USB UHCI Controller #3
-      device pci 1d.7 on end		# USB2 EHCI Controller
-      device pci 1e.0 on		# PCI bridge
-        device pci 08.0 on end		# Intel 82801DB PRO/100 VE Ethernet
-      end
-      device pci 1f.0 on		# ISA/LPC bridge
-        chip superio/smsc/smscsuperio	# Super I/O
-          device pnp 2e.0 off		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 4
-          end
-          device pnp 2e.4 on		# Com1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.5 on		# Com2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.7 on		# PS/2 keyboard/mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# Keyboard interrupt
-            irq 0x72 = 12		# Mouse interrupt
-          end
-          device pnp 2e.9 off end	# Game port
-          device pnp 2e.a on		# PME
-            io 0x60 = 0x800
-          end
-          device pnp 2e.b off end	# MPU-401
-        end
-      end
-      device pci 1f.1 on end		# IDE
-      device pci 1f.3 on end		# SMBus
-      device pci 1f.5 on end		# AC'97 audio
-      device pci 1f.6 on end		# AC'97 modem
-    end
-  end
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/socket_PGA370	# Mobile Celeron Micro-FCBGA Socket 479
-      device apic 0 on end		# APIC
-    end
-  end
-end
-
diff --git a/src/mainboard/rca/rm4100/Options.lb b/src/mainboard/rca/rm4100/Options.lb
deleted file mode 100644
index c9b28ce..0000000
--- a/src/mainboard/rca/rm4100/Options.lb
+++ /dev/null
@@ -1,96 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CC
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_IOAPIC
-uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_UDELAY_TSC
-uses CONFIG_VIDEO_MB
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_HEAP_SIZE
-uses HOSTCC
-uses CONFIG_IRQ_SLOT_COUNT
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_OBJCOPY
-uses CONFIG_RAMBASE
-uses CONFIG_ROMBASE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_LCS
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_GENERATE_ACPI_TABLES = 0
-default CONFIG_IOAPIC = 0
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0
-default CONFIG_VIDEO_MB = 0
-default CONFIG_STACK_SIZE = 0x2000
-default CONFIG_HEAP_SIZE = 0x4000
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_ROM_PAYLOAD = 1
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3	# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAINBOARD_VENDOR = "RCA"
-default CONFIG_MAINBOARD_PART_NUMBER = "RM4100"
-end
diff --git a/src/mainboard/roda/rk886ex/Config.lb b/src/mainboard/roda/rk886ex/Config.lb
deleted file mode 100644
index 259eb31..0000000
--- a/src/mainboard/roda/rk886ex/Config.lb
+++ /dev/null
@@ -1,237 +0,0 @@
-##
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-## 
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Image size calculation
-##
-
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-driver rtl8168.o
-object ec.o
-object m3885.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object acpi_tables.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dsdt.asl"
-		action  "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD)  $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl"
-		action  "iasl -p dsdt -tc $(CURDIR)/dsdt.asl"
-		action  "mv $(CURDIR)/dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
-	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I.  -c $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-else
-
-makerule ./auto.inc
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
-	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
-	action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-	action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-if CONFIG_USE_INIT
-	ldscript /cpu/x86/32bit/entry32.lds
-	ldscript /cpu/x86/car/cache_as_ram.lds
-end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-        mainboardinit cpu/x86/16bit/reset16.inc
-        ldscript /cpu/x86/16bit/reset16.lds
-else
-        mainboardinit cpu/x86/32bit/reset32.inc
-        ldscript /cpu/x86/32bit/reset32.lds
-end
-
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i945
-
-        device apic_cluster 0 on
-                chip cpu/intel/socket_mFCPGA478
-                        device apic 0 on end
-                end
-        end
-
-        device pci_domain 0 on 
-                device pci 00.0 on end # host bridge
-		# auto detection:
-		#device pci 01.0 off end # i945 PCIe root port
-		#device pci 02.0 on end # vga controller
-		#device pci 02.1 on end # display controller
-
-                chip southbridge/intel/i82801gx
-			register "pirqa_routing" = "0x0b"
-			register "pirqb_routing" = "0x0b"
-			register "pirqc_routing" = "0x0b"
-			register "pirqd_routing" = "0x0b"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x0b"
-			register "pirqh_routing" = "0x0b"
-
-			# GPI routing
-			#  0 No effect (default)
-			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
-			#  2 SCI (if corresponding GPIO_EN bit is also set)
-			register "gpi13_routing" = "2"
-			register "gpi8_routing"  = "1"
-			register "gpi7_routing"  = "2"
-			register "gpe0_en" = "0x20800007"
-
-                        register "ide_legacy_combined" = "0x1"
-                        register "ide_enable_primary" = "0x1"
-                        register "ide_enable_secondary" = "0x0"
-                        register "sata_ahci" = "0x0"
-
-                	device pci 1b.0 on end # High Definition Audio
-                	device pci 1c.0 on end # PCIe
-                	device pci 1c.1 on end # PCIe
-                	device pci 1c.2 on end # PCIe
-			#device pci 1c.3 off end # PCIe port 4
-			#device pci 1c.4 off end # PCIe port 5
-			#device pci 1c.5 off end # PCIe port 6
-                	device pci 1d.0 on end # USB UHCI
-                	device pci 1d.1 on end # USB UHCI
-                	device pci 1d.2 on end # USB UHCI
-                	device pci 1d.3 on end # USB UHCI
-                	device pci 1d.7 on end # USB2 EHCI
-                	device pci 1e.0 on
-				chip southbridge/ti/pci7420
-                        		register "smartcard_enabled" = "0x0"
-					device pci 3.0 on end
-					device pci 3.1 on end
-					device pci 3.2 on end
-					device pci 3.3 off end  # smartcard
-				end
-			end # PCI bridge
-			#device pci 1e.2 off end # AC'97 Audio 
-			#device pci 1e.3 off end # AC'97 Modem
-                        device pci 1f.0 on # LPC bridge
-                                chip superio/smsc/lpc47n227
-					device pnp 2e.1 off # Parallel port
-					end
-					device pnp 2e.2 on # COM1
-                                                 io 0x60 = 0x3f8
-                                                irq 0x70 = 4
-					end
-					device pnp 2e.3 on # COM2
-                                                 io 0x60 = 0x2f8
-                                                irq 0x70 = 3
-					end
-					device pnp 2e.5 off # Keyboard+Mouse
-					#	 io 0x60 = 0x60
-					#	 io 0x62 = 0x64
-					#	irq 0x70 = 1
-					#	irq 0x72 = 12
-					end
-                                end
-				chip superio/renesas/m3885x
-					device pnp ff.1 on # dummy address
-					end
-				end
-
-                        end
-			#device pci 1f.1 off end # IDE
-                        device pci 1f.2 on end  # SATA
-                        device pci 1f.3 on end  # SMBus
-			#device pci 1f.4 off end # Realtek ID Codec
-                end
-        end
-end
diff --git a/src/mainboard/roda/rk886ex/Options.lb b/src/mainboard/roda/rk886ex/Options.lb
deleted file mode 100644
index 7352232..0000000
--- a/src/mainboard/roda/rk886ex/Options.lb
+++ /dev/null
@@ -1,339 +0,0 @@
-##
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-# Tables
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-uses CONFIG_HAVE_ACPI_RESUME
-# SMP
-uses CONFIG_SMP
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_AP_IN_SIPI_WAIT
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-# Image Size
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-# Payload
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-# Build Internals
-uses CONFIG_RAMBASE
-uses CONFIG_ROMBASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_SMI_HANDLER
-uses CONFIG_PCIE_CONFIGSPACE_HOLE
-uses CONFIG_MMCONF_SUPPORT
-uses CONFIG_MMCONF_BASE_ADDRESS
-uses CONFIG_GFXUMA
-#
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-# Timers
-uses CONFIG_UDELAY_LAPIC
-# Console
-uses CONFIG_USBDEBUG_DIRECT
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
-uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-uses CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES
-uses CONFIG_DEBUG
-# Toolchain
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-# Tweaks
-uses CONFIG_GDB_STUB
-uses CONFIG_MAX_REBOOT_CNT
-uses CONFIG_USE_WATCHDOG_ON_BOOT
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-
-###
-### Build options
-###
-
-##
-##
-default CONFIG_MAX_REBOOT_CNT=3
-
-##
-## Use the watchdog to break out of a lockup condition
-##
-default CONFIG_USE_WATCHDOG_ON_BOOT=0
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1024*1024
-
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## 
-default CONFIG_UDELAY_LAPIC=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build SMI handler
-##
-default CONFIG_HAVE_SMI_HANDLER=1
-
-##
-## Leave a hole for mmapped PCIe config space
-##
-
-default CONFIG_PCIE_CONFIGSPACE_HOLE=1
-default CONFIG_MMCONF_SUPPORT=1
-default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
-
-##
-## UMA
-##
-default CONFIG_GFXUMA=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=18
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to provide ACPI support
-##
-default CONFIG_GENERATE_ACPI_TABLES=1
-default CONFIG_HAVE_MAINBOARD_RESOURCES=1
-default CONFIG_HAVE_ACPI_RESUME=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default CONFIG_coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_PCI_ROM_RUN=0
-#default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1
-#default CONFIG_PCI_OPTION_ROM_RUN_YABEL=0
-# This is needed for Intel's IGD design:
-#default CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=1
-#default CONFIG_DEBUG=0
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-default CONFIG_AP_IN_SIPI_WAIT=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024)
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Execute In Place settings
-##
-
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="RK886EX"
-default CONFIG_MAINBOARD_VENDOR=     "RODA"
-
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x4352
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6886
-
-###
-### coreboot layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 32K stack
-##
-default CONFIG_STACK_SIZE=0x8000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=1
-
-##
-## USB debug console
-##
-
-default CONFIG_USBDEBUG_DIRECT=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb b/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb
deleted file mode 100644
index cdf4b58..0000000
--- a/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb
+++ /dev/null
@@ -1,126 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/ite/it8671f	# Super I/O
-          device pnp 370.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 370.1 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 370.2 on		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 370.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 370.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 370.6 on           # PS/2 mouse
-            irq 0x70 = 12
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb b/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb
deleted file mode 100644
index 61b24fc..0000000
--- a/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb
+++ /dev/null
@@ -1,96 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-end
diff --git a/src/mainboard/sunw/ultra40/Config.lb b/src/mainboard/sunw/ultra40/Config.lb
deleted file mode 100644
index 2781be8..0000000
--- a/src/mainboard/sunw/ultra40/Config.lb
+++ /dev/null
@@ -1,256 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_ROM_PAYLOAD = 1
-
-arch i386 end 
-
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-	if CONFIG_USE_INIT	
-		makerule ./auto.o
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./auto.inc
-        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for CK804
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit southbridge/nvidia/ck804/romstrap.inc
-	ldscript /southbridge/nvidia/ck804/romstrap.lds
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for tyan/s2895
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on end # link 0
-			device pci 18.0 on # link1 
-				#  devices on link 0, link 0 == LDT 0 
-			        chip southbridge/nvidia/ck804 
-					device pci 0.0 on end   # HT
-                			device pci 1.0 on # LPC
-                	                        chip superio/smsc/lpc47m10x
-                        	                        device pnp 2e.0 off #  Floppy
-                                	                         io 0x60 = 0x3f0
-                                        	                irq 0x70 = 6
-                                                	        drq 0x74 = 2
-	                                                end
-        	                                        device pnp 2e.3 off #  Parallel Port
-                	                                         io 0x60 = 0x378
-                        	                                irq 0x70 = 7
-                                	                end
-                                        	        device pnp 2e.4 on #  Com1
-                                                	        io 0x60 = 0x3f8
-	                                                        irq 0x70 = 4
-        	                                        end
-                	                                device pnp 2e.5 off #  Com2
-                        	                                io 0x60 = 0x2f8
-                                	                        irq 0x70 = 3
-                                        	        end
-	                                                device pnp 2e.7 off #  Keyboard
-        	                                                io 0x60 = 0x60
-                	                                        io 0x62 = 0x64
-                        	                                irq 0x70 = 1
-                                	                        irq 0x72 = 12
-                                        	        end
-                        	                end
-					end
-			                device pci 1.1 on # SM 0
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end  
-                                                end              
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
-                                                end             
-                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
-                                                end              
-                                                chip drivers/generic/generic #dimm 1-0-0
-                                                        device i2c 54 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-0-1
-                                                        device i2c 55 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-0
-                                                        device i2c 56 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-1
-                                                        device i2c 57 on end
-                                                end 
-					end # SM
-                                        device pci 1.1 on # SM 1
-#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#                                                chip drivers/generic/generic #PCIXA Slot1
-#                                                        device i2c 50 on end
-#                                                end
-#                                                chip drivers/generic/generic #PCIXB Slot1
-#                                                        device i2c 51 on end
-#                                                end     
-#                                                chip drivers/generic/generic #PCIXB Slot2
-#                                                        device i2c 52 on end
-#                                                end             
-#                                                chip drivers/generic/generic #PCI Slot1
-#                                                        device i2c 53 on end
-#                                                end              
-#                                                chip drivers/generic/generic #Master CK804 PCI-E
-#                                                        device i2c 54 on end
-#                                                end     
-#                                                chip drivers/generic/generic #Slave CK804 PCI-E
-#                                                        device i2c 55 on end
-#                                                end             
-                                                chip drivers/generic/generic #MAC EEPROM
-                                                        device i2c 51 on end
-                                                end 
-
-                                        end # SM 
-	                		device pci 2.0 on end # USB 1.1
-        	        		device pci 2.1 on end # USB 2
-	                		device pci 4.0 on end # ACI
-        	        		device pci 4.1 off end # MCI
-                			device pci 6.0 on end # IDE
-	                		device pci 7.0 on end # SATA 1
-        	        		device pci 8.0 on end # SATA 0
-                			device pci 9.0 on end # PCI
-	                		device pci a.0 on end # NIC
-        	       			device pci b.0 off end # PCI E 3
-                			device pci c.0 off end # PCI E 2
-                			device pci d.0 off end # PCI E 1
-                			device pci e.0 on end # PCI E 0
-	                                register "ide0_enable" = "1"
-        	                        register "ide1_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
-					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end #  device pci 18.0 
-			device pci 18.0 on end # link 2
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end # mc0
-		
-		chip northbridge/amd/amdk8
-                	device pci 19.0 on end # link 0
-		device pci 19.0 on   
-                        	#  devices on link 1, link 1 == LDT 1
-                        	chip southbridge/nvidia/ck804 
-                                	device pci 0.0 on end   # HT
-                                	device pci 1.0 on end   # LPC
-                                	device pci 1.1 off end # SM
-                                	device pci 2.0 off end # USB 1.1
-                                	device pci 2.1 off end # USB 2
-                                	device pci 4.0 off end # ACI
-                                	device pci 4.1 off end # MCI
-                                	device pci 6.0 off end # IDE
-                                	device pci 7.0 off end # SATA 1
-                                	device pci 8.0 off end # SATA 0
-                                	device pci 9.0 off end # PCI
-                                	device pci a.0 on end # NIC
-                                	device pci b.0 off end # PCI E 3
-                                	device pci c.0 off end # PCI E 2
-                                	device pci d.0 off end # PCI E 1
-                                	device pci e.0 on end # PCI E 0
-                                        register "mac_eeprom_smbus" = "3"
-                                        register "mac_eeprom_addr" = "0x51"
-                        	end
-                	end #  device pci 19.0 
-			
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-		end
-	end # PCI domain
-	
-end #root_complex
diff --git a/src/mainboard/sunw/ultra40/Options.lb b/src/mainboard/sunw/ultra40/Options.lb
deleted file mode 100644
index e820fd0..0000000
--- a/src/mainboard/sunw/ultra40/Options.lb
+++ /dev/null
@@ -1,280 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID 
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_ID_SECTION_OFFSET
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-#512K bytes 
-#default CONFIG_ROM_SIZE=524288
-
-#1M bytes
-default CONFIG_ROM_SIZE=1048576
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-##HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-##real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-##only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#VGA
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=1
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=0
-
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="ultra40"
-default CONFIG_MAINBOARD_VENDOR="sunw"
-
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x108e
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/supermicro/h8dme/Config.lb b/src/mainboard/supermicro/h8dme/Config.lb
deleted file mode 100644
index 18cde51..0000000
--- a/src/mainboard/supermicro/h8dme/Config.lb
+++ /dev/null
@@ -1,301 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	if CONFIG_USE_INIT	
-		makerule ./auto.o
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./auto.inc
-        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-        makerule ./apc_auto.o
-                depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-                action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-        end
-        ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_F
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.0 on 
-				#  devices on link 0, link 0 == LDT 0 
-			        chip southbridge/nvidia/mcp55 
-					device pci 0.0 on end   # HT
-                			device pci 1.0 on # LPC
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 off #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	        			device pnp 2e.6 off  # SFI 
-                	                 			io 0x62 = 0x100
-							end
-                	        			device pnp 2e.7 off #  GPIO_GAME_MIDI
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end						
-                	        			device pnp 2e.8 off end #  WDTO_PLED
-                	        			device pnp 2e.9 off end #  GPIO_SUSLED
-                	        			device pnp 2e.a off end #  ACPI
-                	        			device pnp 2e.b on #  HW Monitor
- 					 			io 0x60 = 0x290
-								irq 0x70 = 5
-                					end
-						end
-					end
-			                device pci 1.1 on # SM 0
-						chip drivers/i2c/i2cmux2
-							device i2c 48 off end
-							device i2c 49 off end
-						end
-					end # SM
-                                        device pci 1.1 on # SM 1
-#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#                                                chip drivers/generic/generic #PCIXA Slot1
-#                                                        device i2c 50 on end
-#                                                end
-#                                                chip drivers/generic/generic #PCIXB Slot1
-#                                                        device i2c 51 on end
-#                                                end     
-#                                                chip drivers/generic/generic #PCIXB Slot2
-#                                                        device i2c 52 on end
-#                                                end             
-#                                                chip drivers/generic/generic #PCI Slot1
-#                                                        device i2c 53 on end
-#                                                end              
-#                                                chip drivers/generic/generic #Master MCP55 PCI-E
-#                                                        device i2c 54 on end
-#                                                end     
-#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
-#                                                        device i2c 55 on end
-#                                                end             
-                                                chip drivers/generic/generic #MAC EEPROM
-                                                        device i2c 51 on end
-                                                end
-
-                                        end # SM 
-	                		device pci 2.0 on end # USB 1.1
-        	        		device pci 2.1 on end # USB 2
-                			device pci 4.0 on end # IDE
-	                		device pci 5.0 on end # SATA 0
-	                		device pci 5.1 on end # SATA 1
-	                		device pci 5.2 on end # SATA 2
-                			device pci 6.0 on  # PCI
-                                                device pci 6.0 on end
-					end
-        	        		device pci 6.1 on end # AZA
-	                		device pci 8.0 on end # NIC
-	                		device pci 9.0 on end # NIC
-        	       			device pci a.0 on  # PCI E 5
-						device pci 0.0 on #nec pci-x
-						end
-						device pci 0.1 on #nec pci-x
-							device pci 4.0 on end #scsi
-							device pci 4.1 on end #scsi
-						end
-					end
-        	       			device pci b.0 on end # PCI E 4
-                			device pci c.0 on end # PCI E 3
-                			device pci d.0 on end # PCI E 2
-                			device pci e.0 on end # PCI E 1
-        	       			device pci f.0 on end # PCI E 0
-	                                register "ide0_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
-					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end #  device pci 18.0 
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end # mc0
-		
-	end # PCI domain
-	
-#       chip drivers/generic/debug 
-#               device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 on end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#                device pnp 0.7 off end # tsc
-#                device pnp 0.8 off  end # io
-#                device pnp 0.9 on end # io
-#       end  
-end #root_complex
diff --git a/src/mainboard/supermicro/h8dme/Options.lb b/src/mainboard/supermicro/h8dme/Options.lb
deleted file mode 100644
index 85d8331..0000000
--- a/src/mainboard/supermicro/h8dme/Options.lb
+++ /dev/null
@@ -1,355 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_HAVE_LOW_TABLES
-uses CONFIG_MULTIBOOT
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ID_SECTION_OFFSET
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-#default CONFIG_ROM_SIZE=524288
-default CONFIG_ROM_SIZE=0x100000
-
-default CONFIG_HAVE_LOW_TABLES = 0
-default CONFIG_MULTIBOOT=0
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-#FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#FAILOVER: 4K
-default CONFIG_FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=0
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default CONFIG_HT_CHAIN_UNITID_BASE=0
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_AP_CODE_IN_CAR=1
-default CONFIG_MEM_TRAIN_SEQ=1
-default CONFIG_WAIT_BEFORE_CPUS_INIT=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="h8dme"
-default CONFIG_MAINBOARD_VENDOR="Supermicro"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-#default CONFIG_COMPRESSED_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/supermicro/h8dmr/Config.lb b/src/mainboard/supermicro/h8dmr/Config.lb
deleted file mode 100644
index 13db09a..0000000
--- a/src/mainboard/supermicro/h8dmr/Config.lb
+++ /dev/null
@@ -1,323 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	if CONFIG_USE_INIT	
-		makerule ./auto.o
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./auto.inc
-        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-        makerule ./apc_auto.o
-                depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-                action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-        end
-    end
-end
-
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_F
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.0 on 
-				#  devices on link 0, link 0 == LDT 0 
-			        chip southbridge/nvidia/mcp55 
-					device pci 0.0 on end   # HT
-                			device pci 1.0 on # LPC
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 off #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	        			device pnp 2e.6 off  # SFI 
-                	                 			io 0x62 = 0x100
-							end
-                	        			device pnp 2e.7 off #  GPIO_GAME_MIDI
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end						
-                	        			device pnp 2e.8 off end #  WDTO_PLED
-                	        			device pnp 2e.9 off end #  GPIO_SUSLED
-                	        			device pnp 2e.a off end #  ACPI
-                	        			device pnp 2e.b on #  HW Monitor
- 					 			io 0x60 = 0x290
-								irq 0x70 = 5
-                					end
-						end
-					end
-			                device pci 1.1 on # SM 0
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end  
-                                                end              
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
-                                                end             
-                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
-                                                end              
-                                                chip drivers/generic/generic #dimm 1-0-0
-                                                        device i2c 54 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-0-1
-                                                        device i2c 55 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-0
-                                                        device i2c 56 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-1
-                                                        device i2c 57 on end
-                                                end 
-					end # SM
-                                        device pci 1.1 on # SM 1
-#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#                                                chip drivers/generic/generic #PCIXA Slot1
-#                                                        device i2c 50 on end
-#                                                end
-#                                                chip drivers/generic/generic #PCIXB Slot1
-#                                                        device i2c 51 on end
-#                                                end     
-#                                                chip drivers/generic/generic #PCIXB Slot2
-#                                                        device i2c 52 on end
-#                                                end             
-#                                                chip drivers/generic/generic #PCI Slot1
-#                                                        device i2c 53 on end
-#                                                end              
-#                                                chip drivers/generic/generic #Master MCP55 PCI-E
-#                                                        device i2c 54 on end
-#                                                end     
-#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
-#                                                        device i2c 55 on end
-#                                                end             
-                                                chip drivers/generic/generic #MAC EEPROM
-                                                        device i2c 51 on end
-                                                end 
-
-                                        end # SM 
-	                		device pci 2.0 on end # USB 1.1
-        	        		device pci 2.1 on end # USB 2
-                			device pci 4.0 on end # IDE
-	                		device pci 5.0 on end # SATA 0
-	                		device pci 5.1 on end # SATA 1
-	                		device pci 5.2 on end # SATA 2
-                			device pci 6.0 on  # PCI
-                                                device pci 6.0 on end
-					end
-        	        		device pci 6.1 on end # AZA
-	                		device pci 8.0 on end # NIC
-	                		device pci 9.0 on end # NIC
-        	       			device pci a.0 on  # PCI E 5
-						device pci 0.0 on #nec pci-x
-						end
-						device pci 0.1 on #nec pci-x
-							device pci 4.0 on end #scsi
-							device pci 4.1 on end #scsi
-						end
-					end
-        	       			device pci b.0 on end # PCI E 4
-                			device pci c.0 on end # PCI E 3
-                			device pci d.0 on end # PCI E 2
-                			device pci e.0 on end # PCI E 1
-        	       			device pci f.0 on end # PCI E 0
-	                                register "ide0_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
-					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end #  device pci 18.0 
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end # mc0
-		
-	end # PCI domain
-	
-#       chip drivers/generic/debug 
-#               device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 on end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#                device pnp 0.7 off end # tsc
-#                device pnp 0.8 off  end # io
-#                device pnp 0.9 on end # io
-#       end  
-end #root_complex
diff --git a/src/mainboard/supermicro/h8dmr/Options.lb b/src/mainboard/supermicro/h8dmr/Options.lb
deleted file mode 100644
index f0e9082..0000000
--- a/src/mainboard/supermicro/h8dmr/Options.lb
+++ /dev/null
@@ -1,353 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ID_SECTION_OFFSET
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-#default CONFIG_ROM_SIZE=524288
-default CONFIG_ROM_SIZE=0x100000
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use
-##
-default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
-#FAILOVER: 4K
-default CONFIG_FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=0
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default CONFIG_HT_CHAIN_UNITID_BASE=0
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_AP_CODE_IN_CAR=0
-default CONFIG_MEM_TRAIN_SEQ=1
-default CONFIG_WAIT_BEFORE_CPUS_INIT=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="h8dmr"
-default CONFIG_MAINBOARD_VENDOR="Supermicro"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 0xf000
-
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-#default CONFIG_COMPRESSED_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_USE_FAILOVER_IMAGE=0
-default CONFIG_USE_FALLBACK_IMAGE=0
-default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Config.lb b/src/mainboard/supermicro/h8dmr_fam10/Config.lb
deleted file mode 100644
index fe2d1b6..0000000
--- a/src/mainboard/supermicro/h8dmr_fam10/Config.lb
+++ /dev/null
@@ -1,333 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-# for testing with -O != s. FIXME
-#default CONFIG_XIP_ROM_SIZE = 128 * 1024
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	if CONFIG_USE_INIT	
-		makerule ./auto.o
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./auto.inc
-        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-        makerule ./apc_auto.o
-                depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-                action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-        end
-    end
-end
-
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-dir /southbridge/nvidia/mcp55
-
-chip northbridge/amd/amdfam10/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_F_1207
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdfam10 #mc0
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.0 on 
-        # SB on link 2.0
-			        chip southbridge/nvidia/mcp55 
-					device pci 0.0 on end   # HT
-                			device pci 1.0 on # LPC
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 off #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 on #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	        			device pnp 2e.6 off  # SFI 
-                	                 			io 0x62 = 0x100
-							end
-                	        			device pnp 2e.7 off #  GPIO_GAME_MIDI
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end						
-                	        			device pnp 2e.8 off end #  WDTO_PLED
-                	        			device pnp 2e.9 off end #  GPIO_SUSLED
-                	        			device pnp 2e.a off end #  ACPI
-                	        			device pnp 2e.b on #  HW Monitor
- 					 			io 0x60 = 0x290
-								irq 0x70 = 5
-                					end
-						end
-					end
-			                device pci 1.1 on # SM 0
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end  
-                                                end              
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
-                                                end             
-                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
-                                                end              
-                                                chip drivers/generic/generic #dimm 1-0-0
-                                                        device i2c 54 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-0-1
-                                                        device i2c 55 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-0
-                                                        device i2c 56 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-1
-                                                        device i2c 57 on end
-                                                end 
-					end # SM
-                                        device pci 1.1 on # SM 1
-#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#                                                chip drivers/generic/generic #PCIXA Slot1
-#                                                        device i2c 50 on end
-#                                                end
-#                                                chip drivers/generic/generic #PCIXB Slot1
-#                                                        device i2c 51 on end
-#                                                end     
-#                                                chip drivers/generic/generic #PCIXB Slot2
-#                                                        device i2c 52 on end
-#                                                end             
-#                                                chip drivers/generic/generic #PCI Slot1
-#                                                        device i2c 53 on end
-#                                                end              
-#                                                chip drivers/generic/generic #Master MCP55 PCI-E
-#                                                        device i2c 54 on end
-#                                                end     
-#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
-#                                                        device i2c 55 on end
-#                                                end             
-                                                chip drivers/generic/generic #MAC EEPROM
-                                                        device i2c 51 on end
-                                                end 
-
-                                        end # SM 
-	                		device pci 2.0 on end # USB 1.1
-        	        		device pci 2.1 on end # USB 2
-                			device pci 4.0 on end # IDE
-	                		device pci 5.0 on end # SATA 0
-	                		device pci 5.1 on end # SATA 1
-	                		device pci 5.2 on end # SATA 2
-                			device pci 6.0 on  # PCI
-                                                device pci 6.0 on end
-					end
-        	        		device pci 6.1 on end # AZA
-	                		device pci 8.0 on end # NIC
-	                		device pci 9.0 on end # NIC
-        	       			device pci a.0 on  # PCI E 5
-						device pci 0.0 on #nec pci-x
-						end
-						device pci 0.1 on #nec pci-x
-							device pci 4.0 on end #scsi
-							device pci 4.1 on end #scsi
-						end
-					end
-        	       			device pci b.0 on end # PCI E 4
-                			device pci c.0 on end # PCI E 3
-                			device pci d.0 on end # PCI E 2
-                			device pci e.0 on end # PCI E 1
-        	       			device pci f.0 on end # PCI E 0
-	                                register "ide0_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
-					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end #  device pci 18.0 
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-			device pci 19.4 on end
-		end # mc0
-		
-	end # PCI domain
-	
-#       chip drivers/generic/debug 
-#               device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 on end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#                device pnp 0.7 off end # tsc
-#                device pnp 0.8 off  end # io
-#                device pnp 0.9 on end # io
-#       end  
-end #root_complex
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Options.lb b/src/mainboard/supermicro/h8dmr_fam10/Options.lb
deleted file mode 100644
index a7d3ca8..0000000
--- a/src/mainboard/supermicro/h8dmr_fam10/Options.lb
+++ /dev/null
@@ -1,363 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_UNCOMPRESSED
-
-uses CONFIG_PCI_BUS_SEGN_BITS
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_AMDMCT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_AMD_UCODE_PATCH_FILE
-uses CONFIG_ID_SECTION_OFFSET
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1024*1024
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use
-default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
-default CONFIG_FAILOVER_SIZE=0x02000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=16384*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=0
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS
-default CONFIG_LOGICAL_CPUS=1
-
-default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=1
-default CONFIG_APIC_ID_OFFSET=0x00
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default CONFIG_HT_CHAIN_UNITID_BASE=1
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc4000
-default CONFIG_DCACHE_RAM_SIZE=0x0c000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
-default CONFIG_USE_INIT=0
-
-default CONFIG_MEM_TRAIN_SEQ=2
-default CONFIG_WAIT_BEFORE_CPUS_INIT=0
-default CONFIG_AMDMCT = 1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="h8dmr (Fam10)"
-default CONFIG_MAINBOARD_VENDOR="Supermicro"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
-
-##
-## Set microcode patch file name
-##
-##      Barcelona rev Ax:  "mc_patch_01000020.h"
-##      Barcelona rev B0, B1, BA: "mc_patch_01000084.h"
-##      Barcelona rev B2, B3: "mc_patch_01000083.h"
-##			Shanghai rev RB-C2: "mc_patch_01000086.h"
-##			Shanghai rev DA-C2: "mc_patch_0100009f.h"
-##
-#default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000086.h"
-default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_0100009f.h"
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 0x1e000
-
-##
-## Use a 32K stack
-##
-default CONFIG_STACK_SIZE=0x8000
-
-##
-## Use a 48K heap
-##
-default CONFIG_HEAP_SIZE=0xc0000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00200000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-#default CONFIG_COMPRESSED_PAYLOAD = 1
-
-# CBFS will take care of payload compression
-default CONFIG_UNCOMPRESSED = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_USE_FAILOVER_IMAGE=0
-default CONFIG_USE_FALLBACK_IMAGE=0
-default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-### End Options.lb
-end
diff --git a/src/mainboard/supermicro/h8qme_fam10/Config.lb b/src/mainboard/supermicro/h8qme_fam10/Config.lb
deleted file mode 100644
index 863575b..0000000
--- a/src/mainboard/supermicro/h8qme_fam10/Config.lb
+++ /dev/null
@@ -1,347 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-# for testing with -O != s. FIXME
-#default CONFIG_XIP_ROM_SIZE = 128 * 1024
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	if CONFIG_USE_INIT	
-		makerule ./auto.o
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./auto.inc
-        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-        makerule ./apc_auto.o
-                depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-                action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-        end
-    end
-end
-
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-dir /southbridge/nvidia/mcp55
-dir /southbridge/amd/amd8132
-
-chip northbridge/amd/amdfam10/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_F_1207
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdfam10 #mc0
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.0 on 
-        # SB on link 2.0
-			        chip southbridge/nvidia/mcp55 
-					device pci 0.0 on end   # HT
-                			device pci 1.0 on # LPC
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 off #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-              device pnp 2e.1 off #  Parallel Port
-               			io 0x60 = 0x378
-               			irq 0x70 = 7
-							end
-              device pnp 2e.2 on #  Com1
-               			io 0x60 = 0x3f8
-               			irq 0x70 = 4
-							end
-              device pnp 2e.3 off #  Com2
-               			io 0x60 = 0x2f8
-               			irq 0x70 = 3
-							end
-              device pnp 2e.5 on #  Keyboard
-               			io 0x60 = 0x60
-               			io 0x62 = 0x64
-               			irq 0x70 = 1
-							      irq 0x72 = 12
-							end
-              device pnp 2e.6 off  # SFI 
-              			io 0x62 = 0x100
-							end
-              device pnp 2e.7 off #  GPIO_GAME_MIDI
-							    	io 0x60 = 0x220
-								    io 0x62 = 0x300
-								    irq 0x70 = 9
-							end						
-            	device pnp 2e.8 off end #  WDTO_PLED
-            	device pnp 2e.9 off end #  GPIO_SUSLED
-            	device pnp 2e.a off end #  ACPI
-            	device pnp 2e.b on #  HW Monitor
- 					 		    	io 0x60 = 0x290
-							     	irq 0x70 = 5
-              end
-						end
-					end
-			               device pci 1.1 on # SM 0
-                     #                          chip drivers/generic/generic #dimm 0-0-0
-                     #                                   device i2c 50 on end  
-                     #                           end              
-                     #                           chip drivers/generic/generic #dimm 0-0-1
-                     #                                   device i2c 51 on end
-                     #                           end     
-                     #                           chip drivers/generic/generic #dimm 0-1-0
-                     #                                   device i2c 52 on end
-                     #                           end             
-                     #                           chip drivers/generic/generic #dimm 0-1-1
-                     #                                   device i2c 53 on end
-                     #                           end              
-                     #                           chip drivers/generic/generic #dimm 1-0-0
-                     #                                   device i2c 54 on end
-                     #                           end     
-                     #                           chip drivers/generic/generic #dimm 1-0-1
-                     #                                   device i2c 55 on end
-                     #                           end     
-                     #                           chip drivers/generic/generic #dimm 1-1-0
-                     #                                   device i2c 56 on end
-                     #                           end     
-                     #                           chip drivers/generic/generic #dimm 1-1-1
-                     #                                   device i2c 57 on end
-                     #                           end
-										 #														chip drivers/generic/generic #dimm 2-0-0
-                     #                                    device i2c 58 on end
-                     #                            end
-                     #                            chip drivers/generic/generic #dimm 2-0-1
-                     #                                    device i2c 59 on end
-                     #                            end
-                     #                            chip drivers/generic/generic #dimm 2-1-0
-                     #                                    device i2c 5a on end
-                     #                            end
-                     #                            chip drivers/generic/generic #dimm 2-1-1
-                     #                                   device i2c 5b on end
-                     #                            end
-                     #                            chip drivers/generic/generic #dimm 3-0-0
-                     #                                    device i2c 5c on end
-                     #                            end
-                     #                            chip drivers/generic/generic #dimm 3-0-1
-                     #                                    device i2c 5d on end
-                     #                            end
-                     #                            chip drivers/generic/generic #dimm 3-1-0
-                     #                                    device i2c 5e on end
-                     #                            end
-                     #                            chip drivers/generic/generic #dimm 3-1-1
-                     #                                    device i2c 5f on end
-                     #                            end
-
-					end # SM
-                                        device pci 1.1 on # SM 1
-#PCI device smbus address will diepend on addon pci device, do we need to scan_smbus_bus?
-#                                                         
-                                                chip drivers/generic/generic #MAC EEPROM
-                                                        device i2c 51 on end
-                                                end 
-
-                                        end # SM 
-	                		device pci 2.0 on end # USB 1.1
-        	        		device pci 2.1 on end # USB 2
-                			device pci 4.0 on end # IDE
-	                		device pci 5.0 on end # SATA 0
-	                		device pci 5.1 on end # SATA 1
-	                		device pci 5.2 on end # SATA 2
-					device pci 6.1 off end # AZA
-					device pci 7.0 on
-						device pci 1.0 on end
-					end
-					device pci 8.0 off end
-					device pci 9.0 off end
-        	       			device pci a.0 on end # PCI E 5
-        	       			device pci b.0 on end # PCI E 4
-                			device pci c.0 on end # PCI E 3
-                			device pci d.0 on end # PCI E 2
-                			device pci e.0 on end # PCI E 1
-        	       			device pci f.0 on end # PCI E 0
-	                                register "ide0_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
-					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end #  device pci 18.0 
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.0 on
-				chip southbridge/amd/amd8132
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on
-						device pci 3.0 on end
-						device pci 3.1 on end
-					end
-					device pci 1.1 on end
-				end #amd8132
-			end #device pci 19.0
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-			device pci 19.4 on end
-		end # mc0
-		
-	end # PCI domain
-	
-#       chip drivers/generic/debug 
-#               device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 on end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#                device pnp 0.7 off end # tsc
-#                device pnp 0.8 off  end # io
-#                device pnp 0.9 on end # io
-#       end  
-end #root_complex
diff --git a/src/mainboard/supermicro/h8qme_fam10/Options.lb b/src/mainboard/supermicro/h8qme_fam10/Options.lb
deleted file mode 100644
index 279d8ac..0000000
--- a/src/mainboard/supermicro/h8qme_fam10/Options.lb
+++ /dev/null
@@ -1,373 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_VGA
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_VGA_ROM_RUN
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_UNCOMPRESSED
-
-uses CONFIG_PCI_BUS_SEGN_BITS
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_AMDMCT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_AMD_UCODE_PATCH_FILE
-uses CONFIG_ID_SECTION_OFFSET
-
-uses CONFIG_PIRQ_ROUTE
-
-default CONFIG_PIRQ_ROUTE = 1
-
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1024*1024
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use
-default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
-default CONFIG_FAILOVER_SIZE=0x02000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=16384*1024
-#default CONFIG_RAMTOP=16384*8192
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=0
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_PHYSICAL_CPUS=4
-default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS
-default CONFIG_LOGICAL_CPUS=1
-
-default CONFIG_SERIAL_CPU_INIT=1
-
-default CONFIG_ENABLE_APIC_EXT_ID=1
-default CONFIG_APIC_ID_OFFSET=0x00
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#VGA Console
-default CONFIG_VGA=0
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_VGA_ROM_RUN=1
-default CONFIG_PCI_ROM_RUN=0
-
-#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default CONFIG_HT_CHAIN_UNITID_BASE=1
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc4000
-default CONFIG_DCACHE_RAM_SIZE=0x0c000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
-default CONFIG_USE_INIT=0
-
-default CONFIG_MEM_TRAIN_SEQ=2
-default CONFIG_WAIT_BEFORE_CPUS_INIT=0
-default CONFIG_AMDMCT = 1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="h8qme (Fam10)"
-default CONFIG_MAINBOARD_VENDOR="Supermicro"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
-
-##
-## Set microcode patch file name
-##
-##      Barcelona rev Ax:  "mc_patch_01000020.h"
-##      Barcelona rev B0, B1, BA: "mc_patch_01000084.h"
-##      Barcelona rev B2, B3: "mc_patch_01000083.h"
-##			Shanghai rev RB-C2: "mc_patch_01000086.h"
-##			Shanghai rev DA-C2: "mc_patch_0100009f.h"
-##
-#default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000086.h"
-default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_0100009f.h"
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 0x1e000
-
-##
-## Use a 64K stack
-##
-default CONFIG_STACK_SIZE=0x10000
-
-##
-## Use a 48K heap
-##
-default CONFIG_HEAP_SIZE=0xc000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00200000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-#default CONFIG_COMPRESSED_PAYLOAD = 1
-
-# CBFS will take care of payload compression
-default CONFIG_UNCOMPRESSED = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-#default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_USE_FAILOVER_IMAGE=0
-default CONFIG_USE_FALLBACK_IMAGE=0
-default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-### End Options.lb
-end
diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb
deleted file mode 100644
index 17096f5..0000000
--- a/src/mainboard/supermicro/x6dai_g/Config.lb
+++ /dev/null
@@ -1,167 +0,0 @@
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_HARD_RESET object reset.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/e7525 # mch
-	device pci_domain 0 on
-		chip southbridge/intel/esb6300  # esb6300 
-			register "pirq_a_d" = "0x0b0a0a05"
-			register "pirq_e_h" = "0x0a0b0c80"
-		
-			device pci 1c.0 on end
-		
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.4 on end
-			device pci 1d.5 on end
-			device pci 1d.7 on end
-		
-			device pci 1e.0 on end
-		
-			device pci 1f.0 on 
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 off end
-					device pnp 2e.1 off end
-					device pnp 2e.2 on
-						 io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on
-						 io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.4 off end
-					device pnp 2e.5 off end
-					device pnp 2e.6 off end
-					device pnp 2e.7 off end
-					device pnp 2e.9 off end
-					device pnp 2e.a on  end
-					device pnp 2e.b off end
-					device pnp 2e.f off end
-					device pnp 2e.10 off end
-					device pnp 2e.14 off end
-				end
-			end
-			device pci 1f.1 on end
-			device pci 1f.2 on end
-			device pci 1f.3 on end
-			device pci 1f.5 off end
-			device pci 1f.6 on end
-		end
-		device pci 00.0 on end
-		device pci 00.1 on end 
-		device pci 00.2 on end
-		device pci 02.0 on end
-		device pci 03.0 on end
-		device pci 04.0 on end
-		device pci 08.0 on end
-	end
-	device apic_cluster 0 on
-		chip cpu/intel/socket_mPGA604 # cpu0
-			device apic 0 on end
-		end
-		chip cpu/intel/socket_mPGA604 # cpu1
-			device apic 6 on end
-		end
-	end
-end
-
diff --git a/src/mainboard/supermicro/x6dai_g/Options.lb b/src/mainboard/supermicro/x6dai_g/Options.lb
deleted file mode 100644
index 626f0be..0000000
--- a/src/mainboard/supermicro/x6dai_g/Options.lb
+++ /dev/null
@@ -1,228 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_BTEXT
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1048576
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## Use timer2
-## 
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=15
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_LOGICAL_CPUS=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="X6DAI"
-default CONFIG_MAINBOARD_VENDOR=     "Supermicro"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-##
-## Don't enable the btext console
-##
-default  CONFIG_CONSOLE_BTEXT=0
-
-
-### End Options.lb
-end
diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb
deleted file mode 100644
index 866042b..0000000
--- a/src/mainboard/supermicro/x6dhe_g/Config.lb
+++ /dev/null
@@ -1,190 +0,0 @@
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_HARD_RESET object reset.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-makerule ./auto.inc 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/e7520  # MCH
-	chip drivers/generic/debug  # DEBUGGING
-		device pnp 00.0 on end
-		device pnp 00.1 off end
-		device pnp 00.2 off end
-		device pnp 00.3 off end
-	end
-	device pci_domain 0 on
-		chip southbridge/intel/esb6300	# ESB6300
-			register "pirq_a_d" = "0x0b070a05"
-			register "pirq_e_h" = "0x0a808080"
-
-			device pci 1c.0 on 
-				chip drivers/generic/generic 
-					device pci 01.0 on end	# onboard gige1
-					device pci 02.0 on end 	# onboard gige2
-				end
-			end
-
-			# USB ports
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.4 on end	# Southbridge Watchdog timer
-			device pci 1d.5 on end	# Southbridge I/O apic1
-			device pci 1d.7 on end
-
-			# VGA / PCI 32-bit
-			device pci 1e.0 on 
-				chip drivers/generic/generic
-					device pci 01.0 on end 
-				end
-			end
-
-
-			device pci 1f.0 on 	# ISA bridge
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 off end
-					device pnp 2e.2 on 
-						 io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on
-						 io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.4 off end
-					device pnp 2e.5 off end
-					device pnp 2e.6 off end
-					device pnp 2e.7 off end
-					device pnp 2e.9 off end
-					device pnp 2e.a on end
-					device pnp 2e.b off end
-				end
-			end
-			device pci 1f.1 on end
-			device pci 1f.2 off end
-			device pci 1f.3	on end		# SMBus
-			device pci 1f.5 off end
-			device pci 1f.6 off end
-		end
-
-		device pci 00.0	on end	# Northbridge
-		device pci 00.1	on end  # Northbridge Error reporting
-		device pci 01.0 on end
-		device pci 02.0 on 
-			chip southbridge/intel/pxhd	# PXHD 6700 
-				device pci 00.0 on end   # bridge 
-				device pci 00.1 on end   # I/O apic
-				device pci 00.2 on end   # bridge
-				device pci 00.3 on end   # I/O apic
-			end
-		end
-#	 	device register "intrline" = "0x00070105" 
-		device 	pci 04.0 on end	
-		device 	pci 06.0 on end	
-	end
-
-	device apic_cluster 0 on
-		chip cpu/intel/socket_mPGA604  	# CPU 0
-			device apic 0 on end
-		end
-		chip cpu/intel/socket_mPGA604 	# CPU 1
-			device apic 6 on end
-		end
-	end
-end
diff --git a/src/mainboard/supermicro/x6dhe_g/Options.lb b/src/mainboard/supermicro/x6dhe_g/Options.lb
deleted file mode 100644
index 87be848..0000000
--- a/src/mainboard/supermicro/x6dhe_g/Options.lb
+++ /dev/null
@@ -1,228 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_BTEXT
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1048576
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## Use timer2
-## 
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=15
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_LOGICAL_CPUS=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="X6DHE_g"
-default CONFIG_MAINBOARD_VENDOR=     "Supermicro"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-##
-## Don't enable the btext console
-##
-default  CONFIG_CONSOLE_BTEXT=0
-
-
-### End Options.lb
-end
diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb
deleted file mode 100644
index 11569d9..0000000
--- a/src/mainboard/supermicro/x6dhe_g2/Config.lb
+++ /dev/null
@@ -1,190 +0,0 @@
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_HARD_RESET object reset.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-makerule ./auto.inc 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/e7520  # MCH
-	chip drivers/generic/debug  # DEBUGGING
-		device pnp 00.0 off end
-		device pnp 00.1 off end
-		device pnp 00.2 off end
-		device pnp 00.3 off end
-	end
-	device pci_domain 0 on
-		chip southbridge/intel/i82801er	# ICH5R 
-			register "pirq_a_d" = "0x0b070a05"
-			register "pirq_e_h" = "0x0a808080"
-
-			device pci 1c.0 on 
-				chip drivers/generic/generic 
-					device pci 01.0 on end	# onboard gige1
-					device pci 02.0 on end 	# onboard gige2
-				end
-			end
-
-			# USB ports
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.4 on end	# Southbridge Watchdog timer
-			device pci 1d.5 on end	# Southbridge I/O apic1
-			device pci 1d.7 on end
-
-			# VGA / PCI 32-bit
-			device pci 1e.0 on 
-				chip drivers/generic/generic
-					device pci 01.0 on end 
-				end
-			end
-
-
-			device pci 1f.0 on 	# ISA bridge
-				chip superio/nsc/pc87427
-					device pnp 2e.0 off end
-					device pnp 2e.2 on 
-						 io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on
-						 io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.4 off end
-					device pnp 2e.5 off end
-					device pnp 2e.6 off end
-					device pnp 2e.7 off end
-					device pnp 2e.9 off end
-					device pnp 2e.a on end
-					device pnp 2e.b off end
-				end
-			end
-			device pci 1f.1 on end
-			device pci 1f.2 on end
-			device pci 1f.3	on end		# SMBus
-			device pci 1f.5 off end
-			device pci 1f.6 off end
-		end
-
-		device pci 00.0	on end	# Northbridge
-		device pci 00.1	on end  # Northbridge Error reporting
-		device pci 01.0 on end
-		device pci 02.0 on 
-			chip southbridge/intel/pxhd	# PXHD 6700 
-				device pci 00.0 on end   # bridge 
-				device pci 00.1 on end   # I/O apic
-				device pci 00.2 on end   # bridge
-				device pci 00.3 on end   # I/O apic
-			end
-		end
-#	 	device register "intrline" = "0x00070105" 
-		device 	pci 04.0 on end	
-		device 	pci 06.0 on end	
-	end
-
-	device apic_cluster 0 on
-		chip cpu/intel/socket_mPGA604  	# CPU 0
-			device apic 0 on end
-		end
-		chip cpu/intel/socket_mPGA604 	# CPU 1
-			device apic 6 on end
-		end
-	end
-end
diff --git a/src/mainboard/supermicro/x6dhe_g2/Options.lb b/src/mainboard/supermicro/x6dhe_g2/Options.lb
deleted file mode 100644
index 87be848..0000000
--- a/src/mainboard/supermicro/x6dhe_g2/Options.lb
+++ /dev/null
@@ -1,228 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_BTEXT
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1048576
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## Use timer2
-## 
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=15
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_LOGICAL_CPUS=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="X6DHE_g"
-default CONFIG_MAINBOARD_VENDOR=     "Supermicro"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-##
-## Don't enable the btext console
-##
-default  CONFIG_CONSOLE_BTEXT=0
-
-
-### End Options.lb
-end
diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb
deleted file mode 100644
index dc2dd12..0000000
--- a/src/mainboard/supermicro/x6dhr_ig/Config.lb
+++ /dev/null
@@ -1,187 +0,0 @@
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_HARD_RESET object reset.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/e7520 # mch
-	device pci_domain 0 on 
-		chip southbridge/intel/i82801er # i82801er
-			# USB ports
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.2 on end 
-			device pci 1d.3 on end
-			device pci 1d.7 on end
-		
-			# -> VGA
-			device pci 1e.0 on end
-		
-			# -> IDE
-			device pci 1f.0 on 
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 off end
-					device pnp 2e.2 on 
-						 io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on
-						 io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.4 off end
-					device pnp 2e.5 off end
-					device pnp 2e.6 off end
-					device pnp 2e.7 off end
-					device pnp 2e.9 off end
-					device pnp 2e.a on  end
-					device pnp 2e.b off end
-				end
-			end
-			device pci 1f.1 on end
-			device pci 1f.2 on end
-			device pci 1f.3 on end
-
-			register "pirq_a_d" = "0x0b070a05"
-			register "pirq_e_h" = "0x0a808080"
-		end
-		device pci 00.0 on end 
-		device pci 00.1  on end
-		device pci 01.0 on end 
-		device pci 02.0 on end 
-		device pci 03.0 on 
-			chip southbridge/intel/pxhd # pxhd1
-				# Bus bridges and ioapics usually bus 2
-				device pci 0.0 on end
-				device pci 0.1 on end
-				device pci 0.2 on 
-				# On board gig e1000
-					chip drivers/generic/generic 
-        		        	        device pci 02.0 on end
-        		        	        device pci 02.1 on end
-        		        	end
-				end
-				device pci 0.3 on end
-			end
-		end
-		device pci 04.0 on 
-			chip southbridge/intel/pxhd # pxhd2
-				# Bus bridges and ioapics usually bus 5
-				device pci 0.0 on end
-				# Slot 6  is usually 6:2.0
-				device pci 0.1 on end
-				device pci 0.2 on end
-				# Slot 7 is usually 7:2.0
-				device pci 0.3 on end
-			end
-		end
-		device pci 06.0 on end
-	end
-	device apic_cluster 0 on
-		chip cpu/intel/socket_mPGA604 # cpu 0
-			device apic 0 on end
-		end
-		chip cpu/intel/socket_mPGA604 # cpu 1
-			device apic 6 on end
-		end
-	end
-	register "intrline" = "0x00070105"
-end
-
diff --git a/src/mainboard/supermicro/x6dhr_ig/Options.lb b/src/mainboard/supermicro/x6dhr_ig/Options.lb
deleted file mode 100644
index d8b836b..0000000
--- a/src/mainboard/supermicro/x6dhr_ig/Options.lb
+++ /dev/null
@@ -1,228 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_BTEXT
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1048576
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## Use timer2
-## 
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=15
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_LOGICAL_CPUS=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="X6DHR"
-default CONFIG_MAINBOARD_VENDOR=     "Supermicro"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-##
-## Don't enable the btext console
-##
-default  CONFIG_CONSOLE_BTEXT=0
-
-
-### End Options.lb
-end
diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb
deleted file mode 100644
index 9e8ce14..0000000
--- a/src/mainboard/supermicro/x6dhr_ig2/Config.lb
+++ /dev/null
@@ -1,178 +0,0 @@
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_HARD_RESET object reset.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/e7520 # mch
-	device pci_domain 0 on 
-		chip southbridge/intel/i82801er # i82801er
-			# USB ports
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.2 on end 
-			device pci 1d.3 on end
-			device pci 1d.7 on end
-		
-			# -> Bridge
-			device pci 1e.0 on end
-		
-			# -> ISA
-			device pci 1f.0 on 
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 off end
-					device pnp 2e.2 on 
-						 io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on
-						 io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.4 off end
-					device pnp 2e.5 off end
-					device pnp 2e.6 off end
-					device pnp 2e.7 off end
-					device pnp 2e.9 off end
-					device pnp 2e.a on  end
-					device pnp 2e.b off end
-				end
-			end
-			# -> IDE
-			device pci 1f.1 on end
-			# -> SATA 
-			device pci 1f.2 on end
-			device pci 1f.3 on end
-
-			register "pirq_a_d" = "0x0b070a05"
-			register "pirq_e_h" = "0x0a808080"
-		end
-		device pci 00.0 on end 
-		device pci 00.1 on end
-		device pci 01.0 on end 
-		device pci 02.0 on 
-			chip southbridge/intel/pxhd # pxhd1
-				# Bus bridges and ioapics usually bus 1
-				device pci 0.0 on 
-				# On board gig e1000
-					chip drivers/generic/generic 
-        		        	        device pci 03.0 on end
-        		        	        device pci 03.1 on end
-        		        	end
-				end
-				device pci 0.1 on end
-				device pci 0.2 on end
-				device pci 0.3 on end
-			end
-		end
-		device pci 04.0 on end
-		device pci 06.0 on end
-	end
-	device apic_cluster 0 on
-		chip cpu/intel/socket_mPGA604 # cpu 0
-			device apic 0 on end
-		end
-		chip cpu/intel/socket_mPGA604 # cpu 1
-			device apic 6 on end
-		end
-	end
-	register "intrline" = "0x00070105"
-end
-
diff --git a/src/mainboard/supermicro/x6dhr_ig2/Options.lb b/src/mainboard/supermicro/x6dhr_ig2/Options.lb
deleted file mode 100644
index d8b836b..0000000
--- a/src/mainboard/supermicro/x6dhr_ig2/Options.lb
+++ /dev/null
@@ -1,228 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_BTEXT
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1048576
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## Use timer2
-## 
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=15
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_LOGICAL_CPUS=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="X6DHR"
-default CONFIG_MAINBOARD_VENDOR=     "Supermicro"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-##
-## Don't enable the btext console
-##
-default  CONFIG_CONSOLE_BTEXT=0
-
-
-### End Options.lb
-end
diff --git a/src/mainboard/technexion/tim5690/Config.lb b/src/mainboard/technexion/tim5690/Config.lb
deleted file mode 100644
index 619e76e..0000000
--- a/src/mainboard/technexion/tim5690/Config.lb
+++ /dev/null
@@ -1,261 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-object vgabios.o
-object tn_post_code.o
-object speaker.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE
-	object get_bus_conf.o
-	object irq_tables.o
-end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object acpi_tables.o
-	object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-	if CONFIG_USE_INIT
-
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else
-
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript      /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-#The variables belong to mainboard are defined here.
-
-#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_S1G1
-		device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  southbridge
-				chip southbridge/amd/rs690
-					device pci 0.0 on end # HT  	0x7910
-					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						device pci 5.0 on end	# Internal Graphics 0x791F
-					end
-					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
-					device pci 3.0 off end # PCIE P2P bridge	0x791b
-					device pci 4.0 on end # PCIE P2P bridge 0x7914
-					device pci 5.0 on end # PCIE P2P bridge 0x7915
-					device pci 6.0 on end # PCIE P2P bridge 0x7916
-					device pci 7.0 on end # PCIE P2P bridge 0x7917
-					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "gpp_configuration" = "4"
-					register "port_enable" = "0xfc"
-					register "gfx_dev2_dev3" = "1"
-					register "gfx_dual_slot" = "0"
-					register "gfx_lane_reversal" = "0"
-					register "gfx_tmds" = "1"
-					register "gfx_compliance" = "0"
-					register "gfx_reconfiguration" = "0"
-					register "gfx_link_width" = "0"
-				end
-				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
-					device pci 12.0 on end # SATA  0x4380
-					device pci 13.0 on end # USB   0x4387
-					device pci 13.1 on end # USB   0x4388
-					device pci 13.2 on end # USB   0x4389
-					device pci 13.3 on end # USB   0x438a
-					device pci 13.4 on end # USB   0x438b
-					device pci 13.5 on end # USB 2 0x4386
-	 				device pci 14.0 on # SM        0x4385
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end
-					end # SM
-					device pci 14.1 on end # IDE    0x438c
-					device pci 14.2 on end # HDA    0x4383
-					device pci 14.3 on # LPC	0x438d
-						chip superio/ite/it8712f
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.2 on #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.3 on #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.4 off end #  EC
-							device pnp 2e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 2e.6 on #  Mouse
-								irq 0x70 = 12
-							end
-							device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
-							end
-							device pnp 2e.8 off #  MIDI
-								io 0x60 = 0x300
-								irq 0x70 = 9
-							end
-							device pnp 2e.9 off #  GAME
-								io 0x60 = 0x220
-							end
-							device pnp 2e.a off end #  CIR
-						end	#superio/ite/it8712f
-					end		#LPC
-					device pci 14.4 on end # PCI 0x4384
-					device pci 14.5 on end # ACI 0x4382
-					device pci 14.6 on end # MCI 0x438e
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "hda_viddid" = "0x10ec0882"
-				end	#southbridge/amd/sb600
-			end #  device pci 18.0
-
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end		#northbridge/amd/amdk8
-	end #pci_domain
-end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/technexion/tim5690/Options.lb b/src/mainboard/technexion/tim5690/Options.lb
deleted file mode 100644
index 774baaf..0000000
--- a/src/mainboard/technexion/tim5690/Options.lb
+++ /dev/null
@@ -1,303 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_VIDEO_MB
-uses CONFIG_GFXUMA
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-uses CONFIG_VGA_ROM_RUN
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1
-default CONFIG_VGA_ROM_RUN=1
-
-# BTDC: Only one HT device on Herring.
-#HT Unit ID offset
-#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-
-#real SB Unit ID
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
-
-#make the SB HT chain on bus 0
-default CONFIG_SB_HT_CHAIN_ON_BUS0=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="tim5690"
-default CONFIG_MAINBOARD_VENDOR="technexion"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
-
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_VIDEO_MB=1
-default CONFIG_GFXUMA=1
-default CONFIG_HAVE_MAINBOARD_RESOURCES=1
-
-### End Options.lb
-end
diff --git a/src/mainboard/technexion/tim8690/Config.lb b/src/mainboard/technexion/tim8690/Config.lb
deleted file mode 100644
index fde48a1..0000000
--- a/src/mainboard/technexion/tim8690/Config.lb
+++ /dev/null
@@ -1,258 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE
-	object get_bus_conf.o
-	object irq_tables.o
-end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object acpi_tables.o
-	object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-	if CONFIG_USE_INIT
-
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else
-
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript      /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-#The variables belong to mainboard are defined here.
-
-#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_S1G1
-		device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  southbridge
-				chip southbridge/amd/rs690
-					device pci 0.0 on end # HT  	0x7910
-					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						device pci 5.0 on end	# Internal Graphics 0x791F
-					end
-					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
-					device pci 3.0 off end # PCIE P2P bridge	0x791b
-					device pci 4.0 on end # PCIE P2P bridge 0x7914
-					device pci 5.0 on end # PCIE P2P bridge 0x7915
-					device pci 6.0 on end # PCIE P2P bridge 0x7916
-					device pci 7.0 on end # PCIE P2P bridge 0x7917
-					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "gpp_configuration" = "4"
-					register "port_enable" = "0xfc"
-					register "gfx_dev2_dev3" = "1"
-					register "gfx_dual_slot" = "0"
-					register "gfx_lane_reversal" = "0"
-					register "gfx_tmds" = "0"
-					register "gfx_compliance" = "0"
-					register "gfx_reconfiguration" = "1"
-					register "gfx_link_width" = "0"
-				end
-				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
-					device pci 12.0 on end # SATA  0x4380
-					device pci 13.0 on end # USB   0x4387
-					device pci 13.1 on end # USB   0x4388
-					device pci 13.2 on end # USB   0x4389
-					device pci 13.3 on end # USB   0x438a
-					device pci 13.4 on end # USB   0x438b
-					device pci 13.5 on end # USB 2 0x4386
-	 				device pci 14.0 on # SM        0x4385
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end
-					end # SM
-					device pci 14.1 on end # IDE    0x438c
-					device pci 14.2 on end # HDA    0x4383
-					device pci 14.3 on # LPC	0x438d
-						chip superio/ite/it8712f
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.2 off #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.3 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.4 off end #  EC
-							device pnp 2e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 2e.6 on #  Mouse
-								irq 0x70 = 12
-							end
-							device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
-							end
-							device pnp 2e.8 off #  MIDI
-								io 0x60 = 0x300
-								irq 0x70 = 9
-							end
-							device pnp 2e.9 off #  GAME
-								io 0x60 = 0x220
-							end
-							device pnp 2e.a off end #  CIR
-						end	#superio/ite/it8712f
-					end		#LPC
-					device pci 14.4 on end # PCI 0x4384
-					device pci 14.5 on end # ACI 0x4382
-					device pci 14.6 on end # MCI 0x438e
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "hda_viddid" = "0x10ec0882"
-				end	#southbridge/amd/sb600
-			end #  device pci 18.0
-
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end		#northbridge/amd/amdk8
-	end #pci_domain
-end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/technexion/tim8690/Options.lb b/src/mainboard/technexion/tim8690/Options.lb
deleted file mode 100644
index 9589fcd..0000000
--- a/src/mainboard/technexion/tim8690/Options.lb
+++ /dev/null
@@ -1,300 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_VIDEO_MB
-uses CONFIG_GFXUMA
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-# BTDC: Only one HT device on Herring.
-#HT Unit ID offset
-#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-
-#real SB Unit ID
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
-
-#make the SB HT chain on bus 0
-default CONFIG_SB_HT_CHAIN_ON_BUS0=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="tim8690"
-default CONFIG_MAINBOARD_VENDOR="technexion"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
-
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_VIDEO_MB=1
-default CONFIG_GFXUMA=1
-default CONFIG_HAVE_MAINBOARD_RESOURCES=1
-
-### End Options.lb
-end
diff --git a/src/mainboard/technologic/ts5300/Config.lb b/src/mainboard/technologic/ts5300/Config.lb
deleted file mode 100644
index fdc26ea..0000000
--- a/src/mainboard/technologic/ts5300/Config.lb
+++ /dev/null
@@ -1,111 +0,0 @@
-default CONFIG_ROM_SIZE = 128 * 1024 
-default CONFIG_FALLBACK_SIZE = 0x10000
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 32 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-
-# VGA console
-#if CONFIG_CONSOLE_VGA
-#	default CONFIG_PCI_ROM_RUN=1
-#end
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-dir /devices
-config chip.h
-
-chip cpu/amd/sc520
-	device pci_domain 0 on 
-		device pci 0.0 on end
-	
-#		register "com1" = "{1}"
-#		register "com1" = "{1, 0, 0x3f8, 4}"
-	end
-
-end
diff --git a/src/mainboard/technologic/ts5300/Options.lb b/src/mainboard/technologic/ts5300/Options.lb
deleted file mode 100644
index 1028c98..0000000
--- a/src/mainboard/technologic/ts5300/Options.lb
+++ /dev/null
@@ -1,135 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_COMPRESS
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_USE_INIT
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-
-
-uses CONFIG_CONSOLE_SERIAL8250
-
-
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-
-default CONFIG_CONSOLE_SERIAL8250=1
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x2f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=2
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-end
diff --git a/src/mainboard/televideo/tc7020/Config.lb b/src/mainboard/televideo/tc7020/Config.lb
deleted file mode 100644
index ff76635..0000000
--- a/src/mainboard/televideo/tc7020/Config.lb
+++ /dev/null
@@ -1,130 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Kenji Noguchi <tokoy246@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1		# Northbridge
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 12.0 on		# ISA bridge
-        chip superio/nsc/pc97317	# Super I/O
-          device pnp 2e.0 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.1 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.2 on		# RTC, Advanced power control (APC)
-            io 0x60 = 0x70
-            irq 0x70 = 8
-          end
-          device pnp 2e.3 off		# Floppy (N/A on this board)
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.4 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.5 on		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.6 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.7 on		# GPIO
-            io 0x60 = 0xe0
-          end
-          device pnp 2e.8 on		# Power management
-            io 0x60 = 0xe8
-          end
-        end
-      end
-      device pci 12.1 off end		# SMI
-      device pci 12.2 on end		# IDE
-      device pci 12.3 on end		# Audio
-      device pci 12.4 on end		# VGA (onboard)
-      device pci 13.0 on end		# USB
-      device pci 14.0 on end		# MiniPCI slot
-      device pci 15.0 on end		# Ethernet (onboard)
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "0"	# Not available/needed on this board
-    end
-  end
-  chip cpu/amd/model_gx1		# CPU
-  end
-end
diff --git a/src/mainboard/televideo/tc7020/Options.lb b/src/mainboard/televideo/tc7020/Options.lb
deleted file mode 100644
index 9b0cfb8..0000000
--- a/src/mainboard/televideo/tc7020/Options.lb
+++ /dev/null
@@ -1,102 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Kenji Noguchi <tokyo246@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_VIDEO_MB
-uses CONFIG_SPLASH_GRAPHIC
-uses CONFIG_GX1_VIDEO
-uses CONFIG_GX1_VIDEOMODE
-uses CONFIG_PIRQ_ROUTE
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-default CONFIG_GX1_VIDEO = 1
-default CONFIG_GX1_VIDEOMODE = 0
-default CONFIG_SPLASH_GRAPHIC = 1
-default CONFIG_VIDEO_MB = 2
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_MAINBOARD_VENDOR = "TeleVideo"
-default CONFIG_MAINBOARD_PART_NUMBER = "TC7020"
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_PIRQ_ROUTE=1
-default CONFIG_IRQ_SLOT_COUNT = 3	# Soldered NIC, internal USB, mini PCI slot
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
-end
diff --git a/src/mainboard/thomson/ip1000/Config.lb b/src/mainboard/thomson/ip1000/Config.lb
deleted file mode 100644
index a509341..0000000
--- a/src/mainboard/thomson/ip1000/Config.lb
+++ /dev/null
@@ -1,144 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object dsdt.o
-	object acpi_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i82830		# Northbridge
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    chip southbridge/intel/i82801xx	# Southbridge
-      register "pirqa_routing" = "0x05"
-      register "pirqb_routing" = "0x06"
-      register "pirqc_routing" = "0x07"
-      register "pirqd_routing" = "0x09"
-      register "pirqe_routing" = "0x0a"
-      register "pirqf_routing" = "0x80"
-      register "pirqg_routing" = "0x80"
-      register "pirqh_routing" = "0x0b"
-
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-
-      device pci 1d.0 on end		# USB UHCI Controller #1
-      device pci 1d.1 on end		# USB UHCI Controller #2
-      device pci 1d.2 on end		# USB UHCI Controller #3
-      device pci 1d.7 on end		# USB2 EHCI Controller
-      device pci 1e.0 on		# PCI bridge
-        device pci 08.0 on end		# Intel 82801DB PRO/100 VE Ethernet
-      end
-      device pci 1f.0 on		# ISA/LPC bridge
-        chip superio/smsc/smscsuperio	# Super I/O
-          device pnp 2e.0 off		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 4
-          end
-          device pnp 2e.4 on		# Com1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.5 on		# Com2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.7 on		# PS/2 keyboard/mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# Keyboard interrupt
-            irq 0x72 = 12		# Mouse interrupt
-          end
-          device pnp 2e.9 off end	# Game port
-          device pnp 2e.a on		# PME
-            io 0x60 = 0x800
-          end
-          device pnp 2e.b off end	# MPU-401
-        end
-      end
-      device pci 1f.1 on end		# IDE
-      device pci 1f.3 on end		# SMBus
-      device pci 1f.5 on end		# AC'97 audio
-      device pci 1f.6 off end		# AC'97 modem
-    end
-  end
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/socket_PGA370	# Low Voltage PIII Micro-FCBGA Socket 479
-      device apic 0 on end		# APIC
-    end
-  end
-end
-
diff --git a/src/mainboard/thomson/ip1000/Options.lb b/src/mainboard/thomson/ip1000/Options.lb
deleted file mode 100644
index 655d94f..0000000
--- a/src/mainboard/thomson/ip1000/Options.lb
+++ /dev/null
@@ -1,96 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CC
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_IOAPIC
-uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_UDELAY_TSC
-uses CONFIG_VIDEO_MB
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_HEAP_SIZE
-uses HOSTCC
-uses CONFIG_IRQ_SLOT_COUNT
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_OBJCOPY
-uses CONFIG_RAMBASE
-uses CONFIG_ROMBASE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_LCS
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_GENERATE_ACPI_TABLES = 0
-default CONFIG_IOAPIC = 0
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0
-default CONFIG_VIDEO_MB = 0
-default CONFIG_STACK_SIZE = 0x2000
-default CONFIG_HEAP_SIZE = 0x4000
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_ROM_PAYLOAD = 1
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3	# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAINBOARD_VENDOR = "THOMSON"
-default CONFIG_MAINBOARD_PART_NUMBER = "IP1000"
-end
diff --git a/src/mainboard/tyan/s1846/Config.lb b/src/mainboard/tyan/s1846/Config.lb
deleted file mode 100644
index 31e0fb8..0000000
--- a/src/mainboard/tyan/s1846/Config.lb
+++ /dev/null
@@ -1,128 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/nsc/pc87309	# Super I/O
-          device pnp 2e.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.2 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.3 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.4 on		# Power management
-          end
-          device pnp 2e.5 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.6 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/tyan/s1846/Options.lb b/src/mainboard/tyan/s1846/Options.lb
deleted file mode 100644
index 975a085..0000000
--- a/src/mainboard/tyan/s1846/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 0
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-end
diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb
deleted file mode 100644
index 4f9fc5b..0000000
--- a/src/mainboard/tyan/s2735/Config.lb
+++ /dev/null
@@ -1,179 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_ROM_PAYLOAD = 1
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_HARD_RESET object reset.o end
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else
-
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/x86/car/cache_as_ram.lds
-        end
-
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/x86/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for tyan/s2735
-chip northbridge/intel/e7501
-        device pci_domain 0 on
-		device pci 0.0 on end
-        	device pci 0.1 on end
-        	device pci 2.0 on
-        		chip southbridge/intel/i82870
-        	        	device pci 1c.0 on end
-		                device pci 1d.0 on 
-                                     	 device pci 1.0 on end # intel lan
-                                        device pci 1.1 on end
-				end
-        	                device pci 1e.0 on end
-        	                device pci 1f.0 on end
-        		end
-		end
-        	device pci 6.0 on end
-        	chip southbridge/intel/i82801er
-        		device pci 1d.0 on end
-		        device pci 1d.1 on end
-        	        device pci 1d.2 on end
-        	        device pci 1d.3 on end
-		        device pci 1d.7 on end
-		        device pci 1e.0 on 
-                             	device pci 1.0 on end # intel lan 10/100
-                                device pci 2.0 on end # ati
-			end
-		        device pci 1f.0 on
-				chip superio/winbond/w83627hf
-                                	device pnp 2e.0 on #  Floppy
-                                        	io 0x60 = 0x3f0
-                                                irq 0x70 = 6
-                                                drq 0x74 = 2
-                                        end
-	                                device pnp 2e.1 off #  Parallel Port
-                                                io 0x60 = 0x378
-                                                irq 0x70 = 7
-                                        end
-                                        device pnp 2e.2 on #  Com1
-        	                                io 0x60 = 0x3f8
-                                                irq 0x70 = 4
-                                        end
-                                        device pnp 2e.3 on #  Com2
-                                                io 0x60 = 0x2f8
-                                                irq 0x70 = 3
-                                        end
-                                        device pnp 2e.5 on #  Keyboard
-                                                io 0x60 = 0x60
-                                                io 0x62 = 0x64
-                                                irq 0x70 = 1
-                                                irq 0x72 = 12
-                                        end
-                                        device pnp 2e.6 off #  CIR
-                                                io 0x60 = 0x100
-                                        end
-                                        device pnp 2e.7 off #  GAME_MIDI_GIPO1
-                                                io 0x60 = 0x220
-                                                io 0x62 = 0x300
-                                                irq 0x70 = 9
-                                        end                               
-                                        device pnp 2e.8 off end #  GPIO2
-                                        device pnp 2e.9 off end #  GPIO3
-                                        device pnp 2e.a off end #  ACPI
-                                        device pnp 2e.b on #  HW Monitor
-                                                io 0x60 = 0x290
-                                                irq 0x70 = 5
-                                        end
-				end
-		        end
-		        device pci 1f.1 off end
-        	        device pci 1f.2 on end
-        	        device pci 1f.3 on end
-        		device pci 1f.5 off end
-		        device pci 1f.6 off end
-		end # SB
-        end # PCI_DOMAIN
-        device apic_cluster 0 on
-                chip cpu/intel/socket_mPGA604
-                        device apic 0 on end
-                end
-                chip cpu/intel/socket_mPGA604
-                        device apic 6 on end
-                end
-        end
-end
-
diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb
deleted file mode 100644
index 61933d2..0000000
--- a/src/mainboard/tyan/s2735/Options.lb
+++ /dev/null
@@ -1,256 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_INIT
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_SERIAL_CPU_INIT
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-#512K bytes 
-default CONFIG_ROM_SIZE=524288
-
-#1M bytes
-#default CONFIG_ROM_SIZE=1048576
-
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=15
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-default CONFIG_SERIAL_CPU_INIT=0
-
-#BTEXT Console
-#default CONFIG_CONSOLE_BTEXT=1
-
-#VGA Console
-#default CONFIG_CONSOLE_VGA=1
-#default CONFIG_PCI_ROM_RUN=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-#default CONFIG_DCACHE_RAM_BASE=0xF2000000
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="s2735"
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb
deleted file mode 100644
index eaa338e..0000000
--- a/src/mainboard/tyan/s2850/Config.lb
+++ /dev/null
@@ -1,197 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for tyan/s2850
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on                        
-                chip cpu/amd/socket_940                
-                        device apic 0 on end                    
-                end                                     
-        end 
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on # LDT0
-				#  devices on link 2, link 2 == LDT 2
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-                                                #chip drivers/ati/ragexl
-                                                device pci b.0 on end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 on #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	                               device pnp 2e.6 off #  CIR
-                	                                        io 0x60 = 0x100
-                	                                end
-                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
-                	                                        io 0x60 = 0x220
-                	                                        io 0x62 = 0x300
-                	                                        irq 0x70 = 9
-                	                                end  
-                	                                device pnp 2e.8 off end #  GPIO2
-                	                                device pnp 2e.9 off end #  GPIO3
-                	                                device pnp 2e.a off end #  ACPI
-                	                                device pnp 2e.b on #  HW Monitor
-                	                                        io 0x60 = 0x290
-                	                                        irq 0x70 = 5
-                	                                end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on 
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
-                                                end
-					end
-					device pci 1.5 on end
-					device pci 1.6 off end
-                                        register "ide0_enable" = "1"
-                                        register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0 
-                	device pci 18.0 on end
-                	device pci 18.0 on end
-			
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-	end 
-end
-
diff --git a/src/mainboard/tyan/s2850/Options.lb b/src/mainboard/tyan/s2850/Options.lb
deleted file mode 100644
index a53d5b7..0000000
--- a/src/mainboard/tyan/s2850/Options.lb
+++ /dev/null
@@ -1,244 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=12
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="S2850"
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb
deleted file mode 100644
index 6145ba7..0000000
--- a/src/mainboard/tyan/s2875/Config.lb
+++ /dev/null
@@ -1,189 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for tyan/s2875
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  northbridge 
-				#  devices on link 0, link 0 == LDT 0
-				chip southbridge/amd/amd8151
-					# the on/off keyword is mandatory
-					device pci 0.0 on end
-					device pci 1.0 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-                                                device pci 5.0 on end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 on #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 off #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-								irq 0x72 = 12
-							end
-							device pnp 2e.6 off #  CIR
-								io 0x60 = 0x100
-							end
-							device pnp 2e.7 off #  GAME_MIDI_GIPO1
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end  
-							device pnp 2e.8 off end #  GPIO2
-							device pnp 2e.9 off end #  GPIO3
-							device pnp 2e.a off end #  ACPI
-							device pnp 2e.b on #  HW Monitor
-								io 0x60 = 0x290
-								irq 0x70 = 5
-							end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on end
-					device pci 1.5 on end
-					device pci 1.6 off end
-                                        register "ide0_enable" = "1"
-                                        register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0 
-			
-			device pci 18.0 on end
-			device pci 18.0 on end
-			
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-	end 
-end
-
diff --git a/src/mainboard/tyan/s2875/Options.lb b/src/mainboard/tyan/s2875/Options.lb
deleted file mode 100644
index 51913e3..0000000
--- a/src/mainboard/tyan/s2875/Options.lb
+++ /dev/null
@@ -1,245 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=13
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="s2875"
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb
deleted file mode 100644
index 5e72afb..0000000
--- a/src/mainboard/tyan/s2880/Config.lb
+++ /dev/null
@@ -1,200 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for tyan/s2880
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  northbridge 
-				#  devices on link 0, link 0 == LDT 0
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-					device pci 0.0 on
-                                                device pci 9.0 on end #broadcom
-						device pci 9.1 on end
-#                                                chip drivers/lsi/53c1030
-#                                                        device pci a.0 on end
-#                                                        device pci a.1 on end
-#                                                        register "fw_address" = "0xfff8c000"
-#                                                end
-					end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-                                                device pci 5.0 on end #some sata
-                                                device pci 6.0 on end #adti
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 on #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	                                device pnp 2e.6 off #  CIR
-                	                                        io 0x60 = 0x100
-                	                                end
-                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
-                	                                        io 0x60 = 0x220
-                	                                        io 0x62 = 0x300
-                	                                        irq 0x70 = 9
-                	                                end  
-                	                                device pnp 2e.8 off end #  GPIO2
-                	                                device pnp 2e.9 off end #  GPIO3
-                	                                device pnp 2e.a off end #  ACPI
-                	                                device pnp 2e.b on #  HW Monitor
-                	                                        io 0x60 = 0x290
-                	                                        irq 0x70 = 5
-                	                                end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on end
-					device pci 1.5 off end
-					device pci 1.6 off end
-                                        register "ide0_enable" = "1"
-                                        register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0 
-			
-                	device pci 18.0 on end
-                	device pci 18.0 on end
-			
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-	end 
-end
-
diff --git a/src/mainboard/tyan/s2880/Options.lb b/src/mainboard/tyan/s2880/Options.lb
deleted file mode 100644
index c41e03f..0000000
--- a/src/mainboard/tyan/s2880/Options.lb
+++ /dev/null
@@ -1,244 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=13
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=0
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="S2880"
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb
deleted file mode 100644
index a46e0ef..0000000
--- a/src/mainboard/tyan/s2881/Config.lb
+++ /dev/null
@@ -1,233 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-object get_bus_conf.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for tyan/s2881
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on end # LDT0
-			device pci 18.0 on end # LDT1
-			device pci 18.0 on #  northbridge 
-				#  devices on link 2, link 2 == LDT 2
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-					device pci 0.0 on 
-                                                device pci 9.0 on end # Broadcom 5704
-                                                device pci 9.1 on end
-                                                device pci a.0 on end # Adaptic
-                                                device pci a.1 on end
-					end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-                                                device pci 5.0 on end # SiI
-                                                device pci 6.0 on end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 on #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	                                device pnp 2e.6 off #  CIR
-                	                                        io 0x60 = 0x100
-                	                                end
-                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
-                	                                        io 0x60 = 0x220
-                	                                        io 0x62 = 0x300
-                	                                        irq 0x70 = 9
-                	                                end  
-                	                                device pnp 2e.8 off end #  GPIO2
-                	                                device pnp 2e.9 off end #  GPIO3
-                	                                device pnp 2e.a off end #  ACPI
-                	                                device pnp 2e.b on #  HW Monitor
-                	                                        io 0x60 = 0x290
-                	                                        irq 0x70 = 5
-                	                                end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-                                        device pci 1.3 on 
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 1-0-0
-                                                        device i2c 54 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 1-0-1
-                                                        device i2c 55 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 1-1-0
-                                                        device i2c 56 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 1-1-1
-                                                        device i2c 57 on end
-                                                end
-                                                chip drivers/i2c/adm1027 # ADT7463A CPU0/1 temp, CPU1 vid, SYS FAN 1/2/3
-                                                        device i2c 2d on end
-                                                end
-                                                chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 4,CPU0 vid, CPU0/1 FAN
-                                                        device i2c 2a on end
-                                                end
-                                                chip drivers/generic/generic # Winbond HWM 0x92
-                                                        device i2c 49 on end
-                                                end
-                                                chip drivers/generic/generic # Winbond HWM 0x94
-                                                        device i2c 4a on end
-                                                end
-                                        end # acpi
-					device pci 1.5 off end
-					device pci 1.6 off end
-                                        register "ide0_enable" = "1"
-                                        register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0 
-			
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-	end 
-end
-
diff --git a/src/mainboard/tyan/s2881/Options.lb b/src/mainboard/tyan/s2881/Options.lb
deleted file mode 100644
index 59002d2..0000000
--- a/src/mainboard/tyan/s2881/Options.lb
+++ /dev/null
@@ -1,261 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-##HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0a
-
-##real SB Unit ID, default is 0x20, mean dont touch it at last
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-##only offset for SB chain?, default is yes(1)
-#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="s2881"
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb
deleted file mode 100644
index 2667331..0000000
--- a/src/mainboard/tyan/s2882/Config.lb
+++ /dev/null
@@ -1,227 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for tyan/s2882
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device apic 0 on end
-                end
-        end
-
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  northbridge 
-				#  devices on link 0, link 0 == LDT 0
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-					device pci 0.0 on
-                                                device pci 6.0 on end # adaptec
-                                                device pci 6.1 on end
-                                                device pci 9.0 on end # broadcom 5704
-                                                device pci 9.1 on end
-					end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-                                                device pci 5.0 on end
-                                        #       chip drivers/ati/ragexl
-                                                device pci 6.0 on end
-                                        #       end
-                                                device pci 8.0 on end #intel 10/100
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 on #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	                                device pnp 2e.6 off #  CIR
-                	                                        io 0x60 = 0x100
-                	                                end
-                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
-                	                                        io 0x60 = 0x220
-                	                                        io 0x62 = 0x300
-                	                                        irq 0x70 = 9
-                	                                end  
-                	                                device pnp 2e.8 off end #  GPIO2
-                	                                device pnp 2e.9 off end #  GPIO3
-                	                                device pnp 2e.a off end #  ACPI
-                	                                device pnp 2e.b on #  HW Monitor
-                	                                        io 0x60 = 0x290
-                	                                        irq 0x70 = 5
-                	                                end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on end
-					device pci 1.3 on 
-#						 chip drivers/generic/generic #dimm 0-0-0
-#							 device i2c 50 on end
-#						 end
-#						 chip drivers/generic/generic #dimm 0-0-1
-#							 device i2c 51 on end
-#						 end	 
-#						 chip drivers/generic/generic #dimm 0-1-0
-#							 device i2c 52 on end
-#						 end
-#						 chip drivers/generic/generic #dimm 0-1-1
-#							 device i2c 53 on end
-#						 end
-#						 chip drivers/generic/generic #dimm 1-0-0
-#							 device i2c 54 on end
-#						 end
-#						 chip drivers/generic/generic #dimm 1-0-1
-#							 device i2c 55 on end
-#						 end
-#						 chip drivers/generic/generic #dimm 1-1-0
-#							 device i2c 56 on end
-#						 end
-#						 chip drivers/generic/generic #dimm 1-1-1
-#							 device i2c 57 on end
-#						 end
-                                        end # acpi
-					device pci 1.5 off end
-					device pci 1.6 off end
-					register "ide0_enable" = "1"
-					register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0 
-			
-                	device pci 18.0 on end
-                	device pci 18.0 on end
-			
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end # NB
-	end #pci_domain
-end
-
diff --git a/src/mainboard/tyan/s2882/Options.lb b/src/mainboard/tyan/s2882/Options.lb
deleted file mode 100644
index d4ff6fe..0000000
--- a/src/mainboard/tyan/s2882/Options.lb
+++ /dev/null
@@ -1,244 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=15
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="S2882"
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb
deleted file mode 100644
index 26389a1..0000000
--- a/src/mainboard/tyan/s2885/Config.lb
+++ /dev/null
@@ -1,233 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-object get_bus_conf.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for tyan/s2885
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on # LDT0
-				chip southbridge/amd/amd8151
-					# the on/off keyword is mandatory
-					device pci 0.0 on end
-					device pci 1.0 on end
-				end
-			end
-			device pci 18.0 on end # LDT1
-			device pci 18.0 on #  northbridge 
-				#  devices on link 2, link 2 == LDT 2
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-					device pci 0.0 on 
-                                                device pci 9.0 on end # broadcom 5703
-					end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-                                                device pci b.0 on end # SiI 3114
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 on #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 on #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	        			device pnp 2e.6 off #  CIR
-								io 0x60 = 0x100
-							end
-                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end						
-                	        			device pnp 2e.8 off end #  GPIO2
-                	        			device pnp 2e.9 off end #  GPIO3
-                	        			device pnp 2e.a off end #  ACPI
-                	        			device pnp 2e.b on #  HW Monitor
- 					 			io 0x60 = 0x290
-								irq 0x70 = 5
-                					end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end
-                                                end              
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
-                                                end             
-                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
-                                                end              
-                                                chip drivers/generic/generic #dimm 1-0-0
-                                                        device i2c 54 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-0-1
-                                                        device i2c 55 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 1-1-0
-                                                        device i2c 56 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-1
-                                                        device i2c 57 on end
-                                                end 
-					end # acpi
-					device pci 1.5 on end
-					device pci 1.6 off end
-                	                register "ide0_enable" = "1"
-                	                register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0 
-			
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-
-	end #pci_domain
-
-#        chip drivers/generic/debug 
-#                device pnp 0.0 off end
-#                device pnp 0.1 off end 
-#                device pnp 0.2 off end
-#                device pnp 0.3 off end
-#		device pnp 0.4 off end
-#		device pnp 0.5 on end
-#        end
-end
-
diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb
deleted file mode 100644
index fc43fc8..0000000
--- a/src/mainboard/tyan/s2885/Options.lb
+++ /dev/null
@@ -1,269 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-##HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0a
-
-##real SB Unit ID, default is 0x20, mean dont touch it at last
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-##only offset for SB chain?, default is yes(1)
-#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=1
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="s2885"
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb
deleted file mode 100644
index 42627a3..0000000
--- a/src/mainboard/tyan/s2891/Config.lb
+++ /dev/null
@@ -1,123 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_ROM_PAYLOAD       = 1
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/ati/ragexl
-
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_GENERATE_ACPI_TABLES
-        object acpi_tables.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-        object ./dsdt.o
-	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
-	#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
-end
-
-if CONFIG_USE_INIT
-	makerule ./auto.o
-		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-	end
-else
-	makerule ./auto.inc
-		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for CK804
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit southbridge/nvidia/ck804/romstrap.inc
-	ldscript /southbridge/nvidia/ck804/romstrap.lds
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-include devicetree.cb
diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb
deleted file mode 100644
index a0ed35b..0000000
--- a/src/mainboard/tyan/s2891/Options.lb
+++ /dev/null
@@ -1,302 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_HAVE_LOW_TABLES
-uses CONFIG_MULTIBOOT
-uses CONFIG_HAVE_SMI_HANDLER
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_VGA_ROM_RUN
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_ID_SECTION_OFFSET
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE=512*1024
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build SMI handler
-##
-default CONFIG_HAVE_SMI_HANDLER=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to provide ACPI support
-##
-default CONFIG_GENERATE_ACPI_TABLES=1
-default CONFIG_HAVE_LOW_TABLES=1
-default CONFIG_MULTIBOOT=0
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-default CONFIG_VGA_ROM_RUN=1
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-##HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-##real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-##only offset for SB chain?, default is yes(1)
-#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#BTEXT Console
-#default CONFIG_CONSOLE_BTEXT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=0
-
-
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="s2891"
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb
deleted file mode 100644
index 3864558..0000000
--- a/src/mainboard/tyan/s2892/Config.lb
+++ /dev/null
@@ -1,124 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_ROM_PAYLOAD = 1
-
-arch i386 end
-
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/ati/ragexl
-
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_GENERATE_ACPI_TABLES
-        object acpi_tables.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-        object ./dsdt.o
-	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
-	#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
-end
-
-if CONFIG_USE_INIT
-	makerule ./auto.o
-		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-	end
-else
-	makerule ./auto.inc
-		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for CK804
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit southbridge/nvidia/ck804/romstrap.inc
-	ldscript /southbridge/nvidia/ck804/romstrap.lds
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-include devicetree.cb
diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb
deleted file mode 100644
index e3f1606..0000000
--- a/src/mainboard/tyan/s2892/Options.lb
+++ /dev/null
@@ -1,290 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_HAVE_LOW_TABLES
-uses CONFIG_MULTIBOOT
-uses CONFIG_HAVE_SMI_HANDLER
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_VGA_ROM_RUN
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_ID_SECTION_OFFSET
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE=1024*1024
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build SMI handler
-##
-default CONFIG_HAVE_SMI_HANDLER=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to provide ACPI support
-##
-default CONFIG_GENERATE_ACPI_TABLES=1
-default CONFIG_HAVE_LOW_TABLES=1
-default CONFIG_MULTIBOOT=0
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-default CONFIG_VGA_ROM_RUN=1
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-##HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-##real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-##only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#BTEXT Console
-#default CONFIG_CONSOLE_BTEXT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="s2892"
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb
deleted file mode 100644
index 1b7f808..0000000
--- a/src/mainboard/tyan/s2895/Config.lb
+++ /dev/null
@@ -1,145 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_GENERATE_ACPI_TABLES
-        object acpi_tables.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-        object ./dsdt.o
-	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
-	#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
-end
-
-if CONFIG_USE_INIT
-	makerule ./auto.o
-		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-	end
-else
-	makerule ./auto.inc
-		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit cpu/x86/16bit/entry16.inc
-		ldscript /cpu/x86/16bit/entry16.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit cpu/x86/16bit/entry16.inc
-		ldscript /cpu/x86/16bit/entry16.lds
-	end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for CK804
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit southbridge/nvidia/ck804/romstrap.inc
-		ldscript /southbridge/nvidia/ck804/romstrap.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit southbridge/nvidia/ck804/romstrap.inc
-		ldscript /southbridge/nvidia/ck804/romstrap.lds
-	end
-end
-
-##
-## Setup Cache-As-Ram
-##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-			ldscript /arch/i386/lib/failover_failover.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-			ldscript /arch/i386/lib/failover.lds
-	end
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-include devicetree.cb
diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb
deleted file mode 100644
index 6659c9a..0000000
--- a/src/mainboard/tyan/s2895/Options.lb
+++ /dev/null
@@ -1,311 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_HAVE_LOW_TABLES
-uses CONFIG_MULTIBOOT
-uses CONFIG_HAVE_SMI_HANDLER
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_VGA_ROM_RUN
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_ID_SECTION_OFFSET
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE=1024*1024
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-#FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#FAILOVER: 4K
-default CONFIG_FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build SMI handler
-##
-default CONFIG_HAVE_SMI_HANDLER=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to provide ACPI support
-##
-default CONFIG_GENERATE_ACPI_TABLES=1
-default CONFIG_HAVE_LOW_TABLES=1
-default CONFIG_MULTIBOOT=0
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-default CONFIG_VGA_ROM_RUN=1
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-default CONFIG_SERIAL_CPU_INIT=0
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-##HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-##real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-##only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=0
-
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="s2895"
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s2912/Config.lb b/src/mainboard/tyan/s2912/Config.lb
deleted file mode 100644
index 35511f8..0000000
--- a/src/mainboard/tyan/s2912/Config.lb
+++ /dev/null
@@ -1,315 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	if CONFIG_USE_INIT
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-	makerule ./apc_auto.o
-		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-	end
-	ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_F
-			device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.0 on
-				#  devices on link 0, link 0 == LDT 0
-				chip southbridge/nvidia/mcp55
-					device pci 0.0 on end   # HT
-					device pci 1.0 on # LPC
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 on #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-								irq 0x72 = 12
-							end
-							device pnp 2e.6 off  # SFI
-								io 0x62 = 0x100
-							end
-							device pnp 2e.7 off #  GPIO_GAME_MIDI
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end
-							device pnp 2e.8 off end #  WDTO_PLED
-							device pnp 2e.9 off end #  GPIO_SUSLED
-							device pnp 2e.a off end #  ACPI
-							device pnp 2e.b on #  HW Monitor
-								io 0x60 = 0x290
-								irq 0x70 = 5
-							end
-						end
-					end
-					device pci 1.1 on # SM 0
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end
-						chip drivers/generic/generic #dimm 1-0-0
-							device i2c 54 on end
-						end
-						chip drivers/generic/generic #dimm 1-0-1
-							device i2c 55 on end
-						end
-						chip drivers/generic/generic #dimm 1-1-0
-							device i2c 56 on end
-						end
-						chip drivers/generic/generic #dimm 1-1-1
-							device i2c 57 on end
-						end
-					end # SM
-					device pci 1.1 on # SM 1
-#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#						chip drivers/generic/generic #PCIXA Slot1
-#							device i2c 50 on end
-#						end
-#						chip drivers/generic/generic #PCIXB Slot1
-#							device i2c 51 on end
-#						end
-#						chip drivers/generic/generic #PCIXB Slot2
-#							device i2c 52 on end
-#						end
-#						chip drivers/generic/generic #PCI Slot1
-#							device i2c 53 on end
-#						end
-#						chip drivers/generic/generic #Master MCP55 PCI-E
-#							device i2c 54 on end
-#						end
-#						chip drivers/generic/generic #Slave MCP55 PCI-E
-#							device i2c 55 on end
-#						end
-						chip drivers/generic/generic #MAC EEPROM
-							device i2c 51 on end
-						end
-
-					end # SM
-					device pci 2.0 on end # USB 1.1
-					device pci 2.1 on end # USB 2
-					device pci 4.0 on end # IDE
-					device pci 5.0 on end # SATA 0
-					device pci 5.1 on end # SATA 1
-					device pci 5.2 on end # SATA 2
-					device pci 6.0 on end # PCI
-					device pci 6.1 off end # AZA
-					device pci 8.0 on end # NIC
-					device pci 9.0 on end # NIC
-					device pci a.0 on end # PCI E 5
-					device pci b.0 off end # PCI E 4
-					device pci c.0 off end # PCI E 3
-					device pci d.0 on end # PCI E 2
-					device pci e.0 off end # PCI E 1
-					device pci f.0 on end # PCI E 0
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "sata1_enable" = "1"
-					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end #  device pci 18.0
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end # mc0
-
-	end # PCI domain
-
-#	chip drivers/generic/debug
-#		device pnp 0.0 off end # chip name
-#		device pnp 0.1 on end # pci_regs_all
-#		device pnp 0.2 on end # mem
-#		device pnp 0.3 off end # cpuid
-#		device pnp 0.4 on end # smbus_regs_all
-#		device pnp 0.5 off end # dual core msr
-#		device pnp 0.6 off end # cache size
-#		device pnp 0.7 off end # tsc
-#		device pnp 0.8 off  end # io
-#		device pnp 0.9 off end # io
-#	end
-end #root_complex
diff --git a/src/mainboard/tyan/s2912/Options.lb b/src/mainboard/tyan/s2912/Options.lb
deleted file mode 100644
index 52d8202..0000000
--- a/src/mainboard/tyan/s2912/Options.lb
+++ /dev/null
@@ -1,355 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_USBDEBUG_DIRECT
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ID_SECTION_OFFSET
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-#default CONFIG_ROM_SIZE=0x100000
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-#FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#FAILOVER: 4K
-default CONFIG_FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=0
-## extra SSDT num
-default CONFIG_ACPI_SSDTX_NUM=3
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#default CONFIG_USBDEBUG_DIRECT=1
-
-#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default CONFIG_HT_CHAIN_UNITID_BASE=0
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_AP_CODE_IN_CAR=0
-default CONFIG_MEM_TRAIN_SEQ=1
-default CONFIG_WAIT_BEFORE_CPUS_INIT=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="S2912"
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-#default CONFIG_COMPRESSED_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s2912_fam10/Config.lb b/src/mainboard/tyan/s2912_fam10/Config.lb
deleted file mode 100644
index 538abab..0000000
--- a/src/mainboard/tyan/s2912_fam10/Config.lb
+++ /dev/null
@@ -1,320 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	if CONFIG_USE_INIT
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-	makerule ./apc_auto.o
-		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-	end
-	ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-dir /southbridge/nvidia/mcp55
-
-chip northbridge/amd/amdfam10/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_F_1207
-			device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdfam10 #mc0
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.0 on
-				#  SB on link 2.0.
-				chip southbridge/nvidia/mcp55
-					device pci 0.0 on end   # HT
-					device pci 1.0 on # LPC
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 on #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-								irq 0x72 = 12
-							end
-							device pnp 2e.6 off  # SFI
-								io 0x62 = 0x100
-							end
-							device pnp 2e.7 off #  GPIO_GAME_MIDI
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end
-							device pnp 2e.8 off end #  WDTO_PLED
-							device pnp 2e.9 off end #  GPIO_SUSLED
-							device pnp 2e.a off end #  ACPI
-							device pnp 2e.b on #  HW Monitor
-								io 0x60 = 0x290
-								irq 0x70 = 5
-							end
-						end
-					end
-					device pci 1.1 on # SM 0
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end
-						chip drivers/generic/generic #dimm 1-0-0
-							device i2c 54 on end
-						end
-						chip drivers/generic/generic #dimm 1-0-1
-							device i2c 55 on end
-						end
-						chip drivers/generic/generic #dimm 1-1-0
-							device i2c 56 on end
-						end
-						chip drivers/generic/generic #dimm 1-1-1
-							device i2c 57 on end
-						end
-					end # SM
-					device pci 1.1 on # SM 1
-#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#						chip drivers/generic/generic #PCIXA Slot1
-#							device i2c 50 on end
-#						end
-#						chip drivers/generic/generic #PCIXB Slot1
-#							device i2c 51 on end
-#						end
-#						chip drivers/generic/generic #PCIXB Slot2
-#							device i2c 52 on end
-#						end
-#						chip drivers/generic/generic #PCI Slot1
-#							device i2c 53 on end
-#						end
-#						chip drivers/generic/generic #Master MCP55 PCI-E
-#							device i2c 54 on end
-#						end
-#						chip drivers/generic/generic #Slave MCP55 PCI-E
-#							device i2c 55 on end
-#						end
-						chip drivers/generic/generic #MAC EEPROM
-							device i2c 51 on end
-						end
-
-					end # SM
-					device pci 2.0 on end # USB 1.1
-					device pci 2.1 on end # USB 2
-					device pci 4.0 on end # IDE
-					device pci 5.0 on end # SATA 0
-					device pci 5.1 on end # SATA 1
-					device pci 5.2 on end # SATA 2
-					device pci 6.0 on
-						device pci 4.0 on end
-					end # PCI
-					device pci 6.1 off end # AZA
-					device pci 8.0 on end # NIC
-					device pci 9.0 on end # NIC
-					device pci a.0 on end # PCI E 5
-					device pci b.0 off end # PCI E 4
-					device pci c.0 off end # PCI E 3
-					device pci d.0 on end # PCI E 2
-					device pci e.0 off end # PCI E 1
-					device pci f.0 on end # PCI E 0
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "sata1_enable" = "1"
-					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end #  device pci 18.0
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-		end # mc0
-
-	end # PCI domain
-
-#	chip drivers/generic/debug
-#		device pnp 0.0 off end # chip name
-#		device pnp 0.1 on end # pci_regs_all
-#		device pnp 0.2 on end # mem
-#		device pnp 0.3 off end # cpuid
-#		device pnp 0.4 on end # smbus_regs_all
-#		device pnp 0.5 off end # dual core msr
-#		device pnp 0.6 off end # cache size
-#		device pnp 0.7 off end # tsc
-#		device pnp 0.8 off  end # io
-#		device pnp 0.9 off end # io
-#	end
-end #root_complex
diff --git a/src/mainboard/tyan/s2912_fam10/Options.lb b/src/mainboard/tyan/s2912_fam10/Options.lb
deleted file mode 100644
index d9444d8..0000000
--- a/src/mainboard/tyan/s2912_fam10/Options.lb
+++ /dev/null
@@ -1,362 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_USBDEBUG_DIRECT
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_PCI_BUS_SEGN_BITS
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_AMDMCT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_AMD_UCODE_PATCH_FILE
-uses CONFIG_ID_SECTION_OFFSET
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1024*1024
-#default CONFIG_ROM_SIZE=0x100000
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=16384*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=0
-## extra SSDT num
-default CONFIG_ACPI_SSDTX_NUM=31
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS
-default CONFIG_LOGICAL_CPUS=1
-
-#default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=1
-default CONFIG_APIC_ID_OFFSET=0x00
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#default CONFIG_USBDEBUG_DIRECT=1
-
-#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default CONFIG_HT_CHAIN_UNITID_BASE=1
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc4000
-default CONFIG_DCACHE_RAM_SIZE=0x0c000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
-default CONFIG_USE_INIT=0
-
-default CONFIG_MEM_TRAIN_SEQ=2
-default CONFIG_WAIT_BEFORE_CPUS_INIT=0
-default CONFIG_AMDMCT = 1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="S2912 (Fam10)"
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912
-
-##
-## Set microcode patch file name
-##
-##	Barcelona rev DR-Ax:  "mc_patch_01000020.h"
-##	Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h"
-##	Barcelona rev DR-B2, B3: "mc_patch_01000095.h"
-##	Shanghai rev DA-C2: "mc_patch_0100009f.h"
-##
-default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = (128*1024) - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0xc0000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00200000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-#default CONFIG_COMPRESSED_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb
deleted file mode 100644
index 5e1aaf5..0000000
--- a/src/mainboard/tyan/s4880/Config.lb
+++ /dev/null
@@ -1,195 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_ROM_PAYLOAD = 1
-
-arch i386 end 
-
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	if CONFIG_USE_INIT
-
-		makerule ./auto.o
-        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-	        	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else
-
-		makerule ./auto.inc
-        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        		action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-			end
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for tyan/s4880
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device apic 0 on end
-                end
-        end
-
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on end # LDT0
-			device pci 18.0 on end # LDT1
-			device pci 18.0 on #  northbridge 
-				#  devices on link 2, link 2 == LDT 2
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-                                        device pci 0.0 on
-#                                                chip drivers/lsi/53c1030
-#                                                        device pci 4.0 on end
-#                                                        device pci 4.1 on end
-#                                                        register "fw_address" = "0xfff8c000"
-#                                                end
-                                                device pci 9.0 on end
-                                                device pci 9.1 on end
-					end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-                                                device pci 6.0 on end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 on #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	                                device pnp 2e.6 off #  CIR
-                	                                        io 0x60 = 0x100
-                	                                end
-                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
-                	                                        io 0x60 = 0x220
-                	                                        io 0x62 = 0x300
-                	                                        irq 0x70 = 9
-                	                                end  
-                	                                device pnp 2e.8 off end #  GPIO2
-                	                                device pnp 2e.9 off end #  GPIO3
-                	                                device pnp 2e.a off end #  ACPI
-                	                                device pnp 2e.b on #  HW Monitor
-                	                                        io 0x60 = 0x290
-                	                                        irq 0x70 = 5
-                	                                end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on end
-					device pci 1.5 off end
-					device pci 1.6 off end
-                                        register "ide0_enable" = "1"
-                                        register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0 
-			
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-
-	end #pci_domain
-end
-
diff --git a/src/mainboard/tyan/s4880/Options.lb b/src/mainboard/tyan/s4880/Options.lb
deleted file mode 100644
index 05490b7..0000000
--- a/src/mainboard/tyan/s4880/Options.lb
+++ /dev/null
@@ -1,253 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=22
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=8
-default CONFIG_MAX_PHYSICAL_CPUS=4
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=1
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=0
-
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PART_NUMBER="s4880"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb
deleted file mode 100644
index bbb94f2..0000000
--- a/src/mainboard/tyan/s4882/Config.lb
+++ /dev/null
@@ -1,302 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_ROM_PAYLOAD = 1
-
-arch i386 end 
-
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	if CONFIG_USE_INIT
-
-		makerule ./auto.o
-        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-	        	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else
-
-		makerule ./auto.inc
-        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        		action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-			end
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for tyan/s4882
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on end # LDT0
-			device pci 18.0 on #  northbridge 
-				#  devices on link 1, link 1 == LDT 1
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-					device pci 0.0 on 
-#						chip drivers/lsi/53c1030
-#							device pci 4.0 on end
-#							device pci 4.1 on end
-#							register "fw_address" = "0xfff8c000"
-#						end
-                                                device pci 9.0 on end #Broadcom
-                                                device pci 9.1 on end
-					end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-                                                #chip drivers/ati/ragexl
-                                                device pci 6.0 on end
-                                                #end
-                                                device pci 5.0 on end #SiI
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 on #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 on #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	                                device pnp 2e.6 off #  CIR
-                	                                        io 0x60 = 0x100
-                	                                end
-                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
-                	                                        io 0x60 = 0x220
-                	                                        io 0x62 = 0x300
-                	                                        irq 0x70 = 9
-                	                                end  
-                	                                device pnp 2e.8 off end #  GPIO2
-                	                                device pnp 2e.9 off end #  GPIO3
-                	                                device pnp 2e.a off end #  ACPI
-                	                                device pnp 2e.b on #  HW Monitor
-                	                                        io 0x60 = 0x290
-                	                                        irq 0x70 = 5
-                	                                end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-                                        device pci 1.3 on 
-#                                                chip drivers/i2c/i2cmux # pca9556 smbus mux
-#                                                        device i2c 18 on #0 pca9516 2, 1
-#	  					                chip drivers/i2c/lm63 #cpu0 temp
-#                                                                        device i2c 4c on end
-#                                                                end 
-#							end
-#                                                        device i2c 18 on #1 pca9516 1, 1
-#                                                                chip drivers/generic/generic #dimm 1-0-0
-#                                                                        device i2c 50 on end
-#                                                                end
-#                                                                chip drivers/generic/generic #dimm 1-0-1
-#                                                                        device i2c 51 on end
-#                                                                end
-#                                                                chip drivers/generic/generic #dimm 1-1-0
-#                                                                        device i2c 52 on end
-#                                                                end
-#                                                                chip drivers/generic/generic #dimm 1-1-1
-#	                                                                device i2c 53 on end
-#								end
-#                                                        end
-#                                                        device i2c 18 on #2 pca9516 1, 2
-#                                                                chip drivers/generic/generic #dimm 0-0-0
-#                                                                        device i2c 50 on end
-#                                                                end
-#                                                                chip drivers/generic/generic #dimm 0-0-1
-#                                                                        device i2c 51 on end
-#                                                                end
-#                                                                chip drivers/generic/generic #dimm 0-1-0
-#                                                                        device i2c 52 on end
-#                                                                end
-#                                                                chip drivers/generic/generic #dimm 0-1-1
-#                                                                	device i2c 53 on end
-#								end
-#                                                        end
-#                                                        device i2c 18 on #3 pca9516 1, 3
-#                                                                chip drivers/generic/generic #dimm 3-0-0
-#                                                                        device i2c 50 on end
-#                                                                end
-#                                                                chip drivers/generic/generic #dimm 3-0-1
-#                                                                        device i2c 51 on end
-#                                                                end
-#                                                                chip drivers/generic/generic #dimm 3-1-0
-#                                                                        device i2c 52 on end
-#                                                                end
-#                                                                chip drivers/generic/generic #dimm 3-1-1
-#                                                                	device i2c 53 on end
-#								end
-#                                                        end
-#                                                        device i2c 18 on #4 pca9516 1, 4
-#                                                                chip drivers/generic/generic #dimm 2-0-0
-#                                                                        device i2c 50 on end
-#                                                                end
-#                                                                chip drivers/generic/generic #dimm 2-0-1
-#                                                                        device i2c 51 on end
-#                                                                end
-#                                                                chip drivers/generic/generic #dimm 2-1-0
-#                                                                        device i2c 52 on end
-#                                                                end
-#                                                                chip drivers/generic/generic #dimm 2-1-1
-#                                                                	device i2c 53 on end
-#								end
-#                                                        end
-#                                                        device i2c 18 on #5 pca9516 2, 2
-#                                                                chip drivers/i2c/lm63 #cpu1 temp
-#                                                                       device i2c 4c on end
-#                                                                end
-#                                                        end
-#                                                        device i2c 18 on #6 pca9516 2, 3
-#                                                                chip drivers/i2c/lm63 #cpu2 temp
-#                                                                        device i2c 4c on end
-#                                                                end
-#                                                        end
-#                                                        device i2c 18 on #7 pca9516 2, 4
-#                                                                chip drivers/i2c/lm63 #cpu3 temp
-#                                                                        device i2c 4c on end
-#                                                                end
-#                                                        end
-#                                                end # i2cmux
-#                                                chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN...
-#                                                        device i2c 2e on end
-#                                                end
-#                                                chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid 
-#                                                        device i2c 2a on end
-#                                                end
-#                                                chip drivers/generic/generic # Winbond HWM 0x92
-#                                                        device i2c 49 on end
-#                                                end
-#                                                chip drivers/generic/generic # Winbond HWM 0x94
-#                                                        device i2c 4a on end
-#                                                end
-#                                                chip drivers/generic/generic # ??
-#                                                        device i2c 69 on end
-#                                                end
-                                        end # acpi
-					device pci 1.5 off end
-					device pci 1.6 off end
-					register "ide0_enable" = "1"
-                                        register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0 
-			
-                	device pci 18.0 on end
-			
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-
-	end 
-#        chip drivers/generic/debug
-#                device pnp 0.0 off end # chip name
-#                device pnp 0.1 off end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 on end # cpuid
-#                device pnp 0.4 off end # smbus_regs_all
-#		device pnp 0.5 on end # dual core msr
-#		device pnp 0.6 on end # cache size
-#		device pnp 0.7 on end # tsc
-#        end
-end
-
diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb
deleted file mode 100644
index 820fc3b..0000000
--- a/src/mainboard/tyan/s4882/Options.lb
+++ /dev/null
@@ -1,252 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=22
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=8
-default CONFIG_MAX_PHYSICAL_CPUS=4
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-#default CONFIG_CONSOLE_VGA=1
-#default CONFIG_PCI_ROM_RUN=1
-
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=1
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_VENDOR="Tyan"
-default CONFIG_MAINBOARD_PART_NUMBER="s4882"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00002000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/via/epia-cn/Config.lb b/src/mainboard/via/epia-cn/Config.lb
deleted file mode 100644
index 42d62cb..0000000
--- a/src/mainboard/via/epia-cn/Config.lb
+++ /dev/null
@@ -1,135 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object dsdt.o
-	object acpi_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-chip northbridge/via/cn700			# Northbridge
-  device pci_domain 0 on			# PCI domain
-    device pci 0.0 on end			# AGP Bridge
-    device pci 0.1 on end			# Error Reporting
-    device pci 0.2 on end			# Host Bus Control
-    device pci 0.3 on end			# Memory Controller
-    device pci 0.4 on end			# Power Management
-    device pci 0.7 on end			# V-Link Controller
-    device pci 1.0 on end			# PCI Bridge
-    chip southbridge/via/vt8237r		# Southbridge
-      # Enable both IDE channels.
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      # Both cables are 40pin.
-      register "ide0_80pin_cable" = "0"
-      register "ide1_80pin_cable" = "0"
-      device pci f.0 on end			# IDE
-      register "fn_ctrl_lo" = "0x80"
-      register "fn_ctrl_hi" = "0x1d"
-      device pci 10.0 on end			# OHCI
-      device pci 10.1 on end			# OHCI
-      device pci 10.2 on end			# OHCI
-      device pci 10.3 on end			# OHCI
-      device pci 10.4 on end			# EHCI
-      device pci 10.5 on end			# UDCI
-      device pci 11.0 on			# Southbridge LPC
-        chip superio/via/vt1211			# Super I/O
-          device pnp 2e.0 off			# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on			# Parallel Port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 2e.2 on			# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.3 on			# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.b on			# HWM
-            io 0x60 = 0xec00
-          end
-        end
-      end
-      device pci 11.5 on end			# AC'97 audio
-      # device pci 11.6 off end			# AC'97 Modem
-      device pci 12.0 on end			# Ethernet
-    end
-  end
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/via/model_c7			# VIA C7
-      device apic 0 on end			# APIC
-    end
-  end
-end
diff --git a/src/mainboard/via/epia-cn/Options.lb b/src/mainboard/via/epia-cn/Options.lb
deleted file mode 100644
index 718c75d..0000000
--- a/src/mainboard/via/epia-cn/Options.lb
+++ /dev/null
@@ -1,98 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_VIDEO_MB
-uses CONFIG_IOAPIC
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_IOAPIC = 1
-default CONFIG_VIDEO_MB = 32
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 9
-default CONFIG_GENERATE_ACPI_TABLES = 0
-default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_USE_FALLBACK_IMAGE = 1
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default HOSTCC = "gcc"
-
-end
diff --git a/src/mainboard/via/epia-m/Config.lb b/src/mainboard/via/epia-m/Config.lb
deleted file mode 100644
index 011ce5a..0000000
--- a/src/mainboard/via/epia-m/Config.lb
+++ /dev/null
@@ -1,159 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-object vgabios.o
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object dsdt.o
-	object acpi_tables.o
-end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/via/vt8623
-
-	device apic_cluster 0 on
-		chip cpu/via/model_c3
-			device apic 0 on  end 
-		end
-	end
-
-	device pci_domain 0 on
-		chip southbridge/via/vt8235
-
-			device pci 10.0 on end # USB 1.1
-			device pci 10.1 on end # USB 1.1
-			device pci 10.2 on end # USB 1.1
-			device pci 10.3 on end # USB 2
-
-			device pci 11.0 on      # Southbridge
-				chip superio/via/vt1211
-					device pnp 2e.0 on	# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.1 on	# Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-						drq 0x74 = 3
-					end
-					device pnp 2e.2 on	# COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on	# COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.b on	# HWM
-						io 0x60 = 0xec00
-					end
-
-				end
-			end
-			
-			device pci 11.1 on  end # IDE
-			# 2-4 non existant?
-			device pci 11.5 on  end # AC97 Audio
-			device pci 11.6 off end # AC97 Modem
-			device pci 12.0 on end  # Ethernet
-		end
-#		This is on the EPIA MII, not the M.
-		chip southbridge/ricoh/rl5c476
-			register "enable_cf" = "1"
-			device pci 0a.0 on end
-			device pci 0a.1 on end	
-		end
-	end
-end
diff --git a/src/mainboard/via/epia-m/Options.lb b/src/mainboard/via/epia-m/Options.lb
deleted file mode 100644
index 4583331..0000000
--- a/src/mainboard/via/epia-m/Options.lb
+++ /dev/null
@@ -1,135 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-default CONFIG_PCI_ROM_RUN=0
-default CONFIG_CONSOLE_VGA=0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Use TSC for udelay.
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=5
-
-
-##
-## Build code to load acpi tables
-##
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-default  CONFIG_CONSOLE_SERIAL8250=1
-end
diff --git a/src/mainboard/via/epia-m700/Config.lb b/src/mainboard/via/epia-m700/Config.lb
deleted file mode 100644
index d7d7cbe..0000000
--- a/src/mainboard/via/epia-m700/Config.lb
+++ /dev/null
@@ -1,165 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 One Laptop per Child, Association, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-driver wakeup.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_ACPI_TABLES
-  object fadt.o
-  object dsdt.o
-  # object ssdt.o
-  object acpi_tables.o
-end
-# These lines maybe noused.
-makerule ./failover.E
-  depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-  action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-  depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-  action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-if CONFIG_USE_DCACHE_RAM
-  if CONFIG_USE_INIT
-    makerule ./cache_as_ram_auto.o
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
-    end
-  else
-    makerule ./cache_as_ram_auto.inc
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
-      action "perl -e 's/.rodata/.rom.data/g' -pi $@"
-      action "perl -e 's/.text/.section .rom.text/g' -pi $@"
-    end
-  end
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-ldscript /cpu/x86/16bit/entry16.lds
-
-mainboardinit northbridge/via/vx800/romstrap.inc
-ldscript /northbridge/via/vx800/romstrap.lds
-
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-  mainboardinit cpu/x86/16bit/reset16.inc
-  ldscript /cpu/x86/16bit/reset16.lds
-else
-  mainboardinit cpu/x86/32bit/reset32.inc
-  ldscript /cpu/x86/32bit/reset32.lds
-end
-
-# mainboardinit arch/i386/lib/cpu_reset.inc
-# Here cpu_reset.inc have label _cpu_reset, which is needed in failover.c,
-# but cpu_reset.inc also has code to jump to __main() which is not included
-# in cache_as_ram_auto_auto.c.
-
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-if CONFIG_USE_DCACHE_RAM
-  mainboardinit cpu/via/car/cache_as_ram.inc
-end
-
-if CONFIG_USE_FALLBACK_IMAGE
-  ldscript /arch/i386/lib/failover.lds
-  # failover.inc need definition in cpu_reset.inc, but we do not include
-  # cpu_reset.inc,so ...
-  # mainboardinit ./failover.inc
-end
-# mainboardinit cpu/x86/fpu_enable.inc
-
-if CONFIG_USE_DCACHE_RAM
-  if CONFIG_USE_INIT
-    initobject cache_as_ram_auto.o
-  else
-    mainboardinit ./cache_as_ram_auto.inc
-  end
-end
-
-# mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-
-config chip.h
-
-chip northbridge/via/vx800	# Northbridge
-  device pci_domain 0 on
-    device pci 0.0 on end	# Host Bridge
-    device pci 0.1 on end	# Error Reporting
-    device pci 0.2 on end	# Host Bus Control
-    device pci 0.3 on end	# PCI to PCI Bridge
-    device pci 0.4 on end	# Power Management
-    device pci 0.5 on end	# APIC and Central Traffic Control
-    device pci 0.6 on end	# Scratch Registers
-    device pci 0.7 on end	# North-South Module Interface Control
-    device pci 1.0 on end	# PCI Bridge
-    device pci f.0 on end	# IDE/SATA
-    # device pci f.1 on end	# IDE
-    device pci 10.0 on end	# USB 1.1
-    device pci 10.1 on end	# USB 1.1
-    device pci 10.2 on end	# USB 1.1
-    device pci 10.4 on end	# USB 2.0
-    device pci 11.0 on		# Bus Control and Power Management (SB, LPC)
-      chip superio/winbond/w83697hf
-	# TODO: Check all devices, this may need some more work.
-        device pnp 2e.0 off                   # Floppy (N/A?)
-          io 0x60 = 0x3f0
-          irq 0x70 = 6
-          drq 0x74 = 2
-        end
-        device pnp 2e.1 off                   # Parallel Port (N/A?)
-          io 0x60 = 0x378
-          irq 0x70 = 7
-          drq 0x74 = 4
-        end
-        device pnp 2e.2 on                    # COM1
-          io 0x60 = 0x3f8
-          irq 0x70 = 4
-        end
-        device pnp 2e.3 on                    # COM2
-          io 0x60 = 0x2f8
-          irq 0x70 = 3
-        end
-        device pnp 2e.6 off end               # Consumer IR
-        device pnp 2e.7 off end               # Game port, GPIO 1
-        device pnp 2e.8 off end               # MIDI port, GPIO 5
-        device pnp 2e.9 off end               # GPIO 2-4
-        device pnp 2e.a off end               # ACPI
-        device pnp 2e.b on                    # HWM
-          io 0x60 = 0x290
-        end
-      end
-    end
-    device pci 11.7 on end	# North-South Module Interface Control
-    device pci 14.0 on end	# HD Audio (Azalia)
-  end
-  device apic_cluster 0 on	# APIC cluster
-    chip cpu/via/model_c7	# VIA C7
-      device apic 0 on end	# APIC
-    end
-  end
-end
diff --git a/src/mainboard/via/epia-m700/Options.lb b/src/mainboard/via/epia-m700/Options.lb
deleted file mode 100644
index fffa550..0000000
--- a/src/mainboard/via/epia-m700/Options.lb
+++ /dev/null
@@ -1,138 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 One Laptop per Child, Association, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_VIDEO_MB
-uses CONFIG_IOAPIC
-
-## New options
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-#uses MAX_RAM_SLOTS
-#uses USB_ENABLE
-#uses EHCI_ENABLE
-#uses HPET_ENABLE
-#uses USB_PORTNUM
-#uses FULL_ROM_SIZE
-#uses FULL_ROM_BASE
-#uses PAYLOAD_IS_SEABIOS
-#uses VIACONFIG_TOP_SM_SIZE_MB
-#uses VIACONFIG_VGA_PCI_10
-#uses VIACONFIG_VGA_PCI_14
-
-## New options
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xffef0000
-# default CONFIG_DCACHE_RAM_BASE = 0xffbf0000
-# default CONFIG_DCACHE_RAM_BASE = 0xfec00000 # HPET may use this.
-default CONFIG_DCACHE_RAM_SIZE = 8 * 1024
-default CONFIG_USE_INIT = 0
-#default MAX_RAM_SLOTS = 2
-#default USB_ENABLE = 1
-#default EHCI_ENABLE = 1
-#default HPET_ENABLE = 1
-#default USB_PORTNUM = 2
-#default FULL_ROM_SIZE = 512 * 1024
-#default FULL_ROM_BASE = (0xffffffff - FULL_ROM_SIZE + 1)
-#default VIACONFIG_TOP_SM_SIZE_MB = 0
-# default VIACONFIG_VGA_PCI_10 = 0xd0000008
-# default VIACONFIG_VGA_PCI_14 = 0xfd000000
-#default VIACONFIG_VGA_PCI_10 = 0xf8000008
-#default VIACONFIG_VGA_PCI_14 = 0xfc000000
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_IOAPIC = 1
-
-# Define framebuffer size of VX800's integrated graphics card.
-# Supports: 32, 64, 128, 256.
-default CONFIG_VIDEO_MB = 64
-
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_HARD_RESET = 0
-# TODO: There is an irq_tables.c file, should it be used?
-default CONFIG_GENERATE_PIRQ_TABLE = 0
-default CONFIG_IRQ_SLOT_COUNT = 13
-default CONFIG_GENERATE_ACPI_TABLES = 1
-default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_USE_FALLBACK_IMAGE = 1
-default CONFIG_STACK_SIZE = 16 * 1024
-default CONFIG_HEAP_SIZE = 20 * 1024
-# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-end
diff --git a/src/mainboard/via/epia-n/Config.lb b/src/mainboard/via/epia-n/Config.lb
deleted file mode 100644
index ac0ef8b..0000000
--- a/src/mainboard/via/epia-n/Config.lb
+++ /dev/null
@@ -1,202 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-#object vgabios.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-
-if CONFIG_GENERATE_ACPI_TABLES
-#acpi_create_fadt is located in VT8237R code
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dsdt.asl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-	object acpi_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/via/cn400			# Northbridge
-
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/via/model_c3			# VIA C3
-      device apic 0 on end			# APIC
-    end
-  end
-
-  device pci_domain 0 on			# PCI domain
-    device pci 0.0 on end			# AGP Bridge
-    device pci 0.1 on end			# Error Reporting
-    device pci 0.2 on end			# Host Bus Control
-    device pci 0.3 on end			# Memory Controller
-    device pci 0.4 on end			# Power Management
-    device pci 0.7 on end			# V-Link Controller
-    device pci 1.0 on end			# PCI Bridge
-    chip southbridge/via/vt8237r		# Southbridge
-      # Enable both IDE channels.
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      # Both cables are 40pin.
-      register "ide0_80pin_cable" = "0"
-      register "ide1_80pin_cable" = "0"
-      device pci f.0 on end			# IDE/SATA
-	  device pci f.1 on end			# IDE
-      register "fn_ctrl_lo" = "0xC0"    # Disable AC/MC97
-      register "fn_ctrl_hi" = "0x9d"    # Disable USB Direct & LAN Gating
-      device pci 10.0 on end			# OHCI
-      device pci 10.1 on end			# OHCI
-      device pci 10.2 on end			# OHCI
-      device pci 10.3 on end			# OHCI
-      device pci 10.4 on end			# EHCI
-      device pci 10.5 off end			# USB Direct
-      device pci 11.0 on			# Southbridge LPC
-        chip superio/winbond/w83697hf		# Super I/O
-          device pnp 2e.0 off			# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 off			# Parallel Port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 2e.2 on			# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.3 off			# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.6 off			# IR Port
-            io 0x60 = 0x000
-          end
-          device pnp 2e.7 off			# GPIO 1
-            io 0x60 = 0x201			# 0x201
-          end
-          device pnp 2e.8 off			# GPIO 5
-            io 0x60 = 0x330			# 0x330
-          end
-          device pnp 2e.9 off			# GPIO 2, 3,and 4
-            io 0x60 = 0x000			#
-          end
-          device pnp 2e.a off			# ACPI
-            io 0x60 = 0x000			#
-          end
-          device pnp 2e.b on			# HWM
-            io 0x60 = 0x290
-			irq 0x70 = 0
-          end
-        end
-      end
-      device pci 11.5 off end			# AC'97 audio
-      device pci 11.6 off end			# AC'97 Modem
-      device pci 12.0 on end			# Ethernet
-    end
-  end
-end
diff --git a/src/mainboard/via/epia-n/Options.lb b/src/mainboard/via/epia-n/Options.lb
deleted file mode 100644
index 416b812..0000000
--- a/src/mainboard/via/epia-n/Options.lb
+++ /dev/null
@@ -1,113 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_RAMTOP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_SMP
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_VIDEO_MB
-uses CONFIG_IOAPIC
-uses CONFIG_COMPRESS
-uses CONFIG_EPIA_VT8237R_INIT
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-default CONFIG_EPIA_VT8237R_INIT = 1
-#default CONFIG_RAMTOP = 4 * 1024*1024
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_COMPRESS = 1
-default CONFIG_IOAPIC = 1
-default CONFIG_VIDEO_MB = 64
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_HAVE_FAILOVER_BOOT = 0
-default CONFIG_USE_FAILOVER_IMAGE = 0
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_SMP = 1
-default CONFIG_GENERATE_MP_TABLE = 1
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7
-default CONFIG_GENERATE_ACPI_TABLES = 1
-default CONFIG_HAVE_OPTION_TABLE = 1
-#default CONFIG_ROM_IMAGE_SIZE = 67 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_USE_FALLBACK_IMAGE = 1
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default HOSTCC = "gcc"
-#default CONFIG_MAINBOARD = "EPIA-N"
-default CONFIG_HAVE_MAINBOARD_RESOURCES = 1
-
-end
diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb
deleted file mode 100644
index c75c21e..0000000
--- a/src/mainboard/via/epia/Config.lb
+++ /dev/null
@@ -1,156 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/via/vt8601
-	device pci_domain 0 on
-    		device pci 0.0 on end			# Northbridge
-#		device pci 0.1 on			# AGP bridge
-		#	device pci 0.0 on end		# Integrated VGA
-#		end
-		chip southbridge/via/vt8231
-			register "enable_native_ide" = "0"
-			register "enable_com_ports" = "1"
-			register "enable_keyboard" = "0"
-			device pci 11.0 on              # Southbrdge
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 on      #  Floppy
-					   io 0x60 = 0x3f0
-					  irq 0x70 = 6
-					  drq 0x74 = 2
-					end
-					device pnp 2e.1 off     #  Parallel Port
-					   io 0x60 = 0x378
-					  irq 0x70 = 7
-					end
-					device pnp 2e.2 on      #  Com1
-					   io 0x60 = 0x3f8
-					  irq 0x70 = 4
-					end
-					device pnp 2e.3 off     #  Com2
-					   io 0x60 = 0x2f8
-					  irq 0x70 = 3
-					end
-					device pnp 2e.5 on      #  Keyboard
-					   io 0x60 = 0x60
-					   io 0x62 = 0x64
-					  irq 0x70 = 1
-					  irq 0x72 = 12
-	      				end
-				register "com1" = "{CONFIG_TTYS0_BAUD}"
-				end
-				device pnp 2e.6 off end 	#  CIR
-				device pnp 2e.7 off end 	#  GAME_MIDI_GIPO1
-				device pnp 2e.8 off end		#  GPIO2
-				device pnp 2e.9 off end 	#  GPIO3
-				device pnp 2e.a off end		#  ACPI
-				device pnp 2e.b on		#  HW Monitor
-					io 0x60 = 0x290
-				end
-			end
-			device pci 11.1 on  end		# Ide
-			device pci 11.2 off end		# Usb port 0-1
-			device pci 11.3 off end		# Usb port 2-3
-			device pci 11.4 off end		# ACPI
-			device pci 11.5 off end		# AC97 Audio
-			device pci 11.6 on  end		# AC97 Modem
-          		device pci 12.0 on  end		# Ethernet
-        	end
-	end
-
-        device apic_cluster 0 on
-                chip cpu/via/model_c3
-                        device apic 0 on end
-                end
-        end
-end
diff --git a/src/mainboard/via/epia/Options.lb b/src/mainboard/via/epia/Options.lb
deleted file mode 100644
index 466ffcc..0000000
--- a/src/mainboard/via/epia/Options.lb
+++ /dev/null
@@ -1,143 +0,0 @@
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_UDELAY_IO
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-
-# logging
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-
-# logging
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-
-default CONFIG_CONSOLE_SERIAL8250=1
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-                                                                                
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-##
-## use io based udelay function
-## disable IO and enable TSC on Nehemiah boards
-##
-default CONFIG_UDELAY_IO=1
-default CONFIG_UDELAY_TSC=0
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=5
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-end
diff --git a/src/mainboard/via/pc2500e/Config.lb b/src/mainboard/via/pc2500e/Config.lb
deleted file mode 100644
index 01c2266..0000000
--- a/src/mainboard/via/pc2500e/Config.lb
+++ /dev/null
@@ -1,161 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object dsdt.o
-	object acpi_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-chip northbridge/via/cn700			# Northbridge
-  device pci_domain 0 on			# PCI domain
-    device pci 0.0 on end			# AGP Bridge
-    device pci 0.1 on end			# Error Reporting
-    device pci 0.2 on end			# Host Bus Control
-    device pci 0.3 on end			# Memory Controller
-    device pci 0.4 on end			# Power Management
-    device pci 0.7 on end			# V-Link Controller
-    device pci 1.0 on end			# PCI Bridge
-    chip southbridge/via/vt8237r		# Southbridge
-      # Enable both IDE channels.
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      # Both cables are 40pin.
-      register "ide0_80pin_cable" = "0"
-      register "ide1_80pin_cable" = "0"
-      device pci f.0 on end			# SATA
-      device pci f.1 on end			# IDE
-      register "fn_ctrl_lo" = "0x80"
-      register "fn_ctrl_hi" = "0x1d"
-      device pci 10.0 on end			# UHCI
-      device pci 10.1 on end			# UHCI
-      device pci 10.2 on end			# UHCI
-      device pci 10.3 on end			# UHCI
-      device pci 10.4 on end			# EHCI
-      device pci 10.5 on end			# UDCI
-      device pci 11.0 on			# Southbridge LPC
-        chip superio/ite/it8716f		# Super I/O
-          device pnp 2e.0 on			# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on			# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.2 off			# COM2 (N/A on this board)
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.3 on			# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 2e.4 on			# Environment controller
-            io 0x60 = 0x290
-            io 0x62 = 0x0000
-            irq 0x70 = 9
-          end
-          device pnp 2e.5 off			# PS/2 keyboard (not used)
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.6 off			# PS/2 mouse (not used)
-            irq 0x70 = 12
-          end
-          device pnp 2e.7 on			# GPIO
-            io 0x60 = 0x0000
-            io 0x62 = 0x0800
-            io 0x64 = 0x0000
-          end
-          device pnp 2e.8 off			# MIDI port (N/A)
-            io 0x60 = 0x300
-            irq 0x70 = 10
-          end
-          device pnp 2e.9 off			# Game port (N/A)
-            io 0x60 = 0x201
-          end
-          device pnp 2e.a on			# Consumer IR
-            io 0x60 = 0x310
-            irq 0x70 = 11
-          end
-        end
-      end
-      device pci 11.5 on end			# AC'97 audio
-      # device pci 11.6 off end			# AC'97 modem (N/A)
-      device pci 12.0 on end			# Ethernet
-    end
-  end
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/via/model_c7			# VIA C7
-      device apic 0 on end			# APIC
-    end
-  end
-end
diff --git a/src/mainboard/via/pc2500e/Options.lb b/src/mainboard/via/pc2500e/Options.lb
deleted file mode 100644
index 9e48960..0000000
--- a/src/mainboard/via/pc2500e/Options.lb
+++ /dev/null
@@ -1,109 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_SMP
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_VIDEO_MB
-uses CONFIG_IOAPIC
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_IOAPIC = 1
-default CONFIG_VIDEO_MB = 32
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_SMP = 1
-default CONFIG_GENERATE_MP_TABLE = 1
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 10
-default CONFIG_GENERATE_ACPI_TABLES = 0
-default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_USE_FALLBACK_IMAGE = 1
-default CONFIG_MAINBOARD_VENDOR = "VIA"
-default CONFIG_MAINBOARD_PART_NUMBER = "pc2500e"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0xaa51
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 1
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-end
diff --git a/src/mainboard/via/vt8454c/Config.lb b/src/mainboard/via/vt8454c/Config.lb
deleted file mode 100644
index 6faa33c..0000000
--- a/src/mainboard/via/vt8454c/Config.lb
+++ /dev/null
@@ -1,163 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_MP_TABLE 
-	object mptable.o 
-end
-
-if CONFIG_GENERATE_PIRQ_TABLE 
-	object irq_tables.o 
-end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object acpi_tables.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
-		action  "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-##
-## Romcc output
-##
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
-	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-mainboardinit cpu/via/car/cache_as_ram.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/via/cx700
-	device apic_cluster 0 on
-		chip cpu/via/model_c7
-			device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		device pci 0.0 on end # AGP Bridge
-		device pci 0.1 on end # Error Reporting
-		device pci 0.2 on end # Host Bus Control
-		device pci 0.3 on end # Memory Controller
-		device pci 0.4 on end # Power Management
-		device pci 0.7 on end # V-Link Controller
-		device pci 1.0 on     # PCI Bridge
-			device pci 0.0 on end # Onboard Video
-		end # PCI Bridge
-		device pci f.0 on end # IDE/SATA
-		#device pci f.1 on end # IDE
-		device pci 10.0 on end # USB 1.1
-		device pci 10.1 on end # USB 1.1
-		device pci 10.2 on end # USB 1.1
-		device pci 10.4 on end # USB 2.0
-		device pci 11.0 on      # Southbridge LPC
-			chip superio/via/vt1211
-				device pnp 2e.0 on	# Floppy
-					io 0x60 = 0x3f0
-					irq 0x70 = 6
-					drq 0x74 = 2
-				end
-				device pnp 2e.1 on	# Parallel Port
-					io 0x60 = 0x378
-					irq 0x70 = 7
-					drq 0x74 = 3
-				end
-				device pnp 2e.2 on	# COM1
-					io 0x60 = 0x3f8
-					irq 0x70 = 4
-				end
-				device pnp 2e.3 on	# COM2
-					io 0x60 = 0x2f8
-					irq 0x70 = 3
-				end
-				device pnp 2e.b on	# HWM
-					io 0x60 = 0xec00
-				end
-			end # superio
-		end # pci 11.0
-		# 1-4 non existant
-		#device pci 11.5 on end # AC97 Audio
-		#device pci 11.6 off end # AC97 Modem
-		#device pci 12.0 on end  # Ethernet
-	end # pci domain 0
-end # cx700
-
diff --git a/src/mainboard/via/vt8454c/Options.lb b/src/mainboard/via/vt8454c/Options.lb
deleted file mode 100644
index cb796ca..0000000
--- a/src/mainboard/via/vt8454c/Options.lb
+++ /dev/null
@@ -1,233 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_HAVE_LOW_TABLES
-
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-
-uses CONFIG_COMPRESS
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-
-# compiler specifics
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-
-# Console specifics
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_SMP
-uses CONFIG_IOAPIC
-
-uses CONFIG_GDB_STUB
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xffef0000
-#default CONFIG_DCACHE_RAM_BASE=0xffbf0000
-#default CONFIG_DCACHE_RAM_BASE=0xfec00000
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-###
-### Leave this to 0; VGA is handled by seperate code.
-###
-default CONFIG_PCI_ROM_RUN=0
-default CONFIG_CONSOLE_VGA=0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Use TSC for udelay.
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=15
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to load acpi tables
-##
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Build code to fill in tables both in low and high memory
-##
-default CONFIG_HAVE_LOW_TABLES=1
-
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_SMP=1
-default CONFIG_IOAPIC=1
-
-###
-### LinuxBIOS layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-## Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
-end
-
diff --git a/src/northbridge/amd/amdfam10/Config.lb b/src/northbridge/amd/amdfam10/Config.lb
deleted file mode 100644
index 27c3625..0000000
--- a/src/northbridge/amd/amdfam10/Config.lb
+++ /dev/null
@@ -1,78 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-uses CONFIG_AGP_APERTURE_SIZE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_WRITE_HIGH_TABLES
-
-default CONFIG_AGP_APERTURE_SIZE=0x4000000
-default CONFIG_WRITE_HIGH_TABLES=1
-
-config chip.h
-
-driver northbridge.o
-driver misc_control.o
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object amdfam10_acpi.o
-	makerule ssdt.c
-		depends "$(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl"
-		action	 "iasl -p $(CURDIR)/ssdt -tc $(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl"
-		action	 "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex"
-		action	 "mv ssdt.hex ssdt.c"
-	end
-	object ./ssdt.o
-	makerule sspr1.c
-		depends "$(TOP)/src/northbridge/amd/amdfam10/sspr1.dsl"
-		action	 "iasl -p $(CURDIR)/sspr1 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr1.dsl"
-		action	 "perl -pi -e 's/AmlCode/AmlCode_sspr1/g' sspr1.hex"
-		action	 "mv sspr1.hex sspr1.c"
-	end
-	object ./sspr1.o
-	makerule sspr2.c
-		depends "$(TOP)/src/northbridge/amd/amdfam10/sspr2.dsl"
-		action	 "iasl -p $(CURDIR)/sspr2 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr2.dsl"
-		action	 "perl -pi -e 's/AmlCode/AmlCode_sspr2/g' sspr2.hex"
-		action	 "mv sspr2.hex sspr2.c"
-	end
-	object ./sspr2.o
-	makerule sspr3.c
-		depends "$(TOP)/src/northbridge/amd/amdfam10/sspr3.dsl"
-		action	 "iasl -p $(CURDIR)/sspr3 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr3.dsl"
-		action	 "perl -pi -e 's/AmlCode/AmlCode_sspr3/g' sspr3.hex"
-		action	 "mv sspr3.hex sspr3.c"
-	end
-	object ./sspr3.o
-	makerule sspr4.c
-		depends "$(TOP)/src/northbridge/amd/amdfam10/sspr4.dsl"
-		action	 "iasl -p $(CURDIR)/sspr4 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr4.dsl"
-		action	 "perl -pi -e 's/AmlCode/AmlCode_sspr4/g' sspr4.hex"
-		action	 "mv sspr4.hex sspr4.c"
-	end
-	object ./sspr4.o
-	makerule sspr5.c
-		depends "$(TOP)/src/northbridge/amd/amdfam10/sspr5.dsl"
-		action	 "iasl -p $(CURDIR)/sspr5 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr5.dsl"
-		action	 "perl -pi -e 's/AmlCode/AmlCode_sspr5/g' sspr5.hex"
-		action	 "mv sspr5.hex sspr5.c"
-	end
-	object ./sspr5.o
-end
-
-object get_pci1234.o
diff --git a/src/northbridge/amd/amdfam10/root_complex/Config.lb b/src/northbridge/amd/amdfam10/root_complex/Config.lb
deleted file mode 100644
index 610e929..0000000
--- a/src/northbridge/amd/amdfam10/root_complex/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-config chip.h
diff --git a/src/northbridge/amd/amdk8/Config.lb b/src/northbridge/amd/amdk8/Config.lb
deleted file mode 100644
index d9a3ac5..0000000
--- a/src/northbridge/amd/amdk8/Config.lb
+++ /dev/null
@@ -1,38 +0,0 @@
-uses CONFIG_AGP_APERTURE_SIZE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_WRITE_HIGH_TABLES
-uses CONFIG_K8_REV_F_SUPPORT
-
-default CONFIG_AGP_APERTURE_SIZE=0x4000000
-default CONFIG_WRITE_HIGH_TABLES=1
-
-config chip.h
-
-driver northbridge.o
-driver misc_control.o
-
-if CONFIG_K8_REV_F_SUPPORT
-
-makerule raminit_test
-	depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c"
-	depends "$(TOP)/src/northbridge/amd/amdk8/raminit_f.c"
-	action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g  $< -o $@"
-end
-
-else
-
-makerule raminit_test
-	depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c"
-	depends "$(TOP)/src/northbridge/amd/amdk8/raminit.c"
-	action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g  $< -o $@"
-end
-
-end
-
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object amdk8_acpi.o
-end
-
-
-object get_sblk_pci1234.o
diff --git a/src/northbridge/amd/amdk8/root_complex/Config.lb b/src/northbridge/amd/amdk8/root_complex/Config.lb
deleted file mode 100644
index 610e929..0000000
--- a/src/northbridge/amd/amdk8/root_complex/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-config chip.h
diff --git a/src/northbridge/amd/gx1/Config.lb b/src/northbridge/amd/gx1/Config.lb
deleted file mode 100644
index 55a986e..0000000
--- a/src/northbridge/amd/gx1/Config.lb
+++ /dev/null
@@ -1,4 +0,0 @@
-uses CONFIG_WRITE_HIGH_TABLES
-config chip.h
-driver northbridge.o
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/amd/gx2/Config.lb b/src/northbridge/amd/gx2/Config.lb
deleted file mode 100644
index 0bba6ce..0000000
--- a/src/northbridge/amd/gx2/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-uses CONFIG_WRITE_HIGH_TABLES
-config chip.h
-driver northbridge.o
-object northbridgeinit.o
-object chipsetinit.o
-object grphinit.o
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/amd/lx/Config.lb b/src/northbridge/amd/lx/Config.lb
deleted file mode 100644
index 23d466f..0000000
--- a/src/northbridge/amd/lx/Config.lb
+++ /dev/null
@@ -1,6 +0,0 @@
-uses CONFIG_WRITE_HIGH_TABLES
-config chip.h
-driver northbridge.o
-object northbridgeinit.o
-object grphinit.o
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/e7501/Config.lb b/src/northbridge/intel/e7501/Config.lb
deleted file mode 100644
index 267986d..0000000
--- a/src/northbridge/intel/e7501/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-
-object northbridge.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/e7520/Config.lb b/src/northbridge/intel/e7520/Config.lb
deleted file mode 100644
index fdd7560..0000000
--- a/src/northbridge/intel/e7520/Config.lb
+++ /dev/null
@@ -1,11 +0,0 @@
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-driver northbridge.o
-driver pciexp_porta.o
-driver pciexp_porta1.o
-driver pciexp_portb.o
-driver pciexp_portc.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
-
diff --git a/src/northbridge/intel/e7525/Config.lb b/src/northbridge/intel/e7525/Config.lb
deleted file mode 100644
index fdd7560..0000000
--- a/src/northbridge/intel/e7525/Config.lb
+++ /dev/null
@@ -1,11 +0,0 @@
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-driver northbridge.o
-driver pciexp_porta.o
-driver pciexp_porta1.o
-driver pciexp_portb.o
-driver pciexp_portc.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
-
diff --git a/src/northbridge/intel/i3100/Config.lb b/src/northbridge/intel/i3100/Config.lb
deleted file mode 100644
index 3bbe0f2..0000000
--- a/src/northbridge/intel/i3100/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-
-driver northbridge.o
-driver pciexp_porta.o
-driver pciexp_porta_ep80579.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/i440bx/Config.lb b/src/northbridge/intel/i440bx/Config.lb
deleted file mode 100644
index fb23caa..0000000
--- a/src/northbridge/intel/i440bx/Config.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-
-driver northbridge.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/i440lx/Config.lb b/src/northbridge/intel/i440lx/Config.lb
deleted file mode 100644
index fb23caa..0000000
--- a/src/northbridge/intel/i440lx/Config.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-
-driver northbridge.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/i82810/Config.lb b/src/northbridge/intel/i82810/Config.lb
deleted file mode 100644
index 27dcc62..0000000
--- a/src/northbridge/intel/i82810/Config.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-
-driver northbridge.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/i82830/Config.lb b/src/northbridge/intel/i82830/Config.lb
deleted file mode 100644
index f1bd3b9..0000000
--- a/src/northbridge/intel/i82830/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-
-driver northbridge.o
-driver vga.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/i855gme/Config.lb b/src/northbridge/intel/i855gme/Config.lb
deleted file mode 100644
index 861a91d..0000000
--- a/src/northbridge/intel/i855gme/Config.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Jon Dufresne <jon.dufresne@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-
-object northbridge.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/i855pm/Config.lb b/src/northbridge/intel/i855pm/Config.lb
deleted file mode 100644
index 267986d..0000000
--- a/src/northbridge/intel/i855pm/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-
-object northbridge.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/i945/Config.lb b/src/northbridge/intel/i945/Config.lb
deleted file mode 100644
index 8d2d861..0000000
--- a/src/northbridge/intel/i945/Config.lb
+++ /dev/null
@@ -1,29 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007-2009 coresystems GmbH
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-uses CONFIG_WRITE_HIGH_TABLES
-
-default CONFIG_WRITE_HIGH_TABLES=1
-
-config chip.h
-
-object acpi.o
-
-driver northbridge.o
-driver gma.o
diff --git a/src/northbridge/via/cn400/Config.lb b/src/northbridge/via/cn400/Config.lb
deleted file mode 100644
index 2f89072..0000000
--- a/src/northbridge/via/cn400/Config.lb
+++ /dev/null
@@ -1,33 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_WRITE_HIGH_TABLES
-uses CONFIG_IOAPIC
-
-config chip.h
-
-object vgabios.o
-
-driver northbridge.o
-driver agp.o
-driver vga.o
-driver vlink.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/via/cn700/Config.lb b/src/northbridge/via/cn700/Config.lb
deleted file mode 100644
index da312e6..0000000
--- a/src/northbridge/via/cn700/Config.lb
+++ /dev/null
@@ -1,31 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-
-object vgabios.o
-
-driver northbridge.o
-driver agp.o
-driver vga.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/via/cx700/Config.lb b/src/northbridge/via/cx700/Config.lb
deleted file mode 100644
index 347069e..0000000
--- a/src/northbridge/via/cx700/Config.lb
+++ /dev/null
@@ -1,31 +0,0 @@
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-
-object cx700_reset.o
-object northbridge.o
-object vgabios.o
-
-driver cx700_agp.o
-driver cx700_lpc.o
-driver cx700_sata.o
-driver cx700_vga.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/via/vt8601/Config.lb b/src/northbridge/via/vt8601/Config.lb
deleted file mode 100644
index 79e340b..0000000
--- a/src/northbridge/via/vt8601/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-
-driver northbridge.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/via/vt8623/Config.lb b/src/northbridge/via/vt8623/Config.lb
deleted file mode 100644
index 79e340b..0000000
--- a/src/northbridge/via/vt8623/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-uses CONFIG_WRITE_HIGH_TABLES
-
-config chip.h
-
-driver northbridge.o
-
-default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/via/vx800/Config.lb b/src/northbridge/via/vx800/Config.lb
deleted file mode 100644
index 9e6fcfe..0000000
--- a/src/northbridge/via/vx800/Config.lb
+++ /dev/null
@@ -1,25 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 One Laptop per Child, Association, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object vgabios.o
-driver northbridge.o
-driver vga.o
-driver vx800_lpc.o
-driver vx800_ide.o
diff --git a/src/pc80/Config.lb b/src/pc80/Config.lb
deleted file mode 100644
index 24af51c..0000000
--- a/src/pc80/Config.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-uses CONFIG_UDELAY_IO
-uses CONFIG_USE_INIT
-uses CONFIG_ARCH_X86
-
-object mc146818rtc.o
-object isa-dma.o
-object i8259.o 
-
-if CONFIG_UDELAY_IO
-	object udelay_io.o
-end
-
-dir vga
-
-object keyboard.o
-
-if CONFIG_ARCH_X86
-	if CONFIG_USE_INIT
-		initobject serial.o
-	end
-end
diff --git a/src/pc80/vga/Config.lb b/src/pc80/vga/Config.lb
deleted file mode 100644
index 0608d95..0000000
--- a/src/pc80/vga/Config.lb
+++ /dev/null
@@ -1,9 +0,0 @@
-uses CONFIG_VGA
-
-# always build this.
-object vga_io.o
-
-# this adds a vga modeset including a huge font.
-if CONFIG_VGA
-	object vga.o
-end
diff --git a/src/southbridge/amd/amd8111/Config.lb b/src/southbridge/amd/amd8111/Config.lb
deleted file mode 100644
index dfb7f16..0000000
--- a/src/southbridge/amd/amd8111/Config.lb
+++ /dev/null
@@ -1,12 +0,0 @@
-config chip.h
-driver amd8111.o
-driver amd8111_usb.o
-driver amd8111_lpc.o
-driver amd8111_ide.o
-driver amd8111_acpi.o
-driver amd8111_usb2.o
-driver amd8111_ac97.o
-driver amd8111_nic.o
-driver amd8111_pci.o
-driver amd8111_smbus.o
-object amd8111_reset.o
diff --git a/src/southbridge/amd/amd8131-disable/Config.lb b/src/southbridge/amd/amd8131-disable/Config.lb
deleted file mode 100644
index 9968e9a..0000000
--- a/src/southbridge/amd/amd8131-disable/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver amd8131_bridge.o
diff --git a/src/southbridge/amd/amd8131/Config.lb b/src/southbridge/amd/amd8131/Config.lb
deleted file mode 100644
index 9968e9a..0000000
--- a/src/southbridge/amd/amd8131/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver amd8131_bridge.o
diff --git a/src/southbridge/amd/amd8132/Config.lb b/src/southbridge/amd/amd8132/Config.lb
deleted file mode 100644
index ea045ab..0000000
--- a/src/southbridge/amd/amd8132/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver amd8132_bridge.o
diff --git a/src/southbridge/amd/amd8151/Config.lb b/src/southbridge/amd/amd8151/Config.lb
deleted file mode 100644
index 00a91b6..0000000
--- a/src/southbridge/amd/amd8151/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver amd8151_agp3.o
diff --git a/src/southbridge/amd/cs5530/Config.lb b/src/southbridge/amd/cs5530/Config.lb
deleted file mode 100644
index 9a3ae5f..0000000
--- a/src/southbridge/amd/cs5530/Config.lb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-driver cs5530.o
-driver cs5530_isa.o
-driver cs5530_ide.o
-driver cs5530_vga.o
-driver cs5530_pirq.o
diff --git a/src/southbridge/amd/cs5535/Config.lb b/src/southbridge/amd/cs5535/Config.lb
deleted file mode 100644
index 73d8bba..0000000
--- a/src/southbridge/amd/cs5535/Config.lb
+++ /dev/null
@@ -1,4 +0,0 @@
-#config chip.h
-driver cs5535.o
-#driver cs5535_pci.o
-#driver cs5535_ide.o
diff --git a/src/southbridge/amd/cs5536/Config.lb b/src/southbridge/amd/cs5536/Config.lb
deleted file mode 100644
index 6f317de..0000000
--- a/src/southbridge/amd/cs5536/Config.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-driver cs5536.o
-driver cs5536_ide.o
-driver cs5536_pirq.o
diff --git a/src/southbridge/amd/rs690/Config.lb b/src/southbridge/amd/rs690/Config.lb
deleted file mode 100644
index dbb7d1e..0000000
--- a/src/southbridge/amd/rs690/Config.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-config chip.h
-driver rs690_cmn.o
-driver rs690.o
-driver rs690_pcie.o
-driver rs690_ht.o
-driver rs690_gfx.o
diff --git a/src/southbridge/amd/sb600/Config.lb b/src/southbridge/amd/sb600/Config.lb
deleted file mode 100644
index 6e66487..0000000
--- a/src/southbridge/amd/sb600/Config.lb
+++ /dev/null
@@ -1,34 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-config chip.h
-driver sb600.o
-driver sb600_usb.o
-driver sb600_lpc.o
-driver sb600_sm.o
-driver sb600_ide.o
-driver sb600_sata.o
-driver sb600_hda.o
-driver sb600_ac97.o
-driver sb600_pci.o
-object sb600_reset.o
-
-
diff --git a/src/southbridge/broadcom/bcm21000/Config.lb b/src/southbridge/broadcom/bcm21000/Config.lb
deleted file mode 100644
index b411d1f..0000000
--- a/src/southbridge/broadcom/bcm21000/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver bcm21000_pcie.o
diff --git a/src/southbridge/broadcom/bcm5780/Config.lb b/src/southbridge/broadcom/bcm5780/Config.lb
deleted file mode 100644
index 69153ef..0000000
--- a/src/southbridge/broadcom/bcm5780/Config.lb
+++ /dev/null
@@ -1,3 +0,0 @@
-driver bcm5780_nic.o
-driver bcm5780_pcix.o
-driver bcm5780_pcie.o
diff --git a/src/southbridge/broadcom/bcm5785/Config.lb b/src/southbridge/broadcom/bcm5785/Config.lb
deleted file mode 100644
index 7cbc066..0000000
--- a/src/southbridge/broadcom/bcm5785/Config.lb
+++ /dev/null
@@ -1,8 +0,0 @@
-config chip.h
-driver bcm5785.o
-driver bcm5785_usb.o
-driver bcm5785_lpc.o
-driver bcm5785_sb_pci_main.o
-driver bcm5785_ide.o
-driver bcm5785_sata.o
-object bcm5785_reset.o
diff --git a/src/southbridge/intel/esb6300/Config.lb b/src/southbridge/intel/esb6300/Config.lb
deleted file mode 100644
index 9674c1f..0000000
--- a/src/southbridge/intel/esb6300/Config.lb
+++ /dev/null
@@ -1,12 +0,0 @@
-config chip.h
-driver esb6300.o
-driver esb6300_uhci.o
-driver esb6300_lpc.o
-driver esb6300_ide.o
-driver esb6300_sata.o
-driver esb6300_ehci.o
-driver esb6300_smbus.o
-driver esb6300_pci.o
-driver esb6300_pic.o
-driver esb6300_bridge1c.o
-driver esb6300_ac97.o
diff --git a/src/southbridge/intel/i3100/Config.lb b/src/southbridge/intel/i3100/Config.lb
deleted file mode 100644
index f67a06a..0000000
--- a/src/southbridge/intel/i3100/Config.lb
+++ /dev/null
@@ -1,29 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-driver i3100.o
-driver i3100_uhci.o
-driver i3100_lpc.o
-driver i3100_sata.o
-driver i3100_ehci.o
-driver i3100_smbus.o
-driver i3100_pci.o
-object i3100_reset.o
-object i3100_pciexp_portb.o
diff --git a/src/southbridge/intel/i82371eb/Config.lb b/src/southbridge/intel/i82371eb/Config.lb
deleted file mode 100644
index 9e3e805..0000000
--- a/src/southbridge/intel/i82371eb/Config.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-driver i82371eb.o
-driver i82371eb_isa.o
-driver i82371eb_ide.o
-driver i82371eb_usb.o
-driver i82371eb_smbus.o
-driver i82371eb_reset.o
diff --git a/src/southbridge/intel/i82801ca/Config.lb b/src/southbridge/intel/i82801ca/Config.lb
deleted file mode 100644
index 0f1911b..0000000
--- a/src/southbridge/intel/i82801ca/Config.lb
+++ /dev/null
@@ -1,9 +0,0 @@
-config chip.h
-driver i82801ca.o
-driver i82801ca_usb.o
-driver i82801ca_lpc.o
-driver i82801ca_ide.o
-driver i82801ca_ac97.o
-#driver i82801ca_nic.o
-driver i82801ca_pci.o
-object i82801ca_reset.o
diff --git a/src/southbridge/intel/i82801dbm/Config.lb b/src/southbridge/intel/i82801dbm/Config.lb
deleted file mode 100644
index bdbbe4f..0000000
--- a/src/southbridge/intel/i82801dbm/Config.lb
+++ /dev/null
@@ -1,10 +0,0 @@
-config chip.h
-driver i82801dbm.o
-driver i82801dbm_usb.o
-driver i82801dbm_lpc.o
-driver i82801dbm_ide.o
-driver i82801dbm_usb2.o
-driver i82801dbm_ac97.o
-#driver i82801dbm_nic.o
-#driver i82801dbm_pci.o
-object i82801dbm_reset.o
diff --git a/src/southbridge/intel/i82801er/Config.lb b/src/southbridge/intel/i82801er/Config.lb
deleted file mode 100644
index 1953eaa..0000000
--- a/src/southbridge/intel/i82801er/Config.lb
+++ /dev/null
@@ -1,12 +0,0 @@
-config chip.h
-driver i82801er.o
-driver i82801er_uhci.o
-driver i82801er_lpc.o
-driver i82801er_ide.o
-driver i82801er_sata.o
-driver i82801er_ehci.o
-driver i82801er_smbus.o
-driver i82801er_pci.o
-driver i82801er_ac97.o
-object i82801er_watchdog.o
-object i82801er_reset.o
diff --git a/src/southbridge/intel/i82801gx/Config.lb b/src/southbridge/intel/i82801gx/Config.lb
deleted file mode 100644
index 9ef5f43..0000000
--- a/src/southbridge/intel/i82801gx/Config.lb
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_HAVE_SMI_HANDLER
-
-config chip.h
-driver i82801gx.o
-driver i82801gx_ac97.o
-driver i82801gx_azalia.o
-driver i82801gx_ide.o
-driver i82801gx_lpc.o
-driver i82801gx_nic.o
-driver i82801gx_pci.o
-driver i82801gx_pcie.o
-driver i82801gx_sata.o
-driver i82801gx_smbus.o
-driver i82801gx_usb.o
-driver i82801gx_usb_ehci.o
-
-object i82801gx_reset.o
-object i82801gx_watchdog.o
-
-if CONFIG_HAVE_SMI_HANDLER
-	object i82801gx_smi.o
-	smmobject i82801gx_smihandler.o
-end
diff --git a/src/southbridge/intel/i82801xx/Config.lb b/src/southbridge/intel/i82801xx/Config.lb
deleted file mode 100644
index f02b515..0000000
--- a/src/southbridge/intel/i82801xx/Config.lb
+++ /dev/null
@@ -1,32 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-driver i82801xx.o
-driver i82801xx_usb.o
-driver i82801xx_lpc.o
-driver i82801xx_ide.o
-driver i82801xx_usb_ehci.o
-driver i82801xx_ac97.o
-driver i82801xx_nic.o
-driver i82801xx_pci.o
-driver i82801xx_sata.o
-object i82801xx_reset.o
-object i82801xx_watchdog.o
diff --git a/src/southbridge/intel/i82870/Config.lb b/src/southbridge/intel/i82870/Config.lb
deleted file mode 100644
index e6a9651..0000000
--- a/src/southbridge/intel/i82870/Config.lb
+++ /dev/null
@@ -1,3 +0,0 @@
-driver p64h2_ioapic.o
-driver p64h2_pcibridge.o
-#driver p64h2_pci_parity.o
diff --git a/src/southbridge/intel/pxhd/Config.lb b/src/southbridge/intel/pxhd/Config.lb
deleted file mode 100644
index 349b8dd..0000000
--- a/src/southbridge/intel/pxhd/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-driver pxhd_bridge.o
diff --git a/src/southbridge/nvidia/ck804/Config.lb b/src/southbridge/nvidia/ck804/Config.lb
deleted file mode 100644
index 89bd0e0..0000000
--- a/src/southbridge/nvidia/ck804/Config.lb
+++ /dev/null
@@ -1,20 +0,0 @@
-uses CONFIG_GENERATE_ACPI_TABLES
-
-config chip.h
-driver ck804.o
-driver ck804_usb.o
-driver ck804_lpc.o
-driver ck804_smbus.o
-driver ck804_ide.o
-driver ck804_sata.o
-driver ck804_usb2.o
-driver ck804_ac97.o
-driver ck804_nic.o
-driver ck804_pci.o
-driver ck804_pcie.o
-driver ck804_ht.o
-object ck804_reset.o
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object ck804_fadt.o
-end
diff --git a/src/southbridge/nvidia/mcp55/Config.lb b/src/southbridge/nvidia/mcp55/Config.lb
deleted file mode 100644
index 117cc51..0000000
--- a/src/southbridge/nvidia/mcp55/Config.lb
+++ /dev/null
@@ -1,40 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-uses CONFIG_GENERATE_ACPI_TABLES
-
-config chip.h
-driver mcp55.o
-driver mcp55_usb.o
-driver mcp55_lpc.o
-driver mcp55_smbus.o
-driver mcp55_ide.o
-driver mcp55_sata.o
-driver mcp55_usb2.o
-driver mcp55_aza.o
-driver mcp55_nic.o
-driver mcp55_pci.o
-driver mcp55_pcie.o
-driver mcp55_ht.o
-object mcp55_reset.o
-if CONFIG_GENERATE_ACPI_TABLES
-	object mcp55_fadt.o
-end
diff --git a/src/southbridge/ricoh/rl5c476/Config.lb b/src/southbridge/ricoh/rl5c476/Config.lb
deleted file mode 100644
index 05c7739..0000000
--- a/src/southbridge/ricoh/rl5c476/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object rl5c476.o
diff --git a/src/southbridge/sis/sis966/Config.lb b/src/southbridge/sis/sis966/Config.lb
deleted file mode 100644
index aaf3d5d..0000000
--- a/src/southbridge/sis/sis966/Config.lb
+++ /dev/null
@@ -1,33 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
-## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-driver sis761.o
-driver sis966.o
-driver sis966_lpc.o
-driver sis966_ide.o
-driver sis966_usb.o
-driver sis966_usb2.o
-driver sis966_nic.o
-driver sis966_sata.o
-driver sis966_pcie.o
-driver sis966_aza.o
-object sis966_reset.o
diff --git a/src/southbridge/ti/pci7420/Config.lb b/src/southbridge/ti/pci7420/Config.lb
deleted file mode 100644
index 10d412b..0000000
--- a/src/southbridge/ti/pci7420/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## (C) Copyright 2008-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; either version 2 of
-## the License, or (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-config chip.h
-object pci7420_cardbus.o
-object pci7420_firewire.o
diff --git a/src/southbridge/via/k8t890/Config.lb b/src/southbridge/via/k8t890/Config.lb
deleted file mode 100644
index 72502c2..0000000
--- a/src/southbridge/via/k8t890/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License v2 as published by
-## the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-driver k8t890_ctrl.o
-driver k8t890_dram.o
-driver k8t890_bridge.o
-driver k8t890_host.o
-driver k8t890_host_ctrl.o
-driver k8t890_pcie.o
-driver k8t890_traf_ctrl.o
-driver k8t890_error.o
-driver k8m890_chrome.o
diff --git a/src/southbridge/via/vt8231/Config.lb b/src/southbridge/via/vt8231/Config.lb
deleted file mode 100644
index 46b4e26..0000000
--- a/src/southbridge/via/vt8231/Config.lb
+++ /dev/null
@@ -1,8 +0,0 @@
-config chip.h
-driver vt8231.o
-driver vt8231_lpc.o
-driver vt8231_acpi.o
-driver vt8231_ide.o
-driver vt8231_nic.o
-#driver vt8231_usb.o
-
diff --git a/src/southbridge/via/vt8235/Config.lb b/src/southbridge/via/vt8235/Config.lb
deleted file mode 100644
index 297d214..0000000
--- a/src/southbridge/via/vt8235/Config.lb
+++ /dev/null
@@ -1,6 +0,0 @@
-config chip.h
-driver vt8235.o
-driver vt8235_ide.o
-driver vt8235_lpc.o
-driver vt8235_nic.o
-driver vt8235_usb.o
diff --git a/src/southbridge/via/vt8237r/Config.lb b/src/southbridge/via/vt8237r/Config.lb
deleted file mode 100644
index b760ec2..0000000
--- a/src/southbridge/via/vt8237r/Config.lb
+++ /dev/null
@@ -1,33 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License v2 as published by
-## the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_ACPI_TABLES
-
-config chip.h
-
-driver vt8237r.o
-driver vt8237_ctrl.o
-driver vt8237r_ide.o
-driver vt8237r_lpc.o
-driver vt8237r_sata.o
-driver vt8237r_usb.o
-driver vt8237r_nic.o
-if CONFIG_GENERATE_ACPI_TABLES
-	object vt8237_fadt.o
-end
diff --git a/src/southbridge/via/vt82c686/Config.lb b/src/southbridge/via/vt82c686/Config.lb
deleted file mode 100644
index 9db8b8c..0000000
--- a/src/southbridge/via/vt82c686/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-
diff --git a/src/superio/fintek/f71805f/Config.lb b/src/superio/fintek/f71805f/Config.lb
deleted file mode 100644
index 3773758..0000000
--- a/src/superio/fintek/f71805f/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/intel/i3100/Config.lb b/src/superio/intel/i3100/Config.lb
deleted file mode 100644
index cf4b0f3..0000000
--- a/src/superio/intel/i3100/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/ite/it8661f/Config.lb b/src/superio/ite/it8661f/Config.lb
deleted file mode 100644
index 8e91c17..0000000
--- a/src/superio/ite/it8661f/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/ite/it8671f/Config.lb b/src/superio/ite/it8671f/Config.lb
deleted file mode 100644
index 8e91c17..0000000
--- a/src/superio/ite/it8671f/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/ite/it8673f/Config.lb b/src/superio/ite/it8673f/Config.lb
deleted file mode 100644
index 8e91c17..0000000
--- a/src/superio/ite/it8673f/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/ite/it8705f/Config.lb b/src/superio/ite/it8705f/Config.lb
deleted file mode 100644
index 8e91c17..0000000
--- a/src/superio/ite/it8705f/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/ite/it8712f/Config.lb b/src/superio/ite/it8712f/Config.lb
deleted file mode 100644
index 8e91c17..0000000
--- a/src/superio/ite/it8712f/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/ite/it8716f/Config.lb b/src/superio/ite/it8716f/Config.lb
deleted file mode 100644
index 8e91c17..0000000
--- a/src/superio/ite/it8716f/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/ite/it8718f/Config.lb b/src/superio/ite/it8718f/Config.lb
deleted file mode 100644
index 8e91c17..0000000
--- a/src/superio/ite/it8718f/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/nsc/pc8374/Config.lb b/src/superio/nsc/pc8374/Config.lb
deleted file mode 100644
index df9204e..0000000
--- a/src/superio/nsc/pc8374/Config.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/nsc/pc87309/Config.lb b/src/superio/nsc/pc87309/Config.lb
deleted file mode 100644
index 512a218..0000000
--- a/src/superio/nsc/pc87309/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/nsc/pc87351/Config.lb b/src/superio/nsc/pc87351/Config.lb
deleted file mode 100644
index df9204e..0000000
--- a/src/superio/nsc/pc87351/Config.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/nsc/pc87360/Config.lb b/src/superio/nsc/pc87360/Config.lb
deleted file mode 100644
index df9204e..0000000
--- a/src/superio/nsc/pc87360/Config.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/nsc/pc87366/Config.lb b/src/superio/nsc/pc87366/Config.lb
deleted file mode 100644
index df9204e..0000000
--- a/src/superio/nsc/pc87366/Config.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/nsc/pc87417/Config.lb b/src/superio/nsc/pc87417/Config.lb
deleted file mode 100644
index f863270..0000000
--- a/src/superio/nsc/pc87417/Config.lb
+++ /dev/null
@@ -1,24 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-## Copyright (C) 2004 Tyan by yhlu
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/nsc/pc87427/Config.lb b/src/superio/nsc/pc87427/Config.lb
deleted file mode 100644
index df9204e..0000000
--- a/src/superio/nsc/pc87427/Config.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/nsc/pc97307/Config.lb b/src/superio/nsc/pc97307/Config.lb
deleted file mode 100644
index 5e25501..0000000
--- a/src/superio/nsc/pc97307/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.c
diff --git a/src/superio/nsc/pc97317/Config.lb b/src/superio/nsc/pc97317/Config.lb
deleted file mode 100644
index 5e25501..0000000
--- a/src/superio/nsc/pc97317/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.c
diff --git a/src/superio/renesas/m3885x/Config.lb b/src/superio/renesas/m3885x/Config.lb
deleted file mode 100644
index 3828fd4..0000000
--- a/src/superio/renesas/m3885x/Config.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2009 coresystems GmbH
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-config chip.h
-object superio.o
diff --git a/src/superio/smsc/fdc37m60x/Config.lb b/src/superio/smsc/fdc37m60x/Config.lb
deleted file mode 100644
index 8e91c17..0000000
--- a/src/superio/smsc/fdc37m60x/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/smsc/lpc47b272/Config.lb b/src/superio/smsc/lpc47b272/Config.lb
deleted file mode 100644
index 5a15d15..0000000
--- a/src/superio/smsc/lpc47b272/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2005 Digital Design Corporation
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/smsc/lpc47b397/Config.lb b/src/superio/smsc/lpc47b397/Config.lb
deleted file mode 100644
index 699d2c4..0000000
--- a/src/superio/smsc/lpc47b397/Config.lb
+++ /dev/null
@@ -1,24 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-## Copyright (C) 2004 Tyan
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/smsc/lpc47m10x/Config.lb b/src/superio/smsc/lpc47m10x/Config.lb
deleted file mode 100644
index 3ac7b52..0000000
--- a/src/superio/smsc/lpc47m10x/Config.lb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip
-##
-## Copyright 2000  AG Electronics Ltd.
-## Copyright 2003-2004 Linux Networx
-## Copyright 2004 Tyan
-## Copyright (C) 2005 Digital Design Corporation
-## Copyright (C) Ron Minnich, LANL
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/smsc/lpc47m15x/Config.lb b/src/superio/smsc/lpc47m15x/Config.lb
deleted file mode 100644
index ace2af6..0000000
--- a/src/superio/smsc/lpc47m15x/Config.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/smsc/lpc47n217/Config.lb b/src/superio/smsc/lpc47n217/Config.lb
deleted file mode 100644
index 5a15d15..0000000
--- a/src/superio/smsc/lpc47n217/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2005 Digital Design Corporation
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/smsc/lpc47n227/Config.lb b/src/superio/smsc/lpc47n227/Config.lb
deleted file mode 100644
index f439b9a..0000000
--- a/src/superio/smsc/lpc47n227/Config.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2008 coresystems GmbH
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-config chip.h
-object superio.o
diff --git a/src/superio/smsc/smscsuperio/Config.lb b/src/superio/smsc/smscsuperio/Config.lb
deleted file mode 100644
index 512a218..0000000
--- a/src/superio/smsc/smscsuperio/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/via/vt1211/Config.lb b/src/superio/via/vt1211/Config.lb
deleted file mode 100644
index c914fe2..0000000
--- a/src/superio/via/vt1211/Config.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; either version 2 of
-## the License, or (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-config chip.h
-object vt1211.o
diff --git a/src/superio/winbond/w83627dhg/Config.lb b/src/superio/winbond/w83627dhg/Config.lb
deleted file mode 100644
index db6949f..0000000
--- a/src/superio/winbond/w83627dhg/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/winbond/w83627ehg/Config.lb b/src/superio/winbond/w83627ehg/Config.lb
deleted file mode 100644
index b858b85..0000000
--- a/src/superio/winbond/w83627ehg/Config.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/winbond/w83627hf/Config.lb b/src/superio/winbond/w83627hf/Config.lb
deleted file mode 100644
index 5f1320d..0000000
--- a/src/superio/winbond/w83627hf/Config.lb
+++ /dev/null
@@ -1,24 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-## Copyright (C) 2004 Tyan By LYH change from PC87360
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/winbond/w83627thf/Config.lb b/src/superio/winbond/w83627thf/Config.lb
deleted file mode 100644
index 5f1320d..0000000
--- a/src/superio/winbond/w83627thf/Config.lb
+++ /dev/null
@@ -1,24 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-## Copyright (C) 2004 Tyan By LYH change from PC87360
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/winbond/w83627thg/Config.lb b/src/superio/winbond/w83627thg/Config.lb
deleted file mode 100644
index 5f1320d..0000000
--- a/src/superio/winbond/w83627thg/Config.lb
+++ /dev/null
@@ -1,24 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-## Copyright (C) 2004 Tyan By LYH change from PC87360
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/winbond/w83627uhg/Config.lb b/src/superio/winbond/w83627uhg/Config.lb
deleted file mode 100644
index 18b1abb..0000000
--- a/src/superio/winbond/w83627uhg/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Dynon Avionics
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 $
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/winbond/w83697hf/Config.lb b/src/superio/winbond/w83697hf/Config.lb
deleted file mode 100644
index c4790d9..0000000
--- a/src/superio/winbond/w83697hf/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Sean Nelson <snelson@nmt.edu>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/winbond/w83977f/Config.lb b/src/superio/winbond/w83977f/Config.lb
deleted file mode 100644
index 955a21e..0000000
--- a/src/superio/winbond/w83977f/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/src/superio/winbond/w83977tf/Config.lb b/src/superio/winbond/w83977tf/Config.lb
deleted file mode 100644
index 5f1320d..0000000
--- a/src/superio/winbond/w83977tf/Config.lb
+++ /dev/null
@@ -1,24 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-## Copyright (C) 2004 Tyan By LYH change from PC87360
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object superio.o
diff --git a/targets/a-trend/atc-6220/Config.lb b/targets/a-trend/atc-6220/Config.lb
deleted file mode 100644
index 4d8ebc0..0000000
--- a/targets/a-trend/atc-6220/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target atc-6220
-mainboard a-trend/atc-6220
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "A-Trend"
-option CONFIG_MAINBOARD_PART_NUMBER = "ATC-6220"
-
-option CONFIG_IRQ_SLOT_COUNT = 7
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/a-trend/atc-6240/Config.lb b/targets/a-trend/atc-6240/Config.lb
deleted file mode 100644
index 16a0c26..0000000
--- a/targets/a-trend/atc-6240/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target atc-6240
-mainboard a-trend/atc-6240
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "A-Trend"
-option CONFIG_MAINBOARD_PART_NUMBER = "ATC-6240"
-
-option CONFIG_IRQ_SLOT_COUNT = 7
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/abit/be6-ii_v2_0/Config.lb b/targets/abit/be6-ii_v2_0/Config.lb
deleted file mode 100644
index cfeeca0..0000000
--- a/targets/abit/be6-ii_v2_0/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target be6-ii_v2_0
-mainboard abit/be6-ii_v2_0
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "Abit"
-option CONFIG_MAINBOARD_PART_NUMBER = "BE6-II V2.0"
-
-option CONFIG_IRQ_SLOT_COUNT = 9
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/advantech/pcm-5820/Config.lb b/targets/advantech/pcm-5820/Config.lb
deleted file mode 100644
index 8be840d..0000000
--- a/targets/advantech/pcm-5820/Config.lb
+++ /dev/null
@@ -1,54 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target pcm-5820
-mainboard advantech/pcm-5820
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "Advantech"
-option CONFIG_MAINBOARD_PART_NUMBER = "PCM-5820"
-
-option CONFIG_IRQ_SLOT_COUNT = 2
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-option CONFIG_GX1_VIDEO = 1
-option CONFIG_GX1_VIDEOMODE = 0
-option CONFIG_SPLASH_GRAPHIC = 1
-option CONFIG_VIDEO_MB = 2
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/amd/db800/Config.lb b/targets/amd/db800/Config.lb
deleted file mode 100644
index 967eedb..0000000
--- a/targets/amd/db800/Config.lb
+++ /dev/null
@@ -1,48 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Config file for the AMD Geode LX/5536 DB800 platform.
-
-target db800
-mainboard amd/db800
-
-# HACK to get the right TSC support.
-option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
-
-# Leave 36k for VSA.
-option CONFIG_ROM_SIZE=512*1024-36*1024
-# option CONFIG_ROM_SIZE=256*1024-36*1024
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-# option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
-# option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=64*1024
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/amd/dbm690t/Config-abuild.lb b/targets/amd/dbm690t/Config-abuild.lb
deleted file mode 100644
index b9e9836..0000000
--- a/targets/amd/dbm690t/Config-abuild.lb
+++ /dev/null
@@ -1,30 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=1024*1024
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-        option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-        option CONFIG_USE_FALLBACK_IMAGE=1
-        option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/amd/dbm690t/Config.lb b/targets/amd/dbm690t/Config.lb
deleted file mode 100644
index e3f0ab3..0000000
--- a/targets/amd/dbm690t/Config.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-# This will make a target directory of ./dbm690t
-
-target dbm690t
-mainboard amd/dbm690t
-
-romimage "normal"
-	option CONFIG_ROM_SIZE = 1024*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/amd/dbm690t/VERSION b/targets/amd/dbm690t/VERSION
deleted file mode 100644
index e3cb14e..0000000
--- a/targets/amd/dbm690t/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_dbm690t
diff --git a/targets/amd/norwich/Config.lb b/targets/amd/norwich/Config.lb
deleted file mode 100644
index 828c507..0000000
--- a/targets/amd/norwich/Config.lb
+++ /dev/null
@@ -1,48 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Config file for the AMD Geode LX/5536 Norwich Platform.
-
-target norwich
-mainboard amd/norwich
-
-# HACK to get the right TSC support.
-option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-# Leave 36k for VSA.
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
-
-option CONFIG_ROM_SIZE=512*1024-36*1024
-#option CONFIG_ROM_SIZE=256*1024-36*1024
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-#option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
-#option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=64*1024
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/amd/pistachio/Config-abuild.lb b/targets/amd/pistachio/Config-abuild.lb
deleted file mode 100644
index b9e9836..0000000
--- a/targets/amd/pistachio/Config-abuild.lb
+++ /dev/null
@@ -1,30 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=1024*1024
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-        option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-        option CONFIG_USE_FALLBACK_IMAGE=1
-        option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/amd/pistachio/Config.lb b/targets/amd/pistachio/Config.lb
deleted file mode 100644
index 5d6ca9b..0000000
--- a/targets/amd/pistachio/Config.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-# This will make a target directory of ./pistachio
-
-target pistachio
-mainboard amd/pistachio
-
-romimage "normal"
-	option CONFIG_ROM_SIZE = 1024*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/amd/rumba/Config.lb b/targets/amd/rumba/Config.lb
deleted file mode 100644
index ac42dd4..0000000
--- a/targets/amd/rumba/Config.lb
+++ /dev/null
@@ -1,33 +0,0 @@
-# Config file for the AMD rumba motherboard
-# This will make a target directory of rumba
-
-target rumba
-mainboard amd/rumba
-
-option CONFIG_ROM_SIZE=256*1024
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-#	payload /etc/hosts
-#	payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
-	payload /tmp/filo.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebia
-#	payload /etc/hosts
-#	payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/amd/rumba/Config.nofallback.lb b/targets/amd/rumba/Config.nofallback.lb
deleted file mode 100644
index 4e73c3a..0000000
--- a/targets/amd/rumba/Config.nofallback.lb
+++ /dev/null
@@ -1,36 +0,0 @@
-# Config file for the AMD rumba motherboard
-# This will make a target directory of rumba
-
-target rumba
-mainboard amd/rumba
-
-option CONFIG_ROM_SIZE=128*1024
-
-#romimage "normal"
-#	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x10000
-#	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-#	payload /etc/hosts
-#	payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
-#	payload /tmp/filo.elf
-#end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebia
-#	payload /etc/hosts
-#	payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
-	payload /tmp/filo.elf
-#	payload /home/ollie/work/filo-0.4.1/filo.elf
-end
-
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-
diff --git a/targets/amd/serengeti_cheetah/Config-abuild.lb b/targets/amd/serengeti_cheetah/Config-abuild.lb
deleted file mode 100644
index 22e527e..0000000
--- a/targets/amd/serengeti_cheetah/Config-abuild.lb
+++ /dev/null
@@ -1,34 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/amd/serengeti_cheetah/Config-lab.lb b/targets/amd/serengeti_cheetah/Config-lab.lb
deleted file mode 100644
index 6577672..0000000
--- a/targets/amd/serengeti_cheetah/Config-lab.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-# Sample config file for 
-# the amd serengeti_cheetah 
-# This will make a target directory of ./serengeti_cheetah
-
-target serengeti_cheetah
-mainboard amd/serengeti_cheetah
-
-option CONFIG_ROM_SIZE = 0x100000
-option CONFIG_USE_FAILOVER_IMAGE=0
-option CONFIG_HAVE_FAILOVER_BOOT=0
-option CONFIG_FAILOVER_SIZE=0
-
-romimage "fallback"
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x1a000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	payload ../payload.elf.lzma
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/amd/serengeti_cheetah/Config.lb b/targets/amd/serengeti_cheetah/Config.lb
deleted file mode 100644
index b336c2a..0000000
--- a/targets/amd/serengeti_cheetah/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-# Sample config file for 
-# the amd serengeti_cheetah 
-# This will make a target directory of ./serengeti_cheetah
-
-target serengeti_cheetah
-mainboard amd/serengeti_cheetah
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/amd/serengeti_cheetah/VERSION b/targets/amd/serengeti_cheetah/VERSION
deleted file mode 100644
index e70b27c..0000000
--- a/targets/amd/serengeti_cheetah/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_serengenti_cheetah
diff --git a/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb b/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
deleted file mode 100644
index ba6c58a..0000000
--- a/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
+++ /dev/null
@@ -1,30 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=1024*1024
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x3f000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-	option COREBOOT_EXTRA_VERSION=".0-failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
diff --git a/targets/amd/serengeti_cheetah_fam10/Config-lab.lb b/targets/amd/serengeti_cheetah_fam10/Config-lab.lb
deleted file mode 100644
index 88c7f54..0000000
--- a/targets/amd/serengeti_cheetah_fam10/Config-lab.lb
+++ /dev/null
@@ -1,53 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Sample config file for
-# the amd cheetah_fam10
-# This will make a target directory of ./serengeti_cheetah_fam10
-
-target serengeti_cheetah_fam10
-mainboard amd/serengeti_cheetah_fam10
-# Request this level of debugging output
-	option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-# At a maximum only compile in this level of debugging
-	option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-# 1024KB ROM
-option CONFIG_ROM_SIZE=1024*1024
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x30000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf.lzma
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
-
diff --git a/targets/amd/serengeti_cheetah_fam10/Config.lb b/targets/amd/serengeti_cheetah_fam10/Config.lb
deleted file mode 100644
index 189d536..0000000
--- a/targets/amd/serengeti_cheetah_fam10/Config.lb
+++ /dev/null
@@ -1,70 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Sample config file for
-# the amd cheetah_fam10
-# This will make a target directory of ./serengeti_cheetah_fam10
-
-target serengeti_cheetah_fam10
-mainboard amd/serengeti_cheetah_fam10
-# Request this level of debugging output
-	option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-# At a maximum only compile in this level of debugging
-	option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-# 512KB ROM
-option CONFIG_ROM_SIZE=1024*1024
-
-# Cheetah Family 10
-#romimage "normal"
-#	1MB ROM
-#	option CONFIG_ROM_SIZE = 0x100000
-#	option CONFIG_USE_FAILOVER_IMAGE=0
-#	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x30000
-#	option CONFIG_XIP_ROM_SIZE=0x40000
-#	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#	payload ../payload.elf
-#end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x7f000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-	option CONFIG_XIP_ROM_SIZE=0x80000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
-
diff --git a/targets/arima/hdama/Config-abuild.lb b/targets/arima/hdama/Config-abuild.lb
deleted file mode 100644
index 12c3abf..0000000
--- a/targets/arima/hdama/Config-abuild.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=512*1024
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/arima/hdama/Config.kernelimage.lb b/targets/arima/hdama/Config.kernelimage.lb
deleted file mode 100644
index 236d606..0000000
--- a/targets/arima/hdama/Config.kernelimage.lb
+++ /dev/null
@@ -1,94 +0,0 @@
-# Sample config file for Motorola Sandpoint X3 Demo Board with
-# the Arima HDAMA
-# This will make a target directory of ./hdama
-
-loadoptions
-
-target hdama
-
-uses CONFIG_ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_HAVE_HARD_RESET
-uses i586
-uses i686
-uses CONFIG_INTEL_PPRO_MTRR
-uses CONFIG_HEAP_SIZE
-uses CONFIG_IRQ_SLOT_COUNT
-uses k7
-uses k8
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_SMP
-uses CONFIG_MAX_CPUS
-uses CONFIG_MEMORY_HOLE
-uses CONFIG_RAMBASE
-uses CONFIG_ROMBASE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses  CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses  CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_MAINBOARD
-uses CONFIG_CHIP_CONFIGURE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses COREBOOT_EXTRA_VERSION
-
-option CONFIG_CHIP_CONFIGURE=1
-
-option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-option  CONFIG_CONSOLE_SERIAL8250=1
-
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option CONFIG_INTEL_PPRO_MTRR=1
-option k7=1
-option k8=1
-
-option CONFIG_ROM_SIZE=1024*1024
-
-
-option CONFIG_HAVE_OPTION_TABLE=1
-option CONFIG_ROM_PAYLOAD=1
-option CONFIG_HAVE_FALLBACK_BOOT=1
-
-## Coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x00004000
-
-#
-###
-### Compute the start location and size size of
-### The coreboot bootloader.
-###
-
-#
-# Arima hdama
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-#	option CONFIG_ROM_SECTION_SIZE=0x100000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	mainboard arima/hdama
-#	payload ../../../../tg3--ide_disk.zelf
-	payload ../../../../opteron_phase1_p4_noapic
-#	payload ../../../../../../hdama-1
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/arima/hdama/Config.lb b/targets/arima/hdama/Config.lb
deleted file mode 100644
index 38d6df0..0000000
--- a/targets/arima/hdama/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-# Sample config file for Motorola Sandpoint X3 Demo Board with
-# the Arima HDAMA
-# This will make a target directory of ./hdama
-
-
-target hdama
-mainboard arima/hdama
-
-option CONFIG_ROM_SIZE=512*1024-36*1024
-
-# Arima hdama
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-	payload ../../../payloads/filo.elf
-#	payload /etc/hosts
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload ../../../payloads/filo.elf
-#	payload /etc/hosts
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/artecgroup/dbe61/Config.lb b/targets/artecgroup/dbe61/Config.lb
deleted file mode 100644
index eaa979c..0000000
--- a/targets/artecgroup/dbe61/Config.lb
+++ /dev/null
@@ -1,32 +0,0 @@
-# Config file for the ThinCan dbe61
-
-target dbe61
-mainboard artecgroup/dbe61
-
-# HACK to get the right TSC support.
-option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-## leave 36k for vsa and 32K for video ROM
-#option CONFIG_ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024
-
-#No VGA for now
-option CONFIG_ROM_SIZE = 1024*512 - 36*1024
-
-# CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE=64*1024
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
diff --git a/targets/asi/mb_5blgp/Config.lb b/targets/asi/mb_5blgp/Config.lb
deleted file mode 100644
index db75ec5..0000000
--- a/targets/asi/mb_5blgp/Config.lb
+++ /dev/null
@@ -1,54 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target mb_5blgp
-mainboard asi/mb_5blgp
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "ASI"
-option CONFIG_MAINBOARD_PART_NUMBER = "MB-5BLGP"
-
-option CONFIG_IRQ_SLOT_COUNT = 3
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-option CONFIG_GX1_VIDEO = 1
-option CONFIG_GX1_VIDEOMODE = 0
-option CONFIG_SPLASH_GRAPHIC = 1
-option CONFIG_VIDEO_MB = 2
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/asi/mb_5blmp/Config.lb b/targets/asi/mb_5blmp/Config.lb
deleted file mode 100644
index f57c13d..0000000
--- a/targets/asi/mb_5blmp/Config.lb
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target mb_5blmp
-mainboard asi/mb_5blmp
-
-option CONFIG_ROM_SIZE = (256 * 1024)
-# option CONFIG_ROM_SIZE = (256 * 1024) - (32 * 1024)
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-# buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/asus/a8n_e/Config-abuild.lb b/targets/asus/a8n_e/Config-abuild.lb
deleted file mode 100644
index 22e527e..0000000
--- a/targets/asus/a8n_e/Config-abuild.lb
+++ /dev/null
@@ -1,34 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/asus/a8n_e/Config.lb b/targets/asus/a8n_e/Config.lb
deleted file mode 100644
index 877bbd8..0000000
--- a/targets/asus/a8n_e/Config.lb
+++ /dev/null
@@ -1,48 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
-## (Thanks to LSRA University of Mannheim for their support)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target asus_a8n_e
-mainboard asus/a8n_e
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE = 0
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = "_Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE = 0
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = "_Fallback"
-	payload ../payload.elf
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE = 1
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE
-	option COREBOOT_EXTRA_VERSION = "_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
-# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/asus/a8v-e_se/Config.lb b/targets/asus/a8v-e_se/Config.lb
deleted file mode 100644
index a0af296..0000000
--- a/targets/asus/a8v-e_se/Config.lb
+++ /dev/null
@@ -1,38 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License v2 as published by
-## the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target asus_a8v-e_se
-mainboard asus/a8v-e_se
-
-romimage "normal"
-	option CONFIG_ROM_SIZE = 512 * 1024
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/asus/m2v-mx_se/Config-abuild.lb b/targets/asus/m2v-mx_se/Config-abuild.lb
deleted file mode 100644
index 07c6ebd..0000000
--- a/targets/asus/m2v-mx_se/Config-abuild.lb
+++ /dev/null
@@ -1,43 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License v2 as published by
-## the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target asus_m2v-mx_se
-mainboard asus/m2v-mx_se
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-
-# The board comes with 512KB SPI flash (DIP8), 128KB is for coreboot binary
-# 384KB of flash is for payload/roms.
-
-option CONFIG_ROM_SIZE = 512 * 1024
-
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/asus/m2v-mx_se/Config.lb b/targets/asus/m2v-mx_se/Config.lb
deleted file mode 100644
index 4183543..0000000
--- a/targets/asus/m2v-mx_se/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License v2 as published by
-## the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target asus_m2v-mx_se
-mainboard asus/m2v-mx_se
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-
-# The board comes with 512KB SPI flash (DIP8), 128KB is for coreboot binary
-# 384KB of flash is for payload/roms.
-
-option CONFIG_ROM_SIZE = 512 * 1024
-
-# Use following line instead if you want to use onboard VGA -
-# padd the rom size to 64KB or XIP won't work, complaining about
-# not good base.
-
-#option CONFIG_ROM_SIZE = (512 * 1024) - (64 * 1024)
-
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-
-# Please note that 128KB is cached for (XIP) too
-
-option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/asus/mew-am/Config.lb b/targets/asus/mew-am/Config.lb
deleted file mode 100644
index ce65169..0000000
--- a/targets/asus/mew-am/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target mew-am
-mainboard asus/mew-am
-
-option CONFIG_ROM_SIZE = 512 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "ASUS"
-option CONFIG_MAINBOARD_PART_NUMBER = "MEW-AM"
-
-option CONFIG_IRQ_SLOT_COUNT = 8
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/asus/mew-vm/Config.lb b/targets/asus/mew-vm/Config.lb
deleted file mode 100644
index be75e03..0000000
--- a/targets/asus/mew-vm/Config.lb
+++ /dev/null
@@ -1,25 +0,0 @@
-target mew-vm
-mainboard asus/mew-vm
-
-## Without VGA BIOS
-option CONFIG_ROM_SIZE = 512 * 1024
-## With VGA BIOS (32k)
-#option CONFIG_ROM_SIZE = (512 * 1024) - (32 * 1024)
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /etc/hosts
-	payload /home/amp/filo-0.5/filo.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /etc/hosts
-	payload /home/amp/filo-0.5/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/asus/p2b-d/Config.lb b/targets/asus/p2b-d/Config.lb
deleted file mode 100644
index 739bb77..0000000
--- a/targets/asus/p2b-d/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target p2b-d
-mainboard asus/p2b-d
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "ASUS"
-option CONFIG_MAINBOARD_PART_NUMBER = "P2B-D"
-
-option CONFIG_IRQ_SLOT_COUNT = 6
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/asus/p2b-ds/Config.lb b/targets/asus/p2b-ds/Config.lb
deleted file mode 100644
index ca039ed..0000000
--- a/targets/asus/p2b-ds/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target p2b-ds
-mainboard asus/p2b-ds
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "ASUS"
-option CONFIG_MAINBOARD_PART_NUMBER = "P2B-DS"
-
-option CONFIG_IRQ_SLOT_COUNT = 7
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/asus/p2b-f/Config.lb b/targets/asus/p2b-f/Config.lb
deleted file mode 100644
index 0c19593..0000000
--- a/targets/asus/p2b-f/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target p2b-f
-mainboard asus/p2b-f
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "ASUS"
-option CONFIG_MAINBOARD_PART_NUMBER = "P2B-F"
-
-option CONFIG_IRQ_SLOT_COUNT = 7
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/asus/p2b/Config.lb b/targets/asus/p2b/Config.lb
deleted file mode 100644
index 8f5f33c..0000000
--- a/targets/asus/p2b/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target p2b
-mainboard asus/p2b
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "ASUS"
-option CONFIG_MAINBOARD_PART_NUMBER = "P2B"
-
-option CONFIG_IRQ_SLOT_COUNT = 6
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/asus/p3b-f/Config.lb b/targets/asus/p3b-f/Config.lb
deleted file mode 100644
index 9c2eb61..0000000
--- a/targets/asus/p3b-f/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target p3b-f
-mainboard asus/p3b-f
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "ASUS"
-option CONFIG_MAINBOARD_PART_NUMBER = "P3B-F"
-
-option CONFIG_IRQ_SLOT_COUNT = 8
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/axus/tc320/Config.lb b/targets/axus/tc320/Config.lb
deleted file mode 100644
index 749cd24..0000000
--- a/targets/axus/tc320/Config.lb
+++ /dev/null
@@ -1,51 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## See also: http://coreboot.org/AXUS_WINTERM_Build_Tutorial
-
-target tc320
-mainboard axus/tc320
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-option CONFIG_GX1_VIDEO = 1
-option CONFIG_GX1_VIDEOMODE = 0
-option CONFIG_SPLASH_GRAPHIC = 1
-option CONFIG_VIDEO_MB = 2
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload ../../../../../../../images/etherboot.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload ../../../../../../../images/etherboot.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/azza/pt-6ibd/Config.lb b/targets/azza/pt-6ibd/Config.lb
deleted file mode 100644
index 19bcece..0000000
--- a/targets/azza/pt-6ibd/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target pt-6ibd
-mainboard azza/pt-6ibd
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "AZZA"
-option CONFIG_MAINBOARD_PART_NUMBER = "PT-6IBD"
-
-option CONFIG_IRQ_SLOT_COUNT = 7
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/bcom/winnet100/Config.lb b/targets/bcom/winnet100/Config.lb
deleted file mode 100644
index de81d0f..0000000
--- a/targets/bcom/winnet100/Config.lb
+++ /dev/null
@@ -1,53 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## See also: http://www.coreboot.org/BCOM_WINNET100_Build_Tutorial
-
-target winnet100
-mainboard bcom/winnet100
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-option CONFIG_GX1_VIDEO = 1
-option CONFIG_GX1_VIDEOMODE = 0
-option CONFIG_SPLASH_GRAPHIC = 1
-option CONFIG_VIDEO_MB = 2
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload ../../../../../../../images/etherboot.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload ../../../../../../../images/etherboot.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/bcom/winnetp680/Config-abuild.lb b/targets/bcom/winnetp680/Config-abuild.lb
deleted file mode 100644
index 620685b..0000000
--- a/targets/bcom/winnetp680/Config-abuild.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=512*1024
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/bcom/winnetp680/Config.lb b/targets/bcom/winnetp680/Config.lb
deleted file mode 100644
index f8ced33..0000000
--- a/targets/bcom/winnetp680/Config.lb
+++ /dev/null
@@ -1,45 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target bcom-winnet-p680
-mainboard bcom/winnetp680
-
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-option CONFIG_CONSOLE_SERIAL8250=1
-
-# coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x00004000
-
-#
-# If space is allotted for a VGA BIOS,
-# generate the final ROM like this:
-# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
-#
-#option CONFIG_ROM_SIZE = (512 * 1024) - (63 * 1024) - (64 * 1024)
-option CONFIG_ROM_SIZE = (512 * 1024)
-
-romimage "fallback"
-	option COREBOOT_EXTRA_VERSION = "-winnetp680"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/biostar/m6tba/Config.lb b/targets/biostar/m6tba/Config.lb
deleted file mode 100644
index f3ab12f..0000000
--- a/targets/biostar/m6tba/Config.lb
+++ /dev/null
@@ -1,50 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target m6tba
-mainboard biostar/m6tba
-
-# Note: The original flash ROM chip is 128 KB.
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "Biostar"
-option CONFIG_MAINBOARD_PART_NUMBER = "M6TBA"
-
-option CONFIG_IRQ_SLOT_COUNT = 7
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/broadcom/blast/Config.lb b/targets/broadcom/blast/Config.lb
deleted file mode 100644
index 9cef8d6..0000000
--- a/targets/broadcom/blast/Config.lb
+++ /dev/null
@@ -1,65 +0,0 @@
-# Sample config file for 
-# the broadcom blast
-# This will make a target directory of ./blast
-
-target blast
-mainboard broadcom/blast
-
-romimage "normal"
-#       48K for ATI rom
-        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-#       64K for Etherboot
-#       option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/memtest
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/broadcom/blast/VERSION b/targets/broadcom/blast/VERSION
deleted file mode 100644
index 40937a7..0000000
--- a/targets/broadcom/blast/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_blast
diff --git a/targets/buildtarget b/targets/buildtarget
deleted file mode 100755
index 02694a2..0000000
--- a/targets/buildtarget
+++ /dev/null
@@ -1,87 +0,0 @@
-#!/bin/sh
-PYTHON=python
-# Target build script
-
-if [ $# -lt 1 ]; then
-	echo "usage: buildtarget target [path-to-coreboot]"
-	exit 1
-fi
-
-if [ $# -gt 1 ]; then
-	lbpath=$2
-else
-	lbpath=`pwd`
-	lbpath=`dirname $lbpath`
-fi
-
-target_dir=$lbpath/targets
-config_lb=$1
-config_dir=$lbpath/util/newconfig
-yapps2_py=$config_dir/yapps2.py
-config_g=$config_dir/config.g
-
-if [ ! -d $target_dir ]; then
-	echo "Target directory not found"
-	exit 1
-fi
-
-cd $target_dir
-
-if [ ! -f $config_lb ]; then
-	config_lb=$1/Config.lb
-fi
-if [ ! -f $config_lb ]; then
-	echo "No target config file found"
-	echo "Tried both $1 and $config_lb"
-	exit 1
-fi
-
-build_dir=`dirname $config_lb`/`sed -n -e 's/^target \(.*\)$/\1/p' $config_lb`
-echo "build_dir=$build_dir"
-config_py=$build_dir/config.py
-
-if [ ! -d $build_dir ] ; then
-	mkdir -p $build_dir
-fi
-if [ ! -f $config_py ]; then
-	echo "No coreboot config script found. Rebuilding it.."
-	$PYTHON $yapps2_py $config_g $config_py
-fi
-
-# make sure config.py is up-to-date
-
-export PYTHONPATH=$config_dir
-$PYTHON $config_py $config_lb $lbpath
-
-# now start checking for distro-specific breakage. 
-## This check is for the no stack protector mess.
-EXTRA_CFLAGS=
-
-if [ -z "$CC" ]; then
-       CC=gcc
-fi
-
-$CC -fno-stack-protector -S -xc /dev/null -o .$$.tmp 2>/dev/null
-
-if [ $? -eq 0 ]; then
-       EXTRA_CFLAGS=-fno-stack-protector
-fi
-
-rm -rf .$$.tmp
-
-# The linker output fd depends on the gcc version.
-#  1) 'ld-2.15 --help' and 'gcc-4.0 -Wl,--help' use STDOUT.
-#  2) 'gcc-3.3 --help' and 'gcc-3.4 -Wl,--help' use STDERR.
-# Thus older versions of GCC (presumably 3.x) implement a redirection of
-# output to stderr. Re-redirect stderr to stdout to work always.
-if $CC -Wl,--help 2>&1 | grep -q build-id; then
-	EXTRA_LFLAGS="$EXTRA_LFLAGS -Wl,--build-id=none"
-fi
-
-for i in $build_dir/Makefile.settings $build_dir/*/Makefile.settings
-do
-	echo DISTRO_CFLAGS+=$EXTRA_CFLAGS >>$i
-	echo DISTRO_LFLAGS+=$EXTRA_LFLAGS >>$i
-done
-
-exit $?
diff --git a/targets/compaq/deskpro_en_sff_p600/Config.lb b/targets/compaq/deskpro_en_sff_p600/Config.lb
deleted file mode 100644
index 8df90b7..0000000
--- a/targets/compaq/deskpro_en_sff_p600/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target deskpro_en_sff_p600
-mainboard compaq/deskpro_en_sff_p600
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "Compaq"
-option CONFIG_MAINBOARD_PART_NUMBER = "Deskpro EN SFF P600"
-
-option CONFIG_IRQ_SLOT_COUNT = 5
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/dell/s1850/Config.lb b/targets/dell/s1850/Config.lb
deleted file mode 100644
index bf22a18..0000000
--- a/targets/dell/s1850/Config.lb
+++ /dev/null
@@ -1,25 +0,0 @@
-target s1850
-mainboard dell/s1850
-
-option CONFIG_ROM_SIZE=1024*1024
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-
-#romimage "normal"
-#	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-#	option COREBOOT_EXTRA_VERSION=".0Normal"
-##	payload ../../../payloads/filo.elf
-#	payload /tmp/filo.elf
-#end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload ../../../payloads/filo.elf
-	payload /tmp/filo.elf
-end
-
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/digitallogic/adl855pc/Config.lb b/targets/digitallogic/adl855pc/Config.lb
deleted file mode 100644
index 9102137..0000000
--- a/targets/digitallogic/adl855pc/Config.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-# Sample config file for adl855pc
-# This will make a target directory of ./adl855pc
-
-target adl855pc
-mainboard digitallogic/adl855pc
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-	payload /etc/hosts
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload /etc/hosts
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/digitallogic/msm586seg/Config-abuild.lb b/targets/digitallogic/msm586seg/Config-abuild.lb
deleted file mode 100644
index 7193da1..0000000
--- a/targets/digitallogic/msm586seg/Config-abuild.lb
+++ /dev/null
@@ -1,17 +0,0 @@
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
diff --git a/targets/digitallogic/msm586seg/Config.lb b/targets/digitallogic/msm586seg/Config.lb
deleted file mode 100644
index a2ad579..0000000
--- a/targets/digitallogic/msm586seg/Config.lb
+++ /dev/null
@@ -1,32 +0,0 @@
-target msm586seg
-mainboard digitallogic/msm586seg
-
-
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=3
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=3
-option CONFIG_COMPRESS=0
-
-option CONFIG_CONSOLE_VGA=0
-
-#romimage "normal"
-#	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x10000
-#	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /etc/hosts
-#end
-
-romimage "fallback" 
-	option CONFIG_FALLBACK_SIZE = 256 * 1024
-#	option CONFIG_ROM_SIZE=512*1024
-#	option CONFIG_ROM_SECTION_SIZE=512*1024
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=32 * 1024 # 0x8000
-	option CONFIG_ROM_IMAGE_SIZE=128 * 1024 # 0x10000
-#	option CONFIG_ROM_IMAGE_SIZE=512 * 1024 # 0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload ../../filo.elf
-#	payload ../../eepro100--ide_disk.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
diff --git a/targets/digitallogic/msm800sev/Config.lb b/targets/digitallogic/msm800sev/Config.lb
deleted file mode 100644
index 473556b..0000000
--- a/targets/digitallogic/msm800sev/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-# Config file for the digitallogic msm800sev
-
-target msm800sev
-mainboard digitallogic/msm800sev
-
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-## leave 36k for vsa 
-##
-option CONFIG_ROM_SIZE = 1024*1024 - 36 * 1024
-
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE=64*1024
-
-option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload ../payload.elf 
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
diff --git a/targets/eaglelion/5bcm/Config.lb b/targets/eaglelion/5bcm/Config.lb
deleted file mode 100644
index 323ab7a..0000000
--- a/targets/eaglelion/5bcm/Config.lb
+++ /dev/null
@@ -1,31 +0,0 @@
-# Config file for the Eaglelion 5BCM motherboard
-# This will make a target directory of 5bcm
-
-target 5bcm
-mainboard eaglelion/5bcm
-
-option CONFIG_ROM_SIZE=256*1024
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-#	payload /etc/hosts
-	payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebia
-#	payload /etc/hosts
-	payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/emulation/qemu-x86/Config-abuild.lb b/targets/emulation/qemu-x86/Config-abuild.lb
deleted file mode 100644
index 27fba1a..0000000
--- a/targets/emulation/qemu-x86/Config-abuild.lb
+++ /dev/null
@@ -1,18 +0,0 @@
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-
diff --git a/targets/emulation/qemu-x86/Config-car.lb b/targets/emulation/qemu-x86/Config-car.lb
deleted file mode 100644
index 1d2032e..0000000
--- a/targets/emulation/qemu-x86/Config-car.lb
+++ /dev/null
@@ -1,26 +0,0 @@
-# This will make a target directory of ./emulation_qemu-x86
-
-target qemu-x86-car
-mainboard emulation/qemu-x86
-
-option CONFIG_USE_DCACHE_RAM=1
-option CONFIG_USE_INIT=1
-option CONFIG_ROM_SIZE=512*1024
-option CONFIG_USE_INIT=1
-option CONFIG_USE_PRINTK_IN_CAR=1
-
-option CC="gcc -m32"
-
-option CONFIG_GENERATE_PIRQ_TABLE=1
-option CONFIG_IRQ_SLOT_COUNT=6
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION="-GRUB2"
-#	payload /home/stepan/core.img
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-
diff --git a/targets/emulation/qemu-x86/Config-lab.lb b/targets/emulation/qemu-x86/Config-lab.lb
deleted file mode 100644
index 34786e5..0000000
--- a/targets/emulation/qemu-x86/Config-lab.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-# This will make a target directory of ./emulation_qemu-x86
-
-target qemu-x86
-mainboard emulation/qemu-x86
-
-option CONFIG_ROM_SIZE=2048*1024
-option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-option CONFIG_PRECOMPRESSED_PAYLOAD=1
-
-option CC="gcc -m32"
-
-option CONFIG_GENERATE_PIRQ_TABLE=1
-option CONFIG_IRQ_SLOT_COUNT=6
-
-romimage "fallback" 
-	option COREBOOT_EXTRA_VERSION="-LAB"
-	payload ../payload.elf.lzma
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-
diff --git a/targets/emulation/qemu-x86/Config.OLPC.lb b/targets/emulation/qemu-x86/Config.OLPC.lb
deleted file mode 100644
index 718fd8d..0000000
--- a/targets/emulation/qemu-x86/Config.OLPC.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-# This will make a target directory of ./emulation_qemu-x86
-
-target qemu-x86-OLPC
-mainboard emulation/qemu-x86
-
-option CONFIG_ROM_SIZE=1024*1024 - (128 * 1024)
-option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-option CONFIG_PRECOMPRESSED_PAYLOAD=0
-
-option CC="gcc -m32"
-
-option CONFIG_GENERATE_PIRQ_TABLE=1
-option CONFIG_IRQ_SLOT_COUNT=6
-
-romimage "fallback" 
-	option COREBOOT_EXTRA_VERSION="-OpenBIOS"
-	payload /tmp/olpcpayload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-
diff --git a/targets/emulation/qemu-x86/Config.lb b/targets/emulation/qemu-x86/Config.lb
deleted file mode 100644
index 3425baa..0000000
--- a/targets/emulation/qemu-x86/Config.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-# This will make a target directory of ./emulation_qemu-x86
-
-target qemu-x86
-mainboard emulation/qemu-x86
-
-option CONFIG_ROM_SIZE=512*1024
-
-option CC="gcc -m32"
-
-option CONFIG_GENERATE_PIRQ_TABLE=1
-option CONFIG_IRQ_SLOT_COUNT=6
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION="-GRUB2"
-#	payload /home/stepan/core.img
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-
diff --git a/targets/gigabyte/ga-6bxc/Config.lb b/targets/gigabyte/ga-6bxc/Config.lb
deleted file mode 100644
index 4efbcb6..0000000
--- a/targets/gigabyte/ga-6bxc/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target ga-6bxc
-mainboard gigabyte/ga-6bxc
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "GIGABYTE"
-option CONFIG_MAINBOARD_PART_NUMBER = "GA-6BXC"
-
-option CONFIG_IRQ_SLOT_COUNT = 6
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/gigabyte/ga_2761gxdk/Config-abuild.lb b/targets/gigabyte/ga_2761gxdk/Config-abuild.lb
deleted file mode 100644
index d946796..0000000
--- a/targets/gigabyte/ga_2761gxdk/Config-abuild.lb
+++ /dev/null
@@ -1,57 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE = 512*1024
-
-romimage "normal"
-        option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-Normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-        option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-Fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-        option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION=".0-Failover"
-end
-
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/gigabyte/ga_2761gxdk/Config.lb b/targets/gigabyte/ga_2761gxdk/Config.lb
deleted file mode 100644
index 1266366..0000000
--- a/targets/gigabyte/ga_2761gxdk/Config.lb
+++ /dev/null
@@ -1,58 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
-## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target ga_2761gxdk
-mainboard gigabyte/ga_2761gxdk
-
-romimage "normal"
-#       32K for VGA BIOS
-        option CONFIG_ROM_SIZE = (512*1024 - 32*1024)
-
-        option CONFIG_USE_FAILOVER_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=0x20000
-        option CONFIG_XIP_ROM_SIZE=0x40000
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#	payload ../../../../payloads/filo_uda1.elf
-	payload ../payload.elf
-end
-
-romimage "fallback"
-        option CONFIG_USE_FAILOVER_IMAGE=0
-        option CONFIG_USE_FALLBACK_IMAGE=1
-        option CONFIG_ROM_IMAGE_SIZE=0x20000
-        option CONFIG_XIP_ROM_SIZE=0x40000
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#	payload ../../../../payloads/filo_uda1.elf
-	payload ../payload.elf
-end
-
-romimage "failover"
-        option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-#       buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-        buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/gigabyte/ga_2761gxdk/README b/targets/gigabyte/ga_2761gxdk/README
deleted file mode 100644
index ed850d8..0000000
--- a/targets/gigabyte/ga_2761gxdk/README
+++ /dev/null
@@ -1,3 +0,0 @@
-## How to append VGA bios?
-
-cat 6330VGA.rom ga_2761gxdk/coreboot.rom > ga_2761gxdk.bin
diff --git a/targets/gigabyte/ga_2761gxdk/VERSION b/targets/gigabyte/ga_2761gxdk/VERSION
deleted file mode 100644
index f982358..0000000
--- a/targets/gigabyte/ga_2761gxdk/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_ga_2761gxdk
diff --git a/targets/gigabyte/m57sli/Config-abuild.lb b/targets/gigabyte/m57sli/Config-abuild.lb
deleted file mode 100644
index 22e527e..0000000
--- a/targets/gigabyte/m57sli/Config-abuild.lb
+++ /dev/null
@@ -1,34 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/gigabyte/m57sli/Config-lab.lb b/targets/gigabyte/m57sli/Config-lab.lb
deleted file mode 100644
index 6ed4f11..0000000
--- a/targets/gigabyte/m57sli/Config-lab.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Sample config file for 
-
-target m57sli
-mainboard gigabyte/m57sli
-
-option CONFIG_ROM_SIZE=0x100000
-option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000)
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf.lzma
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
diff --git a/targets/gigabyte/m57sli/Config.lb b/targets/gigabyte/m57sli/Config.lb
deleted file mode 100644
index 3634a64..0000000
--- a/targets/gigabyte/m57sli/Config.lb
+++ /dev/null
@@ -1,56 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target m57sli
-mainboard gigabyte/m57sli
-
-option CONFIG_ROM_SIZE = 0x100000
-
-romimage "normal"
-        option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_BASE=0xFFF80000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback" 
-        option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_BASE=0xFFF80000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf
-end
-
-romimage "failover"
-        option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/gigabyte/m57sli/Config.lb.kernel b/targets/gigabyte/m57sli/Config.lb.kernel
deleted file mode 100644
index e5952e3..0000000
--- a/targets/gigabyte/m57sli/Config.lb.kernel
+++ /dev/null
@@ -1,77 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Sample config file for 
-
-target m57sli
-mainboard gigabyte/m57sli
-
-option CONFIG_ROM_SIZE=0x200000
-option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000)
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/memtest
-#	payload ../../../../payloads/adlo.elf
-#	payload ../../../../payloads/e1000_vga.zelf
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5.4.2.zelf
-	payload /home/yhlu/olpc-payload.elf.lzma
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/filo_hda2_novga.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" 
diff --git a/targets/gigabyte/m57sli/VERSION b/targets/gigabyte/m57sli/VERSION
deleted file mode 100644
index b116945..0000000
--- a/targets/gigabyte/m57sli/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_m57sli
diff --git a/targets/hp/dl145_g3/Config.lb b/targets/hp/dl145_g3/Config.lb
deleted file mode 100644
index c66a94f..0000000
--- a/targets/hp/dl145_g3/Config.lb
+++ /dev/null
@@ -1,39 +0,0 @@
-##
-## This file is part of the Coreboot project.
-##
-## Copyright (C) 2007 University of Mannheim
-## Written by Philipp Degler <pdegler@rumms.uni-mannheim.de>
-## Copyright (C) 2009 University of Heidelberg
-## Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target dl145_g3
-mainboard hp/dl145_g3
-
-option CONFIG_ROM_SIZE= 1024*1024
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ./bios.bin.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-
-pci_rom ./matrox.rom vendor_id=0x102b device_id=0x0522
-
diff --git a/targets/hp/dl145_g3/VERSION b/targets/hp/dl145_g3/VERSION
deleted file mode 100644
index f9ae5cd..0000000
--- a/targets/hp/dl145_g3/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_dl145_g3
diff --git a/targets/hp/e_vectra_p2706t/Config.lb b/targets/hp/e_vectra_p2706t/Config.lb
deleted file mode 100644
index ff36c57..0000000
--- a/targets/hp/e_vectra_p2706t/Config.lb
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target e_vectra_p2706t
-mainboard hp/e_vectra_p2706t
-
-option CONFIG_ROM_SIZE = 512 * 1024
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-
-# pci_rom /tmp/vgabios.rom vendor_id=0x8086 device_id=0x7125
-# pci_rom /tmp/ethbios.rom vendor_id=0x10b7 device_id=0x9200
-
diff --git a/targets/ibm/e325/Config.lb b/targets/ibm/e325/Config.lb
deleted file mode 100644
index cd1a055..0000000
--- a/targets/ibm/e325/Config.lb
+++ /dev/null
@@ -1,34 +0,0 @@
-# the IBM E325
-# This will make a target directory of ./e325
-
-target e325
-
-mainboard ibm/e325
-
-#
-###
-### Compute the start location and size size of
-### The coreboot bootloader.
-###
-
-#
-# Arima hdama
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload ../../filo.elf
-	payload ../../../payloads/filo.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload ../../filo.elf
-	payload ../../../payloads/filo.elf
-# use this to test a build if you don't have the etherboot
-#	payload /etc/hosts
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/ibm/e326/Config-abuild.lb b/targets/ibm/e326/Config-abuild.lb
deleted file mode 100644
index 12c3abf..0000000
--- a/targets/ibm/e326/Config-abuild.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=512*1024
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/ibm/e326/Config.lb b/targets/ibm/e326/Config.lb
deleted file mode 100644
index 34ba0d9..0000000
--- a/targets/ibm/e326/Config.lb
+++ /dev/null
@@ -1,30 +0,0 @@
-# the IBM E326
-# This will make a target directory of ./e326
-
-target e326
-mainboard ibm/e326
-
-###
-### Compute the start location and size size of
-### The coreboot bootloader.
-###
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload ../../filo.elf
-	payload ../../../payloads/filo.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload ../../filo.elf
-	payload ../../../payloads/filo.elf
-# use this to test a build if you don't have the etherboot
-#	payload /etc/hosts
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/iei/juki-511p/Config-abuild.lb b/targets/iei/juki-511p/Config-abuild.lb
deleted file mode 100644
index 0f6d5da..0000000
--- a/targets/iei/juki-511p/Config-abuild.lb
+++ /dev/null
@@ -1,25 +0,0 @@
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=256*1024
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-Normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-Fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/iei/juki-511p/Config.lb b/targets/iei/juki-511p/Config.lb
deleted file mode 100644
index bcccf92..0000000
--- a/targets/iei/juki-511p/Config.lb
+++ /dev/null
@@ -1,37 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target juki-511p
-mainboard iei/juki-511p
-
-option CONFIG_ROM_SIZE=256*1024
-
-option CONFIG_GENERATE_PIRQ_TABLE=1
-
-option CONFIG_COMPRESS=0
-option CONFIG_PRECOMPRESSED_PAYLOAD=0
-
-romimage "fallback"
-	option CONFIG_ROM_IMAGE_SIZE=64*1024
-	option COREBOOT_EXTRA_VERSION="-filo"
-	payload ../../filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/iei/nova4899r/Config.lb b/targets/iei/nova4899r/Config.lb
deleted file mode 100644
index 7a7e108..0000000
--- a/targets/iei/nova4899r/Config.lb
+++ /dev/null
@@ -1,47 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 Luis Correia <luis.f.correia@gmail.com>
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
- 
-# Config file for the IEI nova4899r motherboard
-# This will make a target directory of nova4899r
-
-target nova4899r
-mainboard iei/nova4899r
-
-#option CONFIG_ROM_SIZE=256*1024
-
-#from OLPC definitions
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B=1
-#option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-#option CONFIG_PRECOMPRESSED_PAYLOAD=0
-# leave 128k for vsa and 32k for VGA code
-option CONFIG_ROM_SIZE=(256*1024)-(128*1024)-(32*1024)
-option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=64*1024
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload /opt/coreboot-SVN/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-#"normal" 
diff --git a/targets/iei/pcisa-lx-800-r10/Config.lb b/targets/iei/pcisa-lx-800-r10/Config.lb
deleted file mode 100644
index 8b84806..0000000
--- a/targets/iei/pcisa-lx-800-r10/Config.lb
+++ /dev/null
@@ -1,46 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target pcisa-lx-800-r10
-mainboard iei/pcisa-lx-800-r10
-
-option CONFIG_COMPRESS = 0
-option CONFIG_PRECOMPRESSED_PAYLOAD = 0
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0
-option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0
-
-# Leave 36k for VSA.
-option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024)
-# option CONFIG_ROM_SIZE = (2048 * 1024) - (36 * 1024)
-# Leave 36k for VSA, 1152k for bzImage and 750k for initrd.
-# option CONFIG_ROM_SIZE = (2048 * 1024) - (36 * 1024) - (1152 * 1024) - (750 * 1024)
-option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 80 * 1024
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/intel/d945gclf/Config-abuild.lb b/targets/intel/d945gclf/Config-abuild.lb
deleted file mode 100644
index 5b6df72..0000000
--- a/targets/intel/d945gclf/Config-abuild.lb
+++ /dev/null
@@ -1,46 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=512*1024
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-#pci_rom ../../../misc/d945gclf-pci8086,2772.rom vendor_id=0x8086 device_id=0x2772
-
diff --git a/targets/intel/d945gclf/Config.lb b/targets/intel/d945gclf/Config.lb
deleted file mode 100644
index 1c3057b..0000000
--- a/targets/intel/d945gclf/Config.lb
+++ /dev/null
@@ -1,10 +0,0 @@
-target d945gclf
-mainboard intel/d945gclf
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-
diff --git a/targets/intel/eagleheights/Config.lb b/targets/intel/eagleheights/Config.lb
deleted file mode 100644
index b04c6a0..0000000
--- a/targets/intel/eagleheights/Config.lb
+++ /dev/null
@@ -1,32 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target eagleheights
-mainboard intel/eagleheights
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-option CONFIG_ROM_SIZE = 1024 * 1024
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/intel/mtarvon/Config.lb b/targets/intel/mtarvon/Config.lb
deleted file mode 100644
index 87dc4f9..0000000
--- a/targets/intel/mtarvon/Config.lb
+++ /dev/null
@@ -1,40 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target mtarvon
-mainboard intel/mtarvon
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-option CONFIG_ROM_SIZE = 2 * 1024 * 1024
-
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
-## (including payload) will use
-option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/intel/truxton/Config.lb b/targets/intel/truxton/Config.lb
deleted file mode 100644
index fd6a7bd..0000000
--- a/targets/intel/truxton/Config.lb
+++ /dev/null
@@ -1,40 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target truxton
-mainboard intel/truxton
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-option CONFIG_ROM_SIZE = 2 * 1024 * 1024
-
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
-## (including payload) will use
-option CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	payload /tmp/seabios.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/intel/xe7501devkit/Config.lb b/targets/intel/xe7501devkit/Config.lb
deleted file mode 100644
index 8e70031..0000000
--- a/targets/intel/xe7501devkit/Config.lb
+++ /dev/null
@@ -1,37 +0,0 @@
-target xe7501devkit
-mainboard intel/xe7501devkit
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-option CONFIG_ROM_SIZE = 192*1024
-
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE = 0x1B000
-
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image 
-## (including payload) will use
-option CONFIG_FALLBACK_SIZE = 0
-
-
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../../../../../memtest86/memtest
-#       payload ../../../../../../../etherboot/src/bin/e1000.zelf
-        payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf
-#       payload ../../../../../../../QNX/BSP/images/qnxbasesmp.elf
-end
-
-#NOTE: CMOS currently not supported due to conflicts with factory BIOS
-#      Thus no support for fallback boot.
-#romimage "fallback" 
-#	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../../../../../memtest86/memtest
-#       payload ../../../../../../../etherboot/src/bin/e1000.zelf
-#       payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf
-#end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/intel/xe7501devkit/VERSION b/targets/intel/xe7501devkit/VERSION
deleted file mode 100644
index 49d5957..0000000
--- a/targets/intel/xe7501devkit/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-0.1
diff --git a/targets/iwill/dk8_htx/Config-abuild.lb b/targets/iwill/dk8_htx/Config-abuild.lb
deleted file mode 100644
index 22e527e..0000000
--- a/targets/iwill/dk8_htx/Config-abuild.lb
+++ /dev/null
@@ -1,34 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/iwill/dk8_htx/Config.lb b/targets/iwill/dk8_htx/Config.lb
deleted file mode 100644
index 460dcc4..0000000
--- a/targets/iwill/dk8_htx/Config.lb
+++ /dev/null
@@ -1,74 +0,0 @@
-
-target dk8_htx
-mainboard iwill/dk8_htx
-
-# serengeti_leopard
-romimage "normal"
-#       48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 475136
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 425984 
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 458752 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#       payload ../../../../payloads/e1000--filo.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/memtest
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/iwill/dk8_htx/VERSION b/targets/iwill/dk8_htx/VERSION
deleted file mode 100644
index 5755a12..0000000
--- a/targets/iwill/dk8_htx/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_dk8_htx
diff --git a/targets/iwill/dk8s2/Config.lb b/targets/iwill/dk8s2/Config.lb
deleted file mode 100644
index ff9aeb4..0000000
--- a/targets/iwill/dk8s2/Config.lb
+++ /dev/null
@@ -1,159 +0,0 @@
-# Sample config file for 
-# the Iwill DK8S2
-# This will make a target directory of ./dk8s2
-
-target dk8s2
-
-mainboard iwill/dk8s2
-
-option CONFIG_HAVE_HARD_RESET=1
-
-option CONFIG_HAVE_OPTION_TABLE=1
-option CONFIG_HAVE_MP_TABLE=1
-option CONFIG_ROM_SIZE=1024*1024
-
-option CONFIG_HAVE_FALLBACK_BOOT=1
-  
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-#
-###
-### Build code to export a programmable irq routing table
-###
-option CONFIG_GENERATE_PIRQ_TABLE=1
-option CONFIG_IRQ_SLOT_COUNT=12
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=2
-#option CONFIG_LOGICAL_CPUS=1
-option CONFIG_MAX_PHYSICAL_CPUS=2
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### CONFIG_MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable 
-### caching from 640KB-1MB using fixed MTRRs 
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option CONFIG_MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option CONFIG_MAINBOARD_PART_NUMBER="DK8S2"
-option CONFIG_MAINBOARD_VENDOR="IWILL"
-#
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-#option CONFIG_FALLBACK_SIZE=524288
-#option CONFIG_FALLBACK_SIZE=98304
-option CONFIG_FALLBACK_SIZE=131072
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-option CONFIG_ROM_IMAGE_SIZE=65536
- 
-
-###
-### Compute where this copy of coreboot will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-#option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option CONFIG_TTYS0_BAUD=115200
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-## At a maximum only compile in this level of debugging
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=7
-
-#option CONFIG_DEBUG=1
-
-#
-
-## Coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x004000
-
-##
-## Use a 32K stack
-##
-option CONFIG_STACK_SIZE=0x8000 
-
-##
-## Use a 56K heap
-##
-option CONFIG_HEAP_SIZE=0xe000
-
-#
-###
-### Compute the start location and size size of
-### The coreboot bootloader.
-###
-option CONFIG_ROM_PAYLOAD     = 1
-
-#
-# 
-romimage "normal"
-#	48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#	48K for SCSI FW and 48K for ATI ROM
-#	option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_SECTION_SIZE  = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
-	option CONFIG_ROM_SECTION_OFFSET= 0
-
-#	option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
-        option CONFIG_XIP_ROM_SIZE = 65536
-
-	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
-
-	payload /usr/src/filo-0.4.1_btext/filo.elf
-#	payload /usr/src/filo-0.4.2/filo.elf
-end
-
-romimage "fallback" 
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_SECTION_SIZE  = CONFIG_FALLBACK_SIZE
-	option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
-
-#	option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
-	option CONFIG_XIP_ROM_SIZE = 65536
-	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
-
-	payload ../../../payloads/filo.elf
-#	payload /usr/src/filo-0.4.2/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/iwill/dk8x/Config.lb b/targets/iwill/dk8x/Config.lb
deleted file mode 100644
index 54bd4a1..0000000
--- a/targets/iwill/dk8x/Config.lb
+++ /dev/null
@@ -1,159 +0,0 @@
-# Sample config file for 
-# the Iwill DK8X
-# This will make a target directory of ./dk8x
-
-target dk8x
-
-mainboard iwill/dk8x
-
-option CONFIG_HAVE_HARD_RESET=1
-
-option CONFIG_HAVE_OPTION_TABLE=1
-option CONFIG_HAVE_MP_TABLE=1
-option CONFIG_ROM_SIZE=1024*1024
-
-option CONFIG_HAVE_FALLBACK_BOOT=1
-  
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-#
-###
-### Build code to export a programmable irq routing table
-###
-option CONFIG_GENERATE_PIRQ_TABLE=1
-option CONFIG_IRQ_SLOT_COUNT=12
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=2
-#option CONFIG_LOGICAL_CPUS=1
-option CONFIG_MAX_PHYSICAL_CPUS=2
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### CONFIG_MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable 
-### caching from 640KB-1MB using fixed MTRRs 
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option CONFIG_MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option CONFIG_MAINBOARD_PART_NUMBER="DK8X"
-option CONFIG_MAINBOARD_VENDOR="IWILL"
-#
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-#option CONFIG_FALLBACK_SIZE=524288
-#option CONFIG_FALLBACK_SIZE=98304
-option CONFIG_FALLBACK_SIZE=131072
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-option CONFIG_ROM_IMAGE_SIZE=65536
- 
-
-###
-### Compute where this copy of coreboot will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-#option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option CONFIG_TTYS0_BAUD=115200
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-## At a maximum only compile in this level of debugging
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=7
-
-#option CONFIG_DEBUG=1
-
-#
-
-## Coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x004000
-
-##
-## Use a 32K stack
-##
-option CONFIG_STACK_SIZE=0x8000 
-
-##
-## Use a 56K heap
-##
-option CONFIG_HEAP_SIZE=0xe000
-
-#
-###
-### Compute the start location and size size of
-### The coreboot bootloader.
-###
-option CONFIG_ROM_PAYLOAD     = 1
-
-#
-# 
-romimage "normal"
-#	48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#	48K for SCSI FW and 48K for ATI ROM
-#	option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_SECTION_SIZE  = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
-	option CONFIG_ROM_SECTION_OFFSET= 0
-
-#	option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
-        option CONFIG_XIP_ROM_SIZE = 65536
-
-	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
-
-	payload /usr/src/filo-0.4.1_btext/filo.elf
-#	payload /usr/src/filo-0.4.2/filo.elf
-end
-
-romimage "fallback" 
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_SECTION_SIZE  = CONFIG_FALLBACK_SIZE
-	option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
-
-#	option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
-	option CONFIG_XIP_ROM_SIZE = 65536
-	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
-
-	payload ../../../payloads/filo.elf
-#	payload /usr/src/filo-0.4.2/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/jetway/j7f24/Config-abuild.lb b/targets/jetway/j7f24/Config-abuild.lb
deleted file mode 100644
index 620685b..0000000
--- a/targets/jetway/j7f24/Config-abuild.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=512*1024
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/jetway/j7f24/Config.lb b/targets/jetway/j7f24/Config.lb
deleted file mode 100644
index 61da2c6..0000000
--- a/targets/jetway/j7f24/Config.lb
+++ /dev/null
@@ -1,45 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target jetway-j7f24
-mainboard jetway/j7f24
-
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-option CONFIG_CONSOLE_SERIAL8250=1
-
-# coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x00004000
-
-#
-# If space is allotted for a VGA BIOS,
-# generate the final ROM like this:
-# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
-#
-#option CONFIG_ROM_SIZE = (512 * 1024) - (63 * 1024) - (64 * 1024)
-option CONFIG_ROM_SIZE = (512 * 1024)
-
-romimage "fallback"
-	option COREBOOT_EXTRA_VERSION = "-j7f24"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/kontron/986lcd-m/Config-abuild.lb b/targets/kontron/986lcd-m/Config-abuild.lb
deleted file mode 100644
index 67fc542..0000000
--- a/targets/kontron/986lcd-m/Config-abuild.lb
+++ /dev/null
@@ -1,29 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=1024*1024
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-#pci_rom ../../../misc/kontron-pci8086,27a2.rom vendor_id=0x8086 device_id=0x27a2
-
diff --git a/targets/kontron/986lcd-m/Config.lb b/targets/kontron/986lcd-m/Config.lb
deleted file mode 100644
index 5a4fd47..0000000
--- a/targets/kontron/986lcd-m/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-target kontron_986lcd_m
-mainboard kontron/986lcd-m
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-option CONFIG_ROM_SIZE = 1024 * 1024
-
-option HAVE_HIGH_TABLES=1
-option MAXIMUM_CONSOLE_LOGLEVEL=9
-option DEFAULT_CONSOLE_LOGLEVEL=9
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	payload /tmp/bios.bin.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-
-# Uncomment this and fix the path to your VGA BIOS blob (~/amipci_01.20 here) for on-board VGA support.
-# See http://www.coreboot.org/Kontron_986LCD-M_mITX for details.
-# pci_rom ~/amipci_01.20 vendor_id=0x8086 device_id=0x27a2
-
diff --git a/targets/kontron/kt690/Config-abuild.lb b/targets/kontron/kt690/Config-abuild.lb
deleted file mode 100644
index 77f35aa..0000000
--- a/targets/kontron/kt690/Config-abuild.lb
+++ /dev/null
@@ -1,31 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=1024*1024
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-        option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-        option CONFIG_USE_FALLBACK_IMAGE=1
-        option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-#pci_rom ../../../misc/KT690/pci1002,791f.rom vendor_id=0x1002 device_id=0x791f
diff --git a/targets/kontron/kt690/Config.lb b/targets/kontron/kt690/Config.lb
deleted file mode 100644
index eeb40a4..0000000
--- a/targets/kontron/kt690/Config.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-# This will make a target directory of ./dbm690t
-
-target kt690
-mainboard kontron/kt690
-
-romimage "normal"
-	option CONFIG_ROM_SIZE = 1024*1024 - 55808
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	payload ../payload.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/kontron/kt690/VERSION b/targets/kontron/kt690/VERSION
deleted file mode 100644
index 8e0a930..0000000
--- a/targets/kontron/kt690/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_kt690
diff --git a/targets/lippert/frontrunner/Config.lb b/targets/lippert/frontrunner/Config.lb
deleted file mode 100644
index cee55cd..0000000
--- a/targets/lippert/frontrunner/Config.lb
+++ /dev/null
@@ -1,33 +0,0 @@
-# Config file for the AMD rumba motherboard
-# This will make a target directory of rumba
-
-target frontrunner
-mainboard lippert/frontrunner
-
-option CONFIG_ROM_SIZE=256*1024
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-#	payload /etc/hosts
-#	payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
-	payload /tmp/filo.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebia
-#	payload /etc/hosts
-#	payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/lippert/roadrunner-lx/Config.lb b/targets/lippert/roadrunner-lx/Config.lb
deleted file mode 100644
index 1fb1bbb..0000000
--- a/targets/lippert/roadrunner-lx/Config.lb
+++ /dev/null
@@ -1,54 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Config file for the LiPPERT Cool RoadRunner-LX,		--JR 10/2008
-# based on Config.lb for the AMD Geode LX/5536 DB800 platform.
-
-target roadrunner-lx
-mainboard lippert/roadrunner-lx
-
-# HACK to get the right TSC support.
-option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0
-option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0
-
-# Leave 36k for VSA. Usually board is equipped with a 512 KB FWH (LPC) flash,
-# however it can be replaced with a 1 MB chip.
-option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024)
-#option CONFIG_ROM_SIZE = (1024 * 1024) - (36 * 1024)
-option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
-
-#option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
-#option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
-
-# Saves space on CONFIG_ROM_IMAGE_SIZE, but decompression costs a second on boot.
-option CONFIG_COMPRESS = 1
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-	option COREBOOT_EXTRA_VERSION = ".0"
-	payload ../payload.elf
-	# If getting payload from IDE
-	# payload /dev/null
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/lippert/spacerunner-lx/Config.lb b/targets/lippert/spacerunner-lx/Config.lb
deleted file mode 100644
index 9fa4b5a..0000000
--- a/targets/lippert/spacerunner-lx/Config.lb
+++ /dev/null
@@ -1,54 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## Based on Config.lb for the AMD Geode LX/5536 DB800 platform.
-
-# Config file for the LiPPERT Cool SpaceRunner-LX.		--JR 10/2008
-
-target spacerunner-lx
-mainboard lippert/spacerunner-lx
-
-# HACK to get the right TSC support.
-option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0
-option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0
-
-# Leave 36k for VSA. Board is equipped with a 1 MB SPI flash, however, due to
-# limitations of the IT8712F Super I/O, only the top 512 KB are directly mapped.
-option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024)
-option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
-
-#option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
-#option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
-
-# Saves space on CONFIG_ROM_IMAGE_SIZE, but decompression costs a second on boot.
-option CONFIG_COMPRESS = 1
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-	option COREBOOT_EXTRA_VERSION = ".0"
-	payload ../payload.elf
-	# If getting payload from IDE
-	# payload /dev/null
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/mitac/6513wu/Config.lb b/targets/mitac/6513wu/Config.lb
deleted file mode 100644
index 0c7e7fe..0000000
--- a/targets/mitac/6513wu/Config.lb
+++ /dev/null
@@ -1,41 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target 6513wu
-mainboard mitac/6513wu
-
-# Leave 32 KB free for VGA BIOS.
-option CONFIG_ROM_SIZE = (512 - 32) * 1024
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/msi/ms6119/Config.lb b/targets/msi/ms6119/Config.lb
deleted file mode 100644
index 271b7f0..0000000
--- a/targets/msi/ms6119/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target ms6119
-mainboard msi/ms6119
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "MSI"
-option CONFIG_MAINBOARD_PART_NUMBER = "MS-6119"
-
-option CONFIG_IRQ_SLOT_COUNT = 7
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/msi/ms6147/Config.lb b/targets/msi/ms6147/Config.lb
deleted file mode 100644
index 02a6035..0000000
--- a/targets/msi/ms6147/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Mats Erik Andersson <mats.andersson@gisladisker.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target ms6147
-mainboard msi/ms6147
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "MSI"
-option CONFIG_MAINBOARD_PART_NUMBER = "MS-6147"
-
-option CONFIG_IRQ_SLOT_COUNT = 8
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/msi/ms6156/Config.lb b/targets/msi/ms6156/Config.lb
deleted file mode 100644
index ee7dfef..0000000
--- a/targets/msi/ms6156/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target ms6156
-mainboard msi/ms6156
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "MSI"
-option CONFIG_MAINBOARD_PART_NUMBER = "MS-6156"
-
-option CONFIG_IRQ_SLOT_COUNT = 7
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/msi/ms6178/Config.lb b/targets/msi/ms6178/Config.lb
deleted file mode 100644
index 77a6d54..0000000
--- a/targets/msi/ms6178/Config.lb
+++ /dev/null
@@ -1,53 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target ms6178
-mainboard msi/ms6178
-
-option CONFIG_ROM_SIZE = 512 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "MSI"
-option CONFIG_MAINBOARD_PART_NUMBER = "MS-6178"
-
-option CONFIG_IRQ_SLOT_COUNT = 4
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-option CONFIG_VIDEO_MB = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-
-pci_rom /tmp/i810.vga vendor_id=0x8086 device_id=0x7121
-
diff --git a/targets/msi/ms7135/Config-abuild.lb b/targets/msi/ms7135/Config-abuild.lb
deleted file mode 100644
index 22e527e..0000000
--- a/targets/msi/ms7135/Config-abuild.lb
+++ /dev/null
@@ -1,34 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/msi/ms7135/Config.lb b/targets/msi/ms7135/Config.lb
deleted file mode 100644
index 6d9b215..0000000
--- a/targets/msi/ms7135/Config.lb
+++ /dev/null
@@ -1,61 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
-## (Thanks to LSRA University of Mannheim for their support)
-## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target ms7135
-mainboard msi/ms7135
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-option CONFIG_GENERATE_PIRQ_TABLE=1
-option CONFIG_CONSOLE_VGA=1
-option CONFIG_PCI_ROM_RUN=1
-
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="_Normal"
-	payload /tmp/payload.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="_Fallback"
-	payload /tmp/payload.elf
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-	option COREBOOT_EXTRA_VERSION="_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/msi/ms7260/Config-abuild.lb b/targets/msi/ms7260/Config-abuild.lb
deleted file mode 100644
index ab9568f..0000000
--- a/targets/msi/ms7260/Config-abuild.lb
+++ /dev/null
@@ -1,54 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE = 0
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE = 0
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE = 1
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE
-	option COREBOOT_EXTRA_VERSION = ".0Failover"
-end
-
-# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/msi/ms7260/Config.lb b/targets/msi/ms7260/Config.lb
deleted file mode 100644
index 04a33ff..0000000
--- a/targets/msi/ms7260/Config.lb
+++ /dev/null
@@ -1,58 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target ms7260
-mainboard msi/ms7260
-
-option CONFIG_ROM_SIZE = 512 * 1024
-
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1   # NRV2B compression
-# option CONFIG_COMPRESSED_PAYLOAD_LZMA = 1    # LZMA compression
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE = 0
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-	option CONFIG_XIP_ROM_SIZE = 256 * 1024
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-#	payload /tmp/filo.elf
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE = 0
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-	option CONFIG_XIP_ROM_SIZE = 256 * 1024
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-#	payload /tmp/filo.elf
-	payload ../payload.elf
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE = 1
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE
-	option COREBOOT_EXTRA_VERSION = ".0Failover"
-end
-
-# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/msi/ms9185/Config-abuild.lb b/targets/msi/ms9185/Config-abuild.lb
deleted file mode 100644
index c88403e..0000000
--- a/targets/msi/ms9185/Config-abuild.lb
+++ /dev/null
@@ -1,26 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/msi/ms9185/Config.lb b/targets/msi/ms9185/Config.lb
deleted file mode 100644
index a7cf3f1..0000000
--- a/targets/msi/ms9185/Config.lb
+++ /dev/null
@@ -1,94 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 MSI
-## Written by bxshi <bingxunshi@gmail.com> for MSI.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Sample config file for
-# the msi ms9185
-# This will make a target directory of ./ms9185
-
-target ms9185
-mainboard msi/ms9185
-
-# ms9185
-romimage "normal"
-# 36k for ATI option rom
-       option CONFIG_ROM_SIZE = 512*1024-36*1024
-#      option CONFIG_ROM_SIZE = 524288
-#       option CONFIG_ROM_SIZE = 425984
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 458752
-       option CONFIG_USE_FALLBACK_IMAGE=0
-#      option CONFIG_ROM_IMAGE_SIZE=0x13800
-#      option CONFIG_ROM_IMAGE_SIZE=0x18800
-       option CONFIG_ROM_IMAGE_SIZE=0x20000
-#      option CONFIG_ROM_IMAGE_SIZE=0x15800
-       option CONFIG_XIP_ROM_SIZE=0x40000
-       option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#      payload ../../../payloads/tg3.zelf
-#      payload ../../../../payloads/tg3_vga.zelf
-#      payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#      payload /filo.elf
-       payload /tg3--filo.elf
-#      payload ../../../../payloads/e1000_vga.zelf
-#      payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#      payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "fallback"
-       option CONFIG_USE_FALLBACK_IMAGE=1
-#      option CONFIG_ROM_IMAGE_SIZE=0x13800
-#      option CONFIG_ROM_IMAGE_SIZE=0x19800
-       option CONFIG_ROM_IMAGE_SIZE=0x20000
-#      option CONFIG_ROM_IMAGE_SIZE=0x15800
-       option CONFIG_XIP_ROM_SIZE=0x40000
-       option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#      payload ../../../payloads/tg3.zelf
-#      payload ../../../../payloads/tg3_vga.zelf
-#      payload ../../../../payloads/memtest
-#      payload ../../../../payloads/e1000_vga.zelf
-#      payload ../../../../payloads/filo_hda.zelf
-#      payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#      payload /filo.elf
-       payload /tg3--filo.elf
-#      payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#      payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/msi/ms9282/Config-abuild.lb b/targets/msi/ms9282/Config-abuild.lb
deleted file mode 100644
index c88403e..0000000
--- a/targets/msi/ms9282/Config-abuild.lb
+++ /dev/null
@@ -1,26 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/msi/ms9282/Config.lb b/targets/msi/ms9282/Config.lb
deleted file mode 100644
index 0f3c87e..0000000
--- a/targets/msi/ms9282/Config.lb
+++ /dev/null
@@ -1,91 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 MSI
-## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target ms9282
-mainboard msi/ms9282
-
-romimage "normal"
-#       48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 475136
-       option CONFIG_ROM_SIZE = 512*1024-36*1024
-#      option CONFIG_ROM_SIZE = 524288
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 425984
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 458752
-       option CONFIG_USE_FALLBACK_IMAGE=0
-#      option CONFIG_ROM_IMAGE_SIZE=0x13800
-#      option CONFIG_ROM_IMAGE_SIZE=0x18800
-       option CONFIG_ROM_IMAGE_SIZE=0x20000
-#      option CONFIG_ROM_IMAGE_SIZE=0x15800
-       option CONFIG_XIP_ROM_SIZE=0x40000
-       option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#      payload ../../../payloads/tg3.zelf
-#      payload ../../../../payloads/tg3_vga.zelf
-#      payload /filo.elf
-       payload /tg3--filo.elf
-#      payload /payload
-#      payload ../../../../payloads/e1000_vga.zelf
-#      payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#      payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "fallback"
-       option CONFIG_USE_FALLBACK_IMAGE=1
-#      option CONFIG_ROM_IMAGE_SIZE=0x13800
-#      option CONFIG_ROM_IMAGE_SIZE=0x19800
-       option CONFIG_ROM_IMAGE_SIZE=0x20000
-#      option CONFIG_ROM_IMAGE_SIZE=0x15800
-       option CONFIG_XIP_ROM_SIZE=0x40000
-       option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#      payload ../../../payloads/tg3.zelf
-#      payload ../../../../payloads/tg3_vga.zelf
-#      payload ../../../../payloads/memtest
-#      payload ../../../../payloads/e1000_vga.zelf
-#      payload ../../../../payloads/filo_hda.zelf
-#      payload /filo.elf
-       payload /tg3--filo.elf
-#      payload /payload
-#      payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#      payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/nec/powermate2000/Config.lb b/targets/nec/powermate2000/Config.lb
deleted file mode 100644
index 72e29cc..0000000
--- a/targets/nec/powermate2000/Config.lb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target powermate2000
-mainboard nec/powermate2000
-
-option CONFIG_ROM_SIZE = 512 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "NEC"
-option CONFIG_MAINBOARD_PART_NUMBER = "PowerMate 2000"
-
-option CONFIG_IRQ_SLOT_COUNT = 5
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/newisys/khepri/Config.lb b/targets/newisys/khepri/Config.lb
deleted file mode 100644
index d624b9c..0000000
--- a/targets/newisys/khepri/Config.lb
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# Sample config file for Newisys Khepri systems
-#
-
-# Target directory for khepri build
-target khepri
-	
-mainboard newisys/khepri
-
-# set target C compiler to 32bit gcc.
-option CC="gcc -m32"
-
-# Configuration options.
-
-option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-option  CONFIG_CONSOLE_SERIAL8250=1
-
-# Size of the image. Khepri comes with 512k per default.
-option CONFIG_ROM_SIZE=512*1024
-
-option CONFIG_HAVE_OPTION_TABLE=1
-option CONFIG_ROM_PAYLOAD=1
-option CONFIG_HAVE_FALLBACK_BOOT=1
-
-option CONFIG_FALLBACK_SIZE=131072
-
-## Coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x00004000
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="-Khepri-Normal"
-	payload ../../../payloads/tg3--ide_disk.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="-Khepri-Fallback"
-	payload ../../../payloads/tg3--ide_disk.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/nvidia/l1_2pvv/Config-abuild.lb b/targets/nvidia/l1_2pvv/Config-abuild.lb
deleted file mode 100644
index 22e527e..0000000
--- a/targets/nvidia/l1_2pvv/Config-abuild.lb
+++ /dev/null
@@ -1,34 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/nvidia/l1_2pvv/Config.lb b/targets/nvidia/l1_2pvv/Config.lb
deleted file mode 100644
index 87171a7..0000000
--- a/targets/nvidia/l1_2pvv/Config.lb
+++ /dev/null
@@ -1,108 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Sample config file for 
-# the nvidia l1_2pvv 
-# This will make a target directory of ./l1_2pvv
-
-target l1_2pvv
-mainboard nvidia/l1_2pvv
-
-# serengeti_leopard
-romimage "normal"
-#       48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 475136
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 425984 
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 458752 
-#       44k for atixx.rom
-#        option CONFIG_ROM_SIZE = 479232
-        option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x18800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
-	payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "fallback" 
-        option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/memtest
-#	payload ../../../../payloads/e1000_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/adlo.elf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../../payloads/forcedeth_mcp55_filo_hda2.zelf
-	payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
-#	payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "failover"
-        option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/nvidia/l1_2pvv/Config.lb.kernel b/targets/nvidia/l1_2pvv/Config.lb.kernel
deleted file mode 100644
index 70e95e4..0000000
--- a/targets/nvidia/l1_2pvv/Config.lb.kernel
+++ /dev/null
@@ -1,79 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Sample config file for 
-# the nvidia l1_2pvv 
-# This will make a target directory of ./l1_2pvv
-
-target l1_2pvv
-mainboard nvidia/l1_2pvv
-
-option CONFIG_ROM_SIZE=0x200000
-option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000)
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/memtest
-#	payload ../../../../payloads/adlo.elf
-#	payload ../../../../payloads/e1000_vga.zelf
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5.4.2.zelf
-	payload /home/yhlu/olpc-payload.elf.lzma
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/filo_hda2_novga.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" 
diff --git a/targets/nvidia/l1_2pvv/VERSION b/targets/nvidia/l1_2pvv/VERSION
deleted file mode 100644
index adcbabb..0000000
--- a/targets/nvidia/l1_2pvv/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_l1_2pvv
diff --git a/targets/olpc/btest/Config.lb b/targets/olpc/btest/Config.lb
deleted file mode 100644
index df9d0fe..0000000
--- a/targets/olpc/btest/Config.lb
+++ /dev/null
@@ -1,24 +0,0 @@
-# Config file for the olpc btest
-
-target btest
-mainboard olpc/btest
-
-# Don't let coreboot compress the payload
-#option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-#option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-#option CONFIG_PRECOMPRESSED_PAYLOAD=0
-
-# leave 64k for vsa and 64k for EC code
-option CONFIG_ROM_SIZE=(1024*1024)-(64*1024)-(64*1024)
-option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 3
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 3
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=32*1024
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload /tmp/olpcpayload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
diff --git a/targets/olpc/rev_a/Config.1M.lb b/targets/olpc/rev_a/Config.1M.lb
deleted file mode 100644
index bd7d4bb..0000000
--- a/targets/olpc/rev_a/Config.1M.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-# Config file for the olpc rev_a
-
-target rev_a_1M
-mainboard olpc/rev_a
-
-# Don't let coreboot compress the payload
-# option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-#option CONFIG_PRECOMPRESSED_PAYLOAD=1
-
-# leave 64k for vsa
-option CONFIG_ROM_SIZE=(1024*1024)-(64*1024)
-option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=32*1024
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload /tmp/olpcpayload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
diff --git a/targets/olpc/rev_a/Config.SPI.lb b/targets/olpc/rev_a/Config.SPI.lb
deleted file mode 100644
index 70e4522..0000000
--- a/targets/olpc/rev_a/Config.SPI.lb
+++ /dev/null
@@ -1,24 +0,0 @@
-# Config file for the olpc rev_a
-
-target rev_a_1M
-mainboard olpc/rev_a
-
-# Don't let coreboot compress the payload
-#option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-#option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-#option CONFIG_PRECOMPRESSED_PAYLOAD=0
-
-# leave 64k for vsa and 64k for EC code
-option CONFIG_ROM_SIZE=(1024*1024)-(64*1024)-(64*1024)
-option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=32*1024
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload /tmp/olpcpayload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
diff --git a/targets/olpc/rev_a/Config.kernel.lb b/targets/olpc/rev_a/Config.kernel.lb
deleted file mode 100644
index 15b5a6f..0000000
--- a/targets/olpc/rev_a/Config.kernel.lb
+++ /dev/null
@@ -1,35 +0,0 @@
-# Config file for the olpc rev_a
-
-target rev_a
-mainboard olpc/rev_a
-
-option CONFIG_ROM_SIZE=7*128*1024
-option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
-
-#romimage "normal"
-#	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x10000
-#	option COREBOOT_EXTRA_VERSION=".0Normal"
-##	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-##	payload ../../../../tg3--ide_disk.zelf	
-##	payload ../../../../../lnxieepro100.ebi
-##	payload /etc/hosts
-##	payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
-#	payload /tmp/filo.elf
-#end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebia
-#	payload /etc/hosts
-#	payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
-#	payload /tmp/filo.elf
-	payload /tmp/olpc
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/olpc/rev_a/Config.lb b/targets/olpc/rev_a/Config.lb
deleted file mode 100644
index 2825877..0000000
--- a/targets/olpc/rev_a/Config.lb
+++ /dev/null
@@ -1,20 +0,0 @@
-# Config file for the olpc rev_a
-
-target rev_a
-mainboard olpc/rev_a
-
-# leave 64k for vsa
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-option CONFIG_ROM_SIZE=512*1024-64*1024
-option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=32*1024
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-	payload /tmp/olpcpayload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
diff --git a/targets/pcengines/alix1c/Config.lb b/targets/pcengines/alix1c/Config.lb
deleted file mode 100644
index 2c7a376..0000000
--- a/targets/pcengines/alix1c/Config.lb
+++ /dev/null
@@ -1,25 +0,0 @@
-target alix1c
-mainboard pcengines/alix1c
-
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads). Leave 36k for VSA.
-option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024)
-
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE = (64 * 1024)
-
-option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 3
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload ../payload.elf 
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
diff --git a/targets/rca/rm4100/Config-abuild.lb b/targets/rca/rm4100/Config-abuild.lb
deleted file mode 100644
index 78a4bcb..0000000
--- a/targets/rca/rm4100/Config-abuild.lb
+++ /dev/null
@@ -1,37 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-
diff --git a/targets/rca/rm4100/Config.lb b/targets/rca/rm4100/Config.lb
deleted file mode 100644
index 7d17739..0000000
--- a/targets/rca/rm4100/Config.lb
+++ /dev/null
@@ -1,64 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target rm4100
-mainboard rca/rm4100
-
-##
-## Total number of bytes allocated for coreboot use
-## (fallback images and payloads).
-##
-# option CONFIG_ROM_SIZE = 1024 * 1024
-## For VGA BIOS (-64k)
-option CONFIG_ROM_SIZE = (1024 * 1024) - (64 * 1024)
-
-##
-## VGA Console
-## NOTE: to initialize VGA, you need to copy 
-## the VGA option ROM from the factory BIOS
-## 0=disable  1=enable
-##
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-option CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 1
-
-##
-## Choose the amount of memory pre-allocated for VGA
-## 0 for No memory pre-allocated (Graphics memory Disabled)
-## 512 for DVMT (UMA) mode, 512K of memory pre-allocated for frame buffer
-## 1 for DVMT (UMA) mode, 1M of memory pre-allocated for frame buffer
-## 8 for DVMT (UMA) mode, 8M of memory pre-allocated for frame buffer
-##
-option CONFIG_VIDEO_MB = 8
-
-##
-## Request this level of debugging output
-##
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 7
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
-	option COREBOOT_EXTRA_VERSION = "_RM4100"
-	payload /tmp/filo.elf
-#	payload /tmp/eb-5.4.3-eepro100.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/roda/rk886ex/Config-abuild.lb b/targets/roda/rk886ex/Config-abuild.lb
deleted file mode 100644
index bb84632..0000000
--- a/targets/roda/rk886ex/Config-abuild.lb
+++ /dev/null
@@ -1,29 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=1024*1024
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-#pci_rom ../../../misc/roda-pci8086,27a2.rom vendor_id=0x8086 device_id=0x27a2
-
diff --git a/targets/roda/rk886ex/Config.lb b/targets/roda/rk886ex/Config.lb
deleted file mode 100644
index 309bcd6..0000000
--- a/targets/roda/rk886ex/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-target roda_rk886ex
-mainboard roda_rk886ex
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-option CONFIG_ROM_SIZE = 1024*1024
-
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE = 0x26000
-
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image 
-## (including payload) will use
-option CONFIG_FALLBACK_SIZE = ROM_SIZE
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	#payload $(HOME)/filo.elf
-	payload /dev/zero
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/soyo/sy-6ba-plus-iii/Config.lb b/targets/soyo/sy-6ba-plus-iii/Config.lb
deleted file mode 100644
index 98bd666..0000000
--- a/targets/soyo/sy-6ba-plus-iii/Config.lb
+++ /dev/null
@@ -1,51 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target sy-6ba-plus-iii
-mainboard soyo/sy-6ba-plus-iii
-
-option CONFIG_ROM_SIZE = 256 * 1024
-# option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
-
-option CONFIG_MAINBOARD_VENDOR = "Soyo"
-option CONFIG_MAINBOARD_PART_NUMBER = "SY-6BA+ III"
-
-option CONFIG_IRQ_SLOT_COUNT = 7
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload ../payload.elf
-end
-
-# buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/sunw/ultra40/Config.lb b/targets/sunw/ultra40/Config.lb
deleted file mode 100644
index cbd7f96..0000000
--- a/targets/sunw/ultra40/Config.lb
+++ /dev/null
@@ -1,73 +0,0 @@
-# Sample config file for 
-# the sunw ultra40
-# This will make a target directory of ./ultra40
-
-target ultra40
-mainboard sunw/ultra40
-
-option CONFIG_ROM_SIZE=512*1024
-# sunw ultra40
-romimage "normal"
-#       48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 48K for ATI ROM
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-#	64K for NIC option 48K for Raid option rom
-#	option CONFIG_ROM_SIZE = 512*1024-64*1024-48*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga.zelf
-	payload /etc/hosts
-#	payload ../../../payloads/forcedeth_vga.zelf
-#	payload ../../../payloads/forcedeth--filo_hda2_vga_5_4.zelf
-#	payload ../../../../../../elf/ram0_2.5_2.6.11.tiny.elf
-#	payload ../../../../../../elf/ram0_2.5_2.6.12.tiny.elf
-#	payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	 payload ../../../payloads/tg3_vga.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vgax.zelf
-#        payload ../../../payloads/tg3--filo_hda2_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga.zelf
-	payload /etc/hosts
-#	payload ../../../payloads/forcedeth_vga.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vgax.zelf
-#        payload ../../../payloads/tg3--filo_hda2_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/sunw/ultra40/VERSION b/targets/sunw/ultra40/VERSION
deleted file mode 100644
index e8cefbb..0000000
--- a/targets/sunw/ultra40/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_ultra40
diff --git a/targets/supermicro/h8dme/Config-abuild.lb b/targets/supermicro/h8dme/Config-abuild.lb
deleted file mode 100644
index 76ff766..0000000
--- a/targets/supermicro/h8dme/Config-abuild.lb
+++ /dev/null
@@ -1,35 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-        option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-        option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION=".0-failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/supermicro/h8dme/Config-lab.lb b/targets/supermicro/h8dme/Config-lab.lb
deleted file mode 100644
index 4f81981..0000000
--- a/targets/supermicro/h8dme/Config-lab.lb
+++ /dev/null
@@ -1,45 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target h8dmre
-mainboard supermicro/h8dme
-
-option CONFIG_ROM_SIZE=0x100000
-# 44K for ATI ROM in 1M; 4K for failover
-option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0xC000)
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x18000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf.lzma
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
diff --git a/targets/supermicro/h8dme/Config.lb b/targets/supermicro/h8dme/Config.lb
deleted file mode 100644
index 559371e..0000000
--- a/targets/supermicro/h8dme/Config.lb
+++ /dev/null
@@ -1,48 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target h8dme
-mainboard supermicro/h8dme
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf
-end
-
-romimage "failover"
-        option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/supermicro/h8dme/Config.lb.kernel b/targets/supermicro/h8dme/Config.lb.kernel
deleted file mode 100644
index bf09ee5..0000000
--- a/targets/supermicro/h8dme/Config.lb.kernel
+++ /dev/null
@@ -1,45 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target h8dme
-mainboard supermicro/h8dme
-
-option CONFIG_ROM_SIZE=0x200000
-option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000)
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x18000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
diff --git a/targets/supermicro/h8dme/VERSION b/targets/supermicro/h8dme/VERSION
deleted file mode 100644
index a8d7962..0000000
--- a/targets/supermicro/h8dme/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_h8dme
diff --git a/targets/supermicro/h8dmr/Config-abuild.lb b/targets/supermicro/h8dmr/Config-abuild.lb
deleted file mode 100644
index d531301..0000000
--- a/targets/supermicro/h8dmr/Config-abuild.lb
+++ /dev/null
@@ -1,30 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-  option CONFIG_USE_FAILOVER_IMAGE=1
-  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-  option COREBOOT_EXTRA_VERSION=".0-failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/supermicro/h8dmr/Config-lab.lb b/targets/supermicro/h8dmr/Config-lab.lb
deleted file mode 100644
index 6fcde1f..0000000
--- a/targets/supermicro/h8dmr/Config-lab.lb
+++ /dev/null
@@ -1,48 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target h8dmr
-mainboard supermicro/h8dmr
-
-option CONFIG_ROM_SIZE=0x100000
-# 44K for ATI ROM in 1M; 4K for failover
-option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0xC000)
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x18000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf.lzma
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
diff --git a/targets/supermicro/h8dmr/Config.lb b/targets/supermicro/h8dmr/Config.lb
deleted file mode 100644
index ac4266d..0000000
--- a/targets/supermicro/h8dmr/Config.lb
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target h8dmr
-mainboard supermicro/h8dmr
-
-romimage "normal"
-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-  payload ../payload.elf
-end
-
-romimage "fallback" 
-  option CONFIG_USE_FALLBACK_IMAGE=1
-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-  payload ../payload.elf
-end
-
-romimage "failover"
-  option CONFIG_USE_FAILOVER_IMAGE=1
-  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/supermicro/h8dmr/Config.lb.kernel b/targets/supermicro/h8dmr/Config.lb.kernel
deleted file mode 100644
index 4b8cf7c..0000000
--- a/targets/supermicro/h8dmr/Config.lb.kernel
+++ /dev/null
@@ -1,75 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target h8dmr
-mainboard supermicro/h8dmr
-
-option CONFIG_ROM_SIZE=0x200000
-option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000)
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x18000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/memtest
-#	payload ../../../../payloads/adlo.elf
-#	payload ../../../../payloads/e1000_vga.zelf
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5.4.2.zelf
-	payload /home/yhlu/olpc-payload.elf.lzma
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/filo_hda2_novga.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" 
diff --git a/targets/supermicro/h8dmr/VERSION b/targets/supermicro/h8dmr/VERSION
deleted file mode 100644
index 8097f11..0000000
--- a/targets/supermicro/h8dmr/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_h8dmr
diff --git a/targets/supermicro/h8dmr_fam10/Config-abuild.lb b/targets/supermicro/h8dmr_fam10/Config-abuild.lb
deleted file mode 100644
index 1730ce0..0000000
--- a/targets/supermicro/h8dmr_fam10/Config-abuild.lb
+++ /dev/null
@@ -1,30 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option COREBOOT_EXTRA_VERSION=".0-failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/supermicro/h8dmr_fam10/Config-lab.lb b/targets/supermicro/h8dmr_fam10/Config-lab.lb
deleted file mode 100644
index 8f29de2..0000000
--- a/targets/supermicro/h8dmr_fam10/Config-lab.lb
+++ /dev/null
@@ -1,37 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target h8dmr_fam10
-mainboard supermicro/h8dmr_fam10
-
-romimage "fallback" 
-  option CONFIG_USE_FALLBACK_IMAGE=1
-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf
-end
-
-romimage "failover"
-  option CONFIG_USE_FAILOVER_IMAGE=1
-  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
diff --git a/targets/supermicro/h8dmr_fam10/Config.lb b/targets/supermicro/h8dmr_fam10/Config.lb
deleted file mode 100644
index 9713912..0000000
--- a/targets/supermicro/h8dmr_fam10/Config.lb
+++ /dev/null
@@ -1,44 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target h8dmr_fam10
-mainboard supermicro/h8dmr_fam10
-
-romimage "normal"
-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	payload /personal/projects/coreboot/payloads/seabios.elf
-#	payload ../payload.elf
-end
-
-romimage "fallback" 
-  option CONFIG_USE_FALLBACK_IMAGE=1
-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload /personal/projects/coreboot/payloads/seabios.elf
-#	payload ../payload.elf
-end
-
-romimage "failover"
-  option CONFIG_USE_FAILOVER_IMAGE=1
-  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/supermicro/h8dmr_fam10/Config.lb.kernel b/targets/supermicro/h8dmr_fam10/Config.lb.kernel
deleted file mode 100644
index 8e8c5a4..0000000
--- a/targets/supermicro/h8dmr_fam10/Config.lb.kernel
+++ /dev/null
@@ -1,75 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target h8dmr
-mainboard supermicro/h8dmr
-
-option ROM_SIZE=0x200000
-option FALLBACK_SIZE=(ROM_SIZE-0x1000)
-
-romimage "fallback" 
-	option USE_FAILOVER_IMAGE=0
-	option USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-#	option ROM_IMAGE_SIZE=0x19800
-	option ROM_IMAGE_SIZE=0x18000
-#	option ROM_IMAGE_SIZE=0x15800
-#	option ROM_IMAGE_SIZE=0x13800
-	option XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/memtest
-#	payload ../../../../payloads/adlo.elf
-#	payload ../../../../payloads/e1000_vga.zelf
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5.4.2.zelf
-	payload /home/yhlu/olpc-payload.elf.lzma
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/filo_hda2_novga.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "failover"
-	option USE_FAILOVER_IMAGE=1
-        option USE_FALLBACK_IMAGE=0
-        option ROM_IMAGE_SIZE=FAILOVER_SIZE
-        option XIP_ROM_SIZE=FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-
-buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
-#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" 
diff --git a/targets/supermicro/h8dmr_fam10/VERSION b/targets/supermicro/h8dmr_fam10/VERSION
deleted file mode 100644
index 427f2d0..0000000
--- a/targets/supermicro/h8dmr_fam10/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_h8dmr_fam10
diff --git a/targets/supermicro/h8qme_fam10/Config.lb b/targets/supermicro/h8qme_fam10/Config.lb
deleted file mode 100644
index cdd5df5..0000000
--- a/targets/supermicro/h8qme_fam10/Config.lb
+++ /dev/null
@@ -1,46 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target h8qme_fam10
-mainboard supermicro/h8qme_fam10
-
-romimage "normal"
-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	payload ../seabios.elf
-#  payload /home/knut/Documents/final/filo.elf
-#	payload ../payload.elf
-end
-
-romimage "fallback" 
-  option CONFIG_USE_FALLBACK_IMAGE=1
-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../seabios.elf
-#  payload /home/knut/Documents/final/filo.elf
-#	payload ../payload.elf
-end
-
-romimage "failover"
-  option CONFIG_USE_FAILOVER_IMAGE=1
-  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/supermicro/h8qme_fam10/VERSION b/targets/supermicro/h8qme_fam10/VERSION
deleted file mode 100644
index 98f66ec..0000000
--- a/targets/supermicro/h8qme_fam10/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_h8qme_fam10
diff --git a/targets/technexion/tim5690/Config-abuild.lb b/targets/technexion/tim5690/Config-abuild.lb
deleted file mode 100644
index b47f5ce..0000000
--- a/targets/technexion/tim5690/Config-abuild.lb
+++ /dev/null
@@ -1,26 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/technexion/tim5690/Config.lb b/targets/technexion/tim5690/Config.lb
deleted file mode 100644
index 9affa07..0000000
--- a/targets/technexion/tim5690/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-# This will make a target directory of ./tim5690
-
-target tim5690
-mainboard technexion/tim5690
-
-option CONFIG_ROM_SIZE = (1024*512)
-#option CONFIG_ROM_SIZE = (1024*1024*1)
-#option CONFIG_ROM_SIZE = (1024*1024*2)
-#option CONFIG_ROM_SIZE = (1024*1024*4)
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-
-	payload ../payload.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" 
-
diff --git a/targets/technexion/tim8690/Config-abuild.lb b/targets/technexion/tim8690/Config-abuild.lb
deleted file mode 100644
index b47f5ce..0000000
--- a/targets/technexion/tim8690/Config-abuild.lb
+++ /dev/null
@@ -1,26 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/technexion/tim8690/Config.lb b/targets/technexion/tim8690/Config.lb
deleted file mode 100644
index 8a25959..0000000
--- a/targets/technexion/tim8690/Config.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-# This will make a target directory of ./tim8690
-
-target tim8690
-mainboard technexion/tim8690
-
-
-romimage "normal"
-	option CONFIG_ROM_SIZE = 1024*512 - 55808
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	payload /home/daniel/mypayloads/link
-end
-
-romimage "fallback" 
-	option CONFIG_FALLBACK_SIZE= 1024*512 - 55808
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	payload /home/daniel/mypayloads/link
-
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" 
-
-
-
diff --git a/targets/technologic/ts5300/Config-abuild.lb b/targets/technologic/ts5300/Config-abuild.lb
deleted file mode 100644
index 5ae820b..0000000
--- a/targets/technologic/ts5300/Config-abuild.lb
+++ /dev/null
@@ -1,17 +0,0 @@
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-Fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
diff --git a/targets/technologic/ts5300/Config.lb b/targets/technologic/ts5300/Config.lb
deleted file mode 100644
index 720ff07..0000000
--- a/targets/technologic/ts5300/Config.lb
+++ /dev/null
@@ -1,32 +0,0 @@
-# Sample config file for Technologic Systems TS5300
-# This will make a target directory of ./technologic_ts5300
-
-target technologic_ts5300
-mainboard technologic/ts5300
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=3
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=3
-option CONFIG_COMPRESS=1
-
-#romimage "normal"
-#	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x10000
-#	option COREBOOT_EXTRA_VERSION=".0-Normal"
-#	payload /etc/hosts
-#end
-
-romimage "fallback" 
-	option CONFIG_FALLBACK_SIZE = 128 * 1024
-#	option CONFIG_ROM_SIZE=512*1024
-#	option CONFIG_ROM_SECTION_SIZE=512*1024
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=32 * 1024 # 0x8000
-#	option CONFIG_ROM_IMAGE_SIZE=48 * 1024 # 0x8000
-#	option CONFIG_ROM_IMAGE_SIZE=64 * 1024 # 0x10000
-#	option CONFIG_ROM_IMAGE_SIZE=512 * 1024 # 0x10000
-#	option COREBOOT_EXTRA_VERSION=".0-Fallback"
-	option COREBOOT_EXTRA_VERSION=".0"
-	payload /home/stepan/filo-ts5300.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
diff --git a/targets/televideo/tc7020/Config.lb b/targets/televideo/tc7020/Config.lb
deleted file mode 100644
index c078209..0000000
--- a/targets/televideo/tc7020/Config.lb
+++ /dev/null
@@ -1,51 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Kenji Noguchi <tokyo246@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target tc7020
-mainboard televideo/tc7020
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-option CONFIG_GX1_VIDEO = 1
-option CONFIG_GX1_VIDEOMODE = 0
-option CONFIG_SPLASH_GRAPHIC = 1
-option CONFIG_VIDEO_MB = 2
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/thomson/ip1000/Config-abuild.lb b/targets/thomson/ip1000/Config-abuild.lb
deleted file mode 100644
index f606128..0000000
--- a/targets/thomson/ip1000/Config-abuild.lb
+++ /dev/null
@@ -1,37 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-
diff --git a/targets/thomson/ip1000/Config.lb b/targets/thomson/ip1000/Config.lb
deleted file mode 100644
index b3d2c3b..0000000
--- a/targets/thomson/ip1000/Config.lb
+++ /dev/null
@@ -1,64 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target ip1000
-mainboard thomson/ip1000
-
-##
-## Total number of bytes allocated for coreboot use
-## (fallback images and payloads).
-##
-# option CONFIG_ROM_SIZE = 1024 * 1024
-## For VGA BIOS (-64k)
-option CONFIG_ROM_SIZE = (1024 * 1024) - (64 * 1024)
-
-##
-## VGA Console
-## NOTE: to initialize VGA, you need to copy 
-## the VGA option ROM from the factory BIOS
-## 0=disable  1=enable
-##
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-option CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 1
-
-##
-## Choose the amount of memory pre-allocated for VGA
-## 0 for No memory pre-allocated (Graphics memory Disabled)
-## 512 for DVMT (UMA) mode, 512K of memory pre-allocated for frame buffer
-## 1 for DVMT (UMA) mode, 1M of memory pre-allocated for frame buffer
-## 8 for DVMT (UMA) mode, 8M of memory pre-allocated for frame buffer
-##
-option CONFIG_VIDEO_MB = 8
-
-##
-## Request this level of debugging output
-##
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 7
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
-	option COREBOOT_EXTRA_VERSION = "_IP1000"
-	payload /tmp/filo.elf
-#	payload /tmp/eb-5.4.3-eepro100.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/tyan/s1846/Config.lb b/targets/tyan/s1846/Config.lb
deleted file mode 100644
index 9a2c030..0000000
--- a/targets/tyan/s1846/Config.lb
+++ /dev/null
@@ -1,50 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target s1846
-mainboard tyan/s1846
-
-option CONFIG_ROM_SIZE = 256 * 1024
-
-option CONFIG_MAINBOARD_VENDOR = "Tyan"
-option CONFIG_MAINBOARD_PART_NUMBER = "S1846"
-
-# TODO: Add/fix PIRQ table.
-option CONFIG_GENERATE_PIRQ_TABLE = 0
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_PCI_ROM_RUN = 1
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option COREBOOT_EXTRA_VERSION = ".0Normal"
-	payload /tmp/filo.elf
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2735/Config.lb b/targets/tyan/s2735/Config.lb
deleted file mode 100644
index a67f24f..0000000
--- a/targets/tyan/s2735/Config.lb
+++ /dev/null
@@ -1,45 +0,0 @@
-# Sample config file for 
-# the Tyan s2735 
-# This will make a target directory of ./s2735
-
-target s2735
-mainboard tyan/s2735
-
-# Tyan s2735
-romimage "normal"
-#       48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=0x11800
-        option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-        option CONFIG_ROM_IMAGE_SIZE=0x11800
-        option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2735/VERSION b/targets/tyan/s2735/VERSION
deleted file mode 100644
index 242cc8e..0000000
--- a/targets/tyan/s2735/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s2735
diff --git a/targets/tyan/s2735/ns2735 b/targets/tyan/s2735/ns2735
deleted file mode 100644
index 09a1565..0000000
--- a/targets/tyan/s2735/ns2735
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/bash
-TYANMB=s2735
-cd "$TYANMB"
-make
-#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-#cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cp -f $TYANMB"_coreboot.rom" /home/yhlu/
diff --git a/targets/tyan/s2850/Config.lb b/targets/tyan/s2850/Config.lb
deleted file mode 100644
index f6e6f3c..0000000
--- a/targets/tyan/s2850/Config.lb
+++ /dev/null
@@ -1,61 +0,0 @@
-# Sample config file for 
-# the Tyan s2850 
-# This will make a target directory of ./s2850
-
-target s2850
-mainboard tyan/s2850
-
-# Tyan s2850
-romimage "normal"
-#       48K for SCSI FW or ATI ROM
-        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13c00
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../payloads/tg3--filo_u_hda2_vga.zelf
-#        payload ../../../payloads/tg3--filo_hda2_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13c00
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../payloads/tg3--filo_u_hda2_vga.zelf
-#        payload ../../../payloads/tg3--filo_hda2_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2850/VERSION b/targets/tyan/s2850/VERSION
deleted file mode 100644
index eaf624a..0000000
--- a/targets/tyan/s2850/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s2850
diff --git a/targets/tyan/s2850/atix.txt b/targets/tyan/s2850/atix.txt
deleted file mode 100644
index ae0a5c8..0000000
--- a/targets/tyan/s2850/atix.txt
+++ /dev/null
@@ -1 +0,0 @@
-dd if=/dev/mem of=atix.rom skip=1536 count=96
diff --git a/targets/tyan/s2850/ns2850 b/targets/tyan/s2850/ns2850
deleted file mode 100644
index dd08630..0000000
--- a/targets/tyan/s2850/ns2850
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/bash
-TYANMB=s2850
-cd "$TYANMB"
-make
-cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-#cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-#cp -f $TYANMB"_coreboot.rom" /home/yhlu/
diff --git a/targets/tyan/s2875/Config.lb b/targets/tyan/s2875/Config.lb
deleted file mode 100644
index 50346f7..0000000
--- a/targets/tyan/s2875/Config.lb
+++ /dev/null
@@ -1,59 +0,0 @@
-# Sample config file for 
-# the Tyan s2875
-# This will make a target directory of ./s2875
-
-target s2875
-mainboard tyan/s2875
-
-# Tyan s2875
-romimage "normal"
-#       48K for SCSI FW or ATI ROM
-        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#        payload ../../../payloads/tg3--filo_hda2_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#        payload ../../../payloads/tg3--filo_hda2_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2875/ns2875 b/targets/tyan/s2875/ns2875
deleted file mode 100644
index 98287d0..0000000
--- a/targets/tyan/s2875/ns2875
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/bash
-TYANMB=s2875
-cd "$TYANMB"
-make
-cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cp -f $TYANMB"_coreboot.rom" /home/yhlu/
diff --git a/targets/tyan/s2880/Config.lb b/targets/tyan/s2880/Config.lb
deleted file mode 100644
index fc40941..0000000
--- a/targets/tyan/s2880/Config.lb
+++ /dev/null
@@ -1,59 +0,0 @@
-# Sample config file for 
-# the Tyan s2880
-# This will make a target directory of ./s2880
-
-target s2880
-mainboard tyan/s2880
-
-# Tyan s2880
-romimage "normal"
-#       48K for SCSI FW or ATI ROM
-        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 48K for ATI ROM
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-	payload ../../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#        payload ../../../payloads/tg3--filo_hda2_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#        payload ../../../payloads/tg3--filo_hda2_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2880/VERSION b/targets/tyan/s2880/VERSION
deleted file mode 100644
index 6f304b5..0000000
--- a/targets/tyan/s2880/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s2880
diff --git a/targets/tyan/s2880/ns2880 b/targets/tyan/s2880/ns2880
deleted file mode 100644
index 509e77f..0000000
--- a/targets/tyan/s2880/ns2880
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/bash
-TYANMB=s2880
-cd "$TYANMB"
-make
-#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-#cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cp -f $TYANMB"_coreboot.rom" /home/yhlu/
diff --git a/targets/tyan/s2881/Config-lab.lb b/targets/tyan/s2881/Config-lab.lb
deleted file mode 100644
index ad42a5d..0000000
--- a/targets/tyan/s2881/Config-lab.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-# Sample config file for 
-# the Tyan s2881 
-# This will make a target directory of ./s2881
-
-target s2881
-mainboard tyan/s2881
-
-option CONFIG_ROM_SIZE=0x100000
-# 36K for ATI ROM in 1M
-option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x9000)
-
-# Tyan s2881
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf.lzma
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/tyan/s2881/Config.lb b/targets/tyan/s2881/Config.lb
deleted file mode 100644
index 010e704..0000000
--- a/targets/tyan/s2881/Config.lb
+++ /dev/null
@@ -1,61 +0,0 @@
-# Sample config file for 
-# the Tyan s2881 
-# This will make a target directory of ./s2881
-
-target s2881
-mainboard tyan/s2881
-
-# Tyan s2881
-romimage "normal"
-#       36K for ATI ROM
-        option CONFIG_ROM_SIZE = 512*1024-36*1024
-#       48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 36K for ATI ROM
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024-36*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13000
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-        option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	 payload ../../../payloads/tg3--filo_hda1_vga_md1.zelf
-#	payload ../../../payloads/tg3--filo_btext_hda2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-	payload ../payload.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13000
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-        option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../payloads/tg3--filo_hda1_vga_md1.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#	payload ../../../payloads/tg3--filo_btext_hda2.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2881/VERSION b/targets/tyan/s2881/VERSION
deleted file mode 100644
index e1c66a3..0000000
--- a/targets/tyan/s2881/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s2881
diff --git a/targets/tyan/s2881/ns2881 b/targets/tyan/s2881/ns2881
deleted file mode 100644
index c3ebf40..0000000
--- a/targets/tyan/s2881/ns2881
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/bash
-TYANMB=s2881
-cd "$TYANMB"
-make
-#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-#cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cp -f $TYANMB"_coreboot.rom" /home/yhlu/
diff --git a/targets/tyan/s2882/Config-lab.lb b/targets/tyan/s2882/Config-lab.lb
deleted file mode 100644
index f72ee2d..0000000
--- a/targets/tyan/s2882/Config-lab.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-# Sample config file for 
-# the Tyan s2882 
-# This will make a target directory of ./s2882
-
-target s2882
-mainboard tyan/s2882
-
-option CONFIG_ROM_SIZE=0x100000
-# 36K for ATI ROM in 1M
-option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x9000)
-
-# Tyan s2882
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf.lzma
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/tyan/s2882/Config.lb b/targets/tyan/s2882/Config.lb
deleted file mode 100644
index a6d3747..0000000
--- a/targets/tyan/s2882/Config.lb
+++ /dev/null
@@ -1,53 +0,0 @@
-# Sample config file for 
-# the Tyan s2882 
-# This will make a target directory of ./s2882
-
-target s2882
-mainboard tyan/s2882
-
-# Tyan s2882
-romimage "normal"
-#       36K for ATI ROM
-        option CONFIG_ROM_SIZE = 512*1024-36*1024
-#       48K for SCSI FW and 36K for ATI ROM
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024-36*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-        option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-	payload ../payload.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-        option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2882/VERSION b/targets/tyan/s2882/VERSION
deleted file mode 100644
index fe289ce..0000000
--- a/targets/tyan/s2882/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s2882
diff --git a/targets/tyan/s2882/ns2882 b/targets/tyan/s2882/ns2882
deleted file mode 100644
index 706fade..0000000
--- a/targets/tyan/s2882/ns2882
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/bash
-TYANMB=s2882
-cd "$TYANMB"
-make
-#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-#cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cp -f $TYANMB"_coreboot.rom" /home/yhlu/
diff --git a/targets/tyan/s2885/Config.lb b/targets/tyan/s2885/Config.lb
deleted file mode 100644
index 72877d2..0000000
--- a/targets/tyan/s2885/Config.lb
+++ /dev/null
@@ -1,63 +0,0 @@
-# Sample config file for 
-# the Tyan s2885 
-# This will make a target directory of ./s2885
-
-target s2885
-mainboard tyan/s2885
-
-# Tyan s2895
-romimage "normal"
-#       48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16200
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16200
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2885/VERSION b/targets/tyan/s2885/VERSION
deleted file mode 100644
index 90544df..0000000
--- a/targets/tyan/s2885/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s2885
diff --git a/targets/tyan/s2885/ns2885 b/targets/tyan/s2885/ns2885
deleted file mode 100644
index 056da1d..0000000
--- a/targets/tyan/s2885/ns2885
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/bash
-TYANMB=s2885
-cd "$TYANMB"
-make
-cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cp -f $TYANMB"_coreboot.rom" /home/yhlu/
diff --git a/targets/tyan/s2891/Config-abuild.lb b/targets/tyan/s2891/Config-abuild.lb
deleted file mode 100644
index 40620c0..0000000
--- a/targets/tyan/s2891/Config-abuild.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2891/Config-lab.lb b/targets/tyan/s2891/Config-lab.lb
deleted file mode 100644
index 8253b03..0000000
--- a/targets/tyan/s2891/Config-lab.lb
+++ /dev/null
@@ -1,23 +0,0 @@
-# Sample config file for 
-# the Tyan s2891 
-# This will make a target directory of ./s2891
-
-target s2891
-mainboard tyan/s2891
-
-option CONFIG_ROM_SIZE=0x100000
-# 36K for ATI ROM in 1M
-option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x9000)
-
-# Tyan s2891
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf.lzma
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/tyan/s2891/Config.lb b/targets/tyan/s2891/Config.lb
deleted file mode 100644
index cab355e..0000000
--- a/targets/tyan/s2891/Config.lb
+++ /dev/null
@@ -1,63 +0,0 @@
-# Sample config file for 
-# the Tyan s2891 
-# This will make a target directory of ./s2891
-
-target s2891
-mainboard tyan/s2891
-
-# Tyan s2891
-romimage "normal"
-#       36K for ATI ROM in 1M
-	option CONFIG_ROM_SIZE = 1024*1024-36*1024
-#       48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 36K for ATI ROM
-#       option CONFIG_ROM_SIZE = 512*1024-48*1024-36*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13000
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-        option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga_com2.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga_5_3.zelf
-#	payload ../../../payloads/tg3--filo_btext_hda2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-	payload ../payload.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13000
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-        option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga_com2.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga_5_3.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#	payload ../../../payloads/tg3--filo_btext_hda2.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2891/Config.lb.com2 b/targets/tyan/s2891/Config.lb.com2
deleted file mode 100644
index 24251e1..0000000
--- a/targets/tyan/s2891/Config.lb.com2
+++ /dev/null
@@ -1,57 +0,0 @@
-# Sample config file for 
-# the Tyan s2891 
-# This will make a target directory of ./s2891
-
-target s2891
-mainboard tyan/s2891
-
-# Tyan s2891
-romimage "normal"
-#       48K for SCSI FW or ATI ROM
-        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13000
-	option CONFIG_ROM_IMAGE_SIZE=0x15800
-        option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga.zelf
-	payload ../../../payloads/tg3--filo_hda2_vga_com2.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga_5_3.zelf
-#	payload ../../../payloads/tg3--filo_btext_hda2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13000
-	option CONFIG_ROM_IMAGE_SIZE=0x15800
-        option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga.zelf
-	payload ../../../payloads/tg3--filo_hda2_vga_com2.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga_5_3.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#	payload ../../../payloads/tg3--filo_btext_hda2.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2891/VERSION b/targets/tyan/s2891/VERSION
deleted file mode 100644
index 291e23c..0000000
--- a/targets/tyan/s2891/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s2891
diff --git a/targets/tyan/s2892/Config-abuild.lb b/targets/tyan/s2892/Config-abuild.lb
deleted file mode 100644
index 40620c0..0000000
--- a/targets/tyan/s2892/Config-abuild.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2892/Config-lab.lb b/targets/tyan/s2892/Config-lab.lb
deleted file mode 100644
index c9d8584..0000000
--- a/targets/tyan/s2892/Config-lab.lb
+++ /dev/null
@@ -1,26 +0,0 @@
-# Sample config file for 
-# the Tyan s2892 
-# This will make a target directory of ./s2892
-
-target s2892
-mainboard tyan/s2892
-
-# Leave Space for VGA BIOS
-option CONFIG_ROM_SIZE = 1024*1024-36*1024
-#option CONFIG_ROM_SIZE = 1024*1024
-option CONFIG_CONSOLE_SERIAL8250 = 1
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_XIP_ROM_SIZE = 0x20000
-option CONFIG_ROM_IMAGE_SIZE = 0x18000
-option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
-
-# Tyan s2892
-romimage "fallback" 
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf.lzma
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/tyan/s2892/Config.lb b/targets/tyan/s2892/Config.lb
deleted file mode 100644
index 82e4ca4..0000000
--- a/targets/tyan/s2892/Config.lb
+++ /dev/null
@@ -1,63 +0,0 @@
-# Sample config file for 
-# the Tyan s2892 
-# This will make a target directory of ./s2892
-
-target s2892
-mainboard tyan/s2892
-
-# Tyan s2892
-romimage "normal"
-#       36K for ATI ROM in 1M
-	option CONFIG_ROM_SIZE = 1024*1024-36*1024
-#       48K for SCSI FW or ATI ROM
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16380
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#        payload ../../../payloads/tg3--filo_hda2_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-	payload ../payload.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16380
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#        payload ../../../payloads/tg3--filo_hda2_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2892/VERSION b/targets/tyan/s2892/VERSION
deleted file mode 100644
index 91e6ccd..0000000
--- a/targets/tyan/s2892/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s2892
diff --git a/targets/tyan/s2895/Config-abuild.lb b/targets/tyan/s2895/Config-abuild.lb
deleted file mode 100644
index 1f26bbe..0000000
--- a/targets/tyan/s2895/Config-abuild.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2895/Config-lab.lb b/targets/tyan/s2895/Config-lab.lb
deleted file mode 100644
index e536892..0000000
--- a/targets/tyan/s2895/Config-lab.lb
+++ /dev/null
@@ -1,25 +0,0 @@
-# Sample config file for 
-# the Tyan s2895 
-# This will make a target directory of ./s2895
-
-target s2895
-mainboard tyan/s2895
-
-option CONFIG_CONSOLE_SERIAL8250 = 1
-option CONFIG_CONSOLE_VGA = 1
-option CONFIG_XIP_ROM_SIZE = 0x20000
-option CONFIG_ROM_IMAGE_SIZE = 0x18000
-option CONFIG_HAVE_FAILOVER_BOOT = 0
-option CONFIG_FAILOVER_SIZE = 0
-option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
-option CONFIG_COMPRESSED_PAYLOAD_LZMA = 1
-option CONFIG_PRECOMPRESSED_PAYLOAD = 1
-
-# Tyan s2895
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf.lzma
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/tyan/s2895/Config.lb b/targets/tyan/s2895/Config.lb
deleted file mode 100644
index 122716b..0000000
--- a/targets/tyan/s2895/Config.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-# Sample config file for 
-# the Tyan s2895 
-# This will make a target directory of ./s2895
-
-target s2895
-mainboard tyan/s2895
-
-# Tyan s2895
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s2895/VERSION b/targets/tyan/s2895/VERSION
deleted file mode 100644
index 0d641e6..0000000
--- a/targets/tyan/s2895/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s2895
diff --git a/targets/tyan/s2912/Config-abuild.lb b/targets/tyan/s2912/Config-abuild.lb
deleted file mode 100644
index 22e527e..0000000
--- a/targets/tyan/s2912/Config-abuild.lb
+++ /dev/null
@@ -1,34 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/tyan/s2912/Config.lb b/targets/tyan/s2912/Config.lb
deleted file mode 100644
index 3c7d62e..0000000
--- a/targets/tyan/s2912/Config.lb
+++ /dev/null
@@ -1,50 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Sample config file for s2912
-
-target s2912
-mainboard tyan/s2912
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback" 
-        option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#	payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
-	payload ../payload.elf
-end
-
-romimage "failover"
-        option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/tyan/s2912/Config.lb.kernel b/targets/tyan/s2912/Config.lb.kernel
deleted file mode 100644
index e09a558..0000000
--- a/targets/tyan/s2912/Config.lb.kernel
+++ /dev/null
@@ -1,77 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Sample config file for s2912
-
-target s2912
-mainboard tyan/s2912
-
-option CONFIG_ROM_SIZE=0x200000
-option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000)
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/memtest
-#	payload ../../../../payloads/adlo.elf
-#	payload ../../../../payloads/e1000_vga.zelf
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5.4.2.zelf
-	payload /home/yhlu/olpc-payload.elf.lzma
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/filo_hda2_novga.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" 
diff --git a/targets/tyan/s2912/VERSION b/targets/tyan/s2912/VERSION
deleted file mode 100644
index 202f8ca..0000000
--- a/targets/tyan/s2912/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s2912
diff --git a/targets/tyan/s2912_fam10/Config-abuild.lb b/targets/tyan/s2912_fam10/Config-abuild.lb
deleted file mode 100644
index 2ec827d..0000000
--- a/targets/tyan/s2912_fam10/Config-abuild.lb
+++ /dev/null
@@ -1,53 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target tyan_s2912_fam10
-mainboard tyan/s2912_fam10
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-Normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-Fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION=".0-Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/tyan/s2912_fam10/Config.lb b/targets/tyan/s2912_fam10/Config.lb
deleted file mode 100644
index 1ed0208..0000000
--- a/targets/tyan/s2912_fam10/Config.lb
+++ /dev/null
@@ -1,53 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Sample config file for s2912
-
-target s2912_fam10
-mainboard tyan/s2912_fam10
-
-# Make room for ATI ES1000 VGA ROM
-option CONFIG_ROM_SIZE=CONFIG_ROM_SIZE-44*1024
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	payload ../payload.elf
-end
-
-romimage "fallback" 
-        option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#	payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
-	payload ../payload.elf
-end
-
-romimage "failover"
-        option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/tyan/s2912_fam10/Config.lb.kernel b/targets/tyan/s2912_fam10/Config.lb.kernel
deleted file mode 100644
index e09a558..0000000
--- a/targets/tyan/s2912_fam10/Config.lb.kernel
+++ /dev/null
@@ -1,77 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Sample config file for s2912
-
-target s2912
-mainboard tyan/s2912
-
-option CONFIG_ROM_SIZE=0x200000
-option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000)
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/memtest
-#	payload ../../../../payloads/adlo.elf
-#	payload ../../../../payloads/e1000_vga.zelf
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga_5.4.2.zelf
-	payload /home/yhlu/olpc-payload.elf.lzma
-#	payload ../../../../payloads/filo_hda.zelf
-#	payload ../../../../payloads/filo_hda2_novga.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" 
diff --git a/targets/tyan/s4880/Config.lb b/targets/tyan/s4880/Config.lb
deleted file mode 100644
index 6b98702..0000000
--- a/targets/tyan/s4880/Config.lb
+++ /dev/null
@@ -1,53 +0,0 @@
-# Sample config file for 
-# the Tyan s4880
-# This will make a target directory of ./s4880
-
-target s4880
-mainboard tyan/s4880
-
-# Tyan s4880
-romimage "normal"
-#       48K for SCSI FW or ATI ROM
-        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x19000
-#	option CONFIG_ROM_IMAGE_SIZE=0x19c00
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-	payload ../../../../payloads/tg3_vga.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19000
-#	option CONFIG_ROM_IMAGE_SIZE=0x19c00
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-	payload ../../../../payloads/tg3_vga.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s4880/VERSION b/targets/tyan/s4880/VERSION
deleted file mode 100644
index 2ce1518..0000000
--- a/targets/tyan/s4880/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s4880
diff --git a/targets/tyan/s4880/ns4880 b/targets/tyan/s4880/ns4880
deleted file mode 100644
index c15330b..0000000
--- a/targets/tyan/s4880/ns4880
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/bash
-TYANMB=s4880
-cd "$TYANMB"
-make
-#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-#cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cp -f $TYANMB"_coreboot.rom" /home/yhlu/
diff --git a/targets/tyan/s4882/Config.lb b/targets/tyan/s4882/Config.lb
deleted file mode 100644
index cc44c1b..0000000
--- a/targets/tyan/s4882/Config.lb
+++ /dev/null
@@ -1,61 +0,0 @@
-# Sample config file for 
-# the Tyan s4882
-# This will make a target directory of ./s4882
-
-target s4882
-mainboard tyan/s4882
-
-# Tyan s4882
-romimage "normal"
-#       48K for SCSI FW or ATI ROM
-        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 512*1024-64*1024
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x19000
-#	option CONFIG_ROM_IMAGE_SIZE=0x19c00
-#	option CONFIG_ROM_IMAGE_SIZE=0x18800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16200
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-#	payload ../../../payloads/filo_vga_memtest.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19000
-#	option CONFIG_ROM_IMAGE_SIZE=0x19c00
-#	option CONFIG_ROM_IMAGE_SIZE=0x18800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16200
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-#	payload ../../../payloads/filo_vga_kernel.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/tyan/s4882/VERSION b/targets/tyan/s4882/VERSION
deleted file mode 100644
index d1a14e0..0000000
--- a/targets/tyan/s4882/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s4882
diff --git a/targets/tyan/s4882/ns4882 b/targets/tyan/s4882/ns4882
deleted file mode 100644
index 0092005..0000000
--- a/targets/tyan/s4882/ns4882
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/bash
-TYANMB=s4882
-cd "$TYANMB"
-make
-#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-#cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom"
-cp -f $TYANMB"_coreboot.rom" /home/yhlu/
diff --git a/targets/via/epia-cn/Config-abuild.lb b/targets/via/epia-cn/Config-abuild.lb
deleted file mode 100644
index 620685b..0000000
--- a/targets/via/epia-cn/Config-abuild.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=512*1024
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/via/epia-cn/Config.lb b/targets/via/epia-cn/Config.lb
deleted file mode 100644
index e7e9deb..0000000
--- a/targets/via/epia-cn/Config.lb
+++ /dev/null
@@ -1,43 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target via_epia_cn
-mainboard via/epia-cn
-
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-option CONFIG_CONSOLE_SERIAL8250=1
-
-# coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x00004000
-
-#
-# Generate the final ROM like this:
-# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
-#
-option CONFIG_ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024)
-
-romimage "fallback"
-	option COREBOOT_EXTRA_VERSION = "-epiacn"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/via/epia-m/Config-abuild.lb b/targets/via/epia-m/Config-abuild.lb
deleted file mode 100644
index 0f6d5da..0000000
--- a/targets/via/epia-m/Config-abuild.lb
+++ /dev/null
@@ -1,25 +0,0 @@
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=256*1024
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-Normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-Fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia-m/Config.512kflash.lb b/targets/via/epia-m/Config.512kflash.lb
deleted file mode 100644
index 0cf7e1c..0000000
--- a/targets/via/epia-m/Config.512kflash.lb
+++ /dev/null
@@ -1,55 +0,0 @@
-# Sample config file for EPIA-M
-# This will make a target directory of ./epia-m.512kflash
-
-target epia-m.512kflash
-
-mainboard via/epia-m
-
-option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-option  CONFIG_CONSOLE_SERIAL8250=1
-
-option CONFIG_ROM_SIZE=512*1024
-
-
-option CONFIG_HAVE_OPTION_TABLE=1
-option CONFIG_ROM_PAYLOAD=1
-option CONFIG_HAVE_FALLBACK_BOOT=1
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-option CONFIG_FALLBACK_SIZE=131072
-
-## Coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x00004000
-
-#
-###
-### Compute the start location and size size of
-### The coreboot bootloader.
-###
-
-#
-# Via EPIA M
-#
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-	payload ../../../../../lnxieepro100.ebi
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-	payload ../../../../../lnxieepro100.ebi
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia-m/Config.etherboot.lb b/targets/via/epia-m/Config.etherboot.lb
deleted file mode 100644
index 0ceaf17..0000000
--- a/targets/via/epia-m/Config.etherboot.lb
+++ /dev/null
@@ -1,54 +0,0 @@
-# Sample config file for EPIA-M
-# This will make a target directory of ./epia-m
-
-target epia-m
-
-mainboard via/epia-m
-
-option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-option  CONFIG_CONSOLE_SERIAL8250=1
-
-option CONFIG_ROM_SIZE=256*1024
-
-option CONFIG_HAVE_OPTION_TABLE=1
-option CONFIG_ROM_PAYLOAD=1
-option CONFIG_HAVE_FALLBACK_BOOT=1
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-option CONFIG_FALLBACK_SIZE=131072
-
-## Coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x00004000
-
-#
-###
-### Compute the start location and size size of
-### The coreboot bootloader.
-###
-
-#
-# Via EPIA-M
-#
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-	payload ../../../../../lnxieepro100.ebi
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-	payload ../../../../../lnxieepro100.ebi
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia-m/Config.filo.lb b/targets/via/epia-m/Config.filo.lb
deleted file mode 100644
index 02313ff..0000000
--- a/targets/via/epia-m/Config.filo.lb
+++ /dev/null
@@ -1,56 +0,0 @@
-# Sample config file for EPIA-M
-# This will make a target directory of ./epia-m
-
-target epia-m
-
-mainboard via/epia-m
-
-option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-option  CONFIG_CONSOLE_SERIAL8250=1
-
-option CONFIG_ROM_SIZE=256*1024
-
-option CONFIG_HAVE_OPTION_TABLE=1
-option CONFIG_ROM_PAYLOAD=1
-option CONFIG_HAVE_FALLBACK_BOOT=1
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-option CONFIG_FALLBACK_SIZE=131072
-
-## Coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x00004000
-
-#
-###
-### Compute the start location and size size of
-### The coreboot bootloader.
-###
-
-#
-# EPIA-M
-#
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-	payload ../../../../../../filo.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-	payload ../../../../../../filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia-m/Config.lb b/targets/via/epia-m/Config.lb
deleted file mode 100644
index 2f9d6e1..0000000
--- a/targets/via/epia-m/Config.lb
+++ /dev/null
@@ -1,48 +0,0 @@
-# abuild config file for EPIA-M
-
-target via_epia-m
-mainboard via/epia-m
-
-option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-option  CONFIG_CONSOLE_SERIAL8250=1
-
-option CONFIG_ROM_SIZE=256*1024
-
-
-option CONFIG_HAVE_OPTION_TABLE=1
-option CONFIG_ROM_PAYLOAD=1
-option CONFIG_HAVE_FALLBACK_BOOT=1
-#option CONFIG_COMPRESSED_PAYLOAD_NRV2B=1
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-option CONFIG_FALLBACK_SIZE=131072
-
-## Coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x00004000
-
-#
-# Via EPIA M
-#
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#option CONFIG_ROM_IMAGE_SIZE=128*1024
-	option CONFIG_ROM_IMAGE_SIZE=64*1024
-	option COREBOOT_EXTRA_VERSION=".0-Normal"
-	payload $(HOME)/svn/payload.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	#option CONFIG_ROM_IMAGE_SIZE=128*1024
-	option CONFIG_ROM_IMAGE_SIZE=60*1024
-	option COREBOOT_EXTRA_VERSION=".0-Fallback"
-	payload $(HOME)/svn/payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia-m/Config.vga.filo b/targets/via/epia-m/Config.vga.filo
deleted file mode 100644
index 86b4fb2..0000000
--- a/targets/via/epia-m/Config.vga.filo
+++ /dev/null
@@ -1,50 +0,0 @@
-# Sample config file for EPIA-M
-# This will make a target directory of ./epia-m
-
-target epia-m
-
-mainboard via/epia-m
-
-option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-option  CONFIG_CONSOLE_SERIAL8250=1
-
-option CONFIG_ROM_SIZE=256*1024
-option CONFIG_HAVE_OPTION_TABLE=1
-option CONFIG_ROM_PAYLOAD=1
-option CONFIG_HAVE_FALLBACK_BOOT=1
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-option CONFIG_FALLBACK_SIZE=0x18000
-
-## Coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x00004000
-
-###
-### Compute the start location and size size of
-### The coreboot bootloader.
-###
-
-#
-# EPIA-M
-#
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0xc000
-	option CONFIG_ROM_SECTION_OFFSET=0x10000
-	option CONFIG_ROM_SECTION_SIZE=0x18000
-	option COREBOOT_EXTRA_VERSION=".0-Normal"
-	payload $(HOME)/svn/filo.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0xc000
-	option COREBOOT_EXTRA_VERSION=".0-Fallback"
-	payload $(HOME)/svn/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia-m700/Config-abuild.lb b/targets/via/epia-m700/Config-abuild.lb
deleted file mode 100644
index f0497be..0000000
--- a/targets/via/epia-m700/Config-abuild.lb
+++ /dev/null
@@ -1,36 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "fallback"
-	option COREBOOT_EXTRA_VERSION = "-epia-m700"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/via/epia-m700/Config.lb b/targets/via/epia-m700/Config.lb
deleted file mode 100644
index 6d012cb..0000000
--- a/targets/via/epia-m700/Config.lb
+++ /dev/null
@@ -1,29 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target epia-m700
-mainboard via/epia-m700
-
-romimage "fallback"
-	option COREBOOT_EXTRA_VERSION = "-epia-m700"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/via/epia-n/Config-abuild.lb b/targets/via/epia-n/Config-abuild.lb
deleted file mode 100644
index 620685b..0000000
--- a/targets/via/epia-n/Config-abuild.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=512*1024
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/via/epia-n/Config.lb b/targets/via/epia-n/Config.lb
deleted file mode 100644
index d1b3060..0000000
--- a/targets/via/epia-n/Config.lb
+++ /dev/null
@@ -1,43 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target via_epia_n
-mainboard via/epia-n
-
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=10
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=10
-option CONFIG_CONSOLE_SERIAL8250=1
-
-# coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x00004000
-
-#
-# Generate the final ROM like this:
-# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
-#
-#option CONFIG_ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024)
-
-romimage "fallback"
-	option COREBOOT_EXTRA_VERSION = "-epia_n-fallback"
-	payload ../../../../../payloads/filo/build/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_FALLBACK_SIZE "fallback"
diff --git a/targets/via/epia/Config.512kflash.lb b/targets/via/epia/Config.512kflash.lb
deleted file mode 100644
index c904b41..0000000
--- a/targets/via/epia/Config.512kflash.lb
+++ /dev/null
@@ -1,29 +0,0 @@
-# Sample config file for EPIA
-# This will make a target directory of ./epia.512kflash
-
-target epia.512kflash
-mainboard via/epia
-
-option CONFIG_ROM_SIZE=512*1024
-
-#
-# Via Epia
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-	payload ../../../../../lnxieepro100.ebi
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-	payload ../../../../../lnxieepro100.ebi
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia/Config.512kflash.linuxtiny.lb b/targets/via/epia/Config.512kflash.linuxtiny.lb
deleted file mode 100644
index b6b184b..0000000
--- a/targets/via/epia/Config.512kflash.linuxtiny.lb
+++ /dev/null
@@ -1,21 +0,0 @@
-# Sample config file for EPIA
-# This will make a target directory of ./epia.512kflash
-
-target epia.512kflash.linuxtiny
-mainboard via/epia
-
-option CONFIG_ROM_SIZE=512*1024
-option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=64*1024
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-	payload /tmp/linux.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE  "fallback"
diff --git a/targets/via/epia/Config.filo.lb b/targets/via/epia/Config.filo.lb
deleted file mode 100644
index 5107037..0000000
--- a/targets/via/epia/Config.filo.lb
+++ /dev/null
@@ -1,29 +0,0 @@
-# Sample config file for EPIA
-# This will make a target directory of ./epia
-
-target epia
-mainboard via/epia
-
-#
-# Via Epia
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-	payload /tmp/filo.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia/Config.ituner.filo.lb b/targets/via/epia/Config.ituner.filo.lb
deleted file mode 100644
index ddfec5e..0000000
--- a/targets/via/epia/Config.ituner.filo.lb
+++ /dev/null
@@ -1,31 +0,0 @@
-# Sample config file for EPIA
-# This will make a target directory of ./epia
-
-target epia-ituner-filo
-mainboard via/epia
-
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-#
-# Via Epia
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-	payload /tmp/filo.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-	payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia/Config.lb b/targets/via/epia/Config.lb
deleted file mode 100644
index 72440e1..0000000
--- a/targets/via/epia/Config.lb
+++ /dev/null
@@ -1,35 +0,0 @@
-# Sample config file for EPIA
-# This will make a target directory of ./epia
-
-## uncomment these three lines if you have a Nehemiah CPU to boot 1s faster
-#option CONFIG_UDELAY_IO=0
-#option CONFIG_UDELAY_TSC=1
-#option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-target epia
-mainboard via/epia
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-#
-# Via Epia
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Normal"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-	payload /etc/hosts
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
-#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-#	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-	payload /etc/hosts
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/pc2500e/Config-abuild.lb b/targets/via/pc2500e/Config-abuild.lb
deleted file mode 100644
index d0c75cd..0000000
--- a/targets/via/pc2500e/Config-abuild.lb
+++ /dev/null
@@ -1,40 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC = "CROSSCC"
-option CONFIG_CROSS_COMPILE = "CROSS_PREFIX"
-option HOSTCC = "CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE = 512 * 1024
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-	option COREBOOT_EXTRA_VERSION = ".0Fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/via/pc2500e/Config.lb b/targets/via/pc2500e/Config.lb
deleted file mode 100644
index 35afeb4..0000000
--- a/targets/via/pc2500e/Config.lb
+++ /dev/null
@@ -1,29 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-target via_pc2500e
-mainboard via/pc2500e
-
-romimage "fallback"
-	option COREBOOT_EXTRA_VERSION = "-pc2500e"
-	payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/via/vt8454c/Config-abuild.lb b/targets/via/vt8454c/Config-abuild.lb
deleted file mode 100644
index f4f35c5..0000000
--- a/targets/via/vt8454c/Config-abuild.lb
+++ /dev/null
@@ -1,43 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-
-# This will make a target directory of ./VENDOR_MAINBOARD
-# build a single image coreboot. Only Fallback, no normal.
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-option CONFIG_ROM_SIZE=512*1024
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" 
-#pci_rom $(TOP)/via-cx700.rom vendor_id=0x1106 device_id=0x3157
diff --git a/targets/via/vt8454c/Config.lb b/targets/via/vt8454c/Config.lb
deleted file mode 100644
index cb42703..0000000
--- a/targets/via/vt8454c/Config.lb
+++ /dev/null
@@ -1,43 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Config file for VIA VT8454c mainboard
-#
-
-target via_vt8454c
-mainboard via/vt8454c
-
-option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
-option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
-
-option CONFIG_ROM_SIZE=(512-64)*1024
-
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload $(HOME)/payload.elf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload $(HOME)/payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/util/abuild/abuild b/util/abuild/abuild
index 525740d..be6ecfa 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -34,8 +34,6 @@ cpus=1
 
 # Configure-only mode
 configureonly=0
-# use old config method "newconfig"
-oldconfig=0
 
 # One might want to adjust these in case of cross compiling
 for i in make gmake gnumake nonexistant_make; do
@@ -122,117 +120,9 @@ function architecture
 {
 	VENDOR=$1
 	MAINBOARD=$2
-	if [ $oldconfig -eq 1 ]; then
-		ARCH=`cat $ROOT/src/mainboard/$VENDOR/$MAINBOARD/Config.lb | \
-			grep ^arch | cut -f 2 -d\ `
-		echo $ARCH | sed s/ppc/powerpc/
-	else
-		ARCH=`cat $ROOT/src/mainboard/$VENDOR/$MAINBOARD/Kconfig | \
-		        grep "select ARCH_"|cut -f2- -d_`
-		echo $ARCH | sed s/X86/i386/
-	fi
-}
-
-function create_config_old
-{
-	VENDOR=$1
-	MAINBOARD=$2
-	CONFIG=$3
-	TARCH=$( architecture $VENDOR $MAINBOARD )
-	TARGCONFIG=$ROOT/targets/$VENDOR/$MAINBOARD/Config-abuild.lb
-
-	if [ "$CONFIG" != "" ]; then
-		TARGCONFIG=$ROOT/targets/$VENDOR/$MAINBOARD/$CONFIG
-	fi
-
-        # get a working payload for the board if we have one.
-        # the --payload option expects a directory containing 
-	# a shell script payload.sh
-	#   Usage: payload.sh [VENDOR] [DEVICE]
-	# the script returns an absolute path to the payload binary.
-
-	if [ -f $payloads/payload.sh ]; then
-		PAYLOAD=`sh $payloads/payload.sh $VENDOR $MAINBOARD`
-		printf "Using payload $PAYLOAD\n"
-	fi
-	
-	mkdir -p $TARGET
-
-        if [ -f $TARGCONFIG ]; then
-        	cp $TARGCONFIG $TARGET/Config-${VENDOR}_${MAINBOARD}.lb
-		printf "Using existing test target $TARGCONFIG"
-		xml "  <config>$TARGCONFIG</config>"
-	else
-		printf "  Creating config file..."
-		xml "  <config>autogenerated</config>"
-		( cat << EOF
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-EOF
-		if [ "$TARCH" == i386 ] ; then
-			cat <<EOF
-romimage "normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-EOF
-		else
-			cat <<EOF
-romimage "only"
-	option COREBOOT_EXTRA_VERSION=".0"
-	payload __PAYLOAD__
-end
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "only"
-EOF
-		fi 
-		) > $TARGET/Config-${VENDOR}_${MAINBOARD}.lb
-	fi
-
-	if [ "$loglevel" != "default" ]; then
-		LOGLEVEL1="option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$loglevel"
-		LOGLEVEL2="option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$loglevel"
-	else
-		LOGLEVEL1="# no loglevel override"
-		LOGLEVEL2=""
-	fi
-
-	COMPRESSION="# no compression"
-	if which lzma >/dev/null 2>/dev/null; then
-		if [ "$PAYLOAD" != /dev/null ]; then
-			COMPRESSION="option CONFIG_COMPRESSED_PAYLOAD_LZMA=1"
-		fi
-	fi
-
-	cp $TARGET/Config-${VENDOR}_${MAINBOARD}.lb $TARGET/Config-${VENDOR}_${MAINBOARD}.lb.pre
-	sed -e s:VENDOR:$VENDOR:g \
-		-e s:MAINBOARD:$MAINBOARD:g \
-		-e s:payload\ __PAYLOAD__:payload\ $PAYLOAD:g \
-		-e s:CROSSCC:"$CC":g \
-		-e s:CROSS_PREFIX:"$CROSS_COMPILE":g \
-		-e s:CROSS_HOSTCC:"$HOSTCC":g \
-		-e s:__COMPRESSION__:"$COMPRESSION":g \
-		-e s:__LOGLEVEL__:"$LOGLEVEL1"\
-"$LOGLEVEL2":g \
-		$TARGET/Config-${VENDOR}_${MAINBOARD}.lb.pre > $TARGET/Config-${VENDOR}_${MAINBOARD}.lb
-	printf " ok\n"
+	ARCH=`cat $ROOT/src/mainboard/$VENDOR/$MAINBOARD/Kconfig | \
+		grep "select ARCH_"|cut -f2- -d_`
+	echo $ARCH | sed s/X86/i386/
 }
 
 function create_config
@@ -308,66 +198,12 @@ function create_config
 	fi
 }
 
-function create_builddir
-{	
-	VENDOR=$1
-	MAINBOARD=$2
-	
-	printf "  Creating builddir..."
-
-	target_dir=$TARGET
-	config_dir=$ROOT/util/newconfig
-	yapps2_py=$config_dir/yapps2.py
-	config_g=$config_dir/config.g
-	config_lb=Config-${VENDOR}_${MAINBOARD}.lb
-
-	cd $target_dir
-
-	build_dir=${VENDOR}_${MAINBOARD}
-	config_py=$build_dir/config.py
-
-	if [ ! -d $build_dir ] ; then
-		mkdir -p $build_dir
-	fi
-	if [ ! -f $config_py ]; then
-		$PYTHON $yapps2_py $config_g $config_py &> $build_dir/py.log
-	fi
-
-	# make sure config.py is up-to-date
-
-	export PYTHONPATH=$config_dir
-	$PYTHON $config_py $config_lb $ROOT &> $build_dir/config.log
-	if [ $? -eq 0 ]; then
-		printf "ok\n"
-		xml "  <builddir>ok</builddir>"
-		xml "  <log>"
-		xmlfile $build_dir/config.log
-		xml "  </log>"
-		xml ""
-		return 0
-	else
-		printf "FAILED! Log excerpt:\n"
-		xml "  <builddir>failed</builddir>"
-		xml "  <log>"
-		xmlfile $build_dir/config.log
-		xml "  </log>"
-		xml ""
-		tail -n $CONTEXT $build_dir/config.log 2> /dev/null || tail -$CONTEXT $build_dir/config.log
-		return 1
-	fi
-}
-
 function create_buildenv
 {
 	VENDOR=$1
 	MAINBOARD=$2
 	CONFIG=$3
-	if [ $oldconfig -eq 1 ]; then
-		create_config_old $VENDOR $MAINBOARD $CONFIG
-		create_builddir $VENDOR $MAINBOARD
-	else
-		create_config $VENDOR $MAINBOARD $CONFIG
-	fi
+	create_config $VENDOR $MAINBOARD $CONFIG
 }
 
 function compile_target
@@ -382,20 +218,14 @@ function compile_target
 
 	CURR=$( pwd )
 	stime=`perl -e 'print time();'`
-	if [ $oldconfig -eq 1 ]; then
-		cd $TARGET/${VENDOR}_${MAINBOARD}
-		eval $MAKE $silent -j $cpus &> make.log
-		ret=$?
-	else
-		build_dir=$TARGET/${VENDOR}_${MAINBOARD}
-		eval $MAKE $silent -j $cpus obj=${build_dir} \
-			&> ${build_dir}/make.log
-		ret=$?
-		mv .config ${build_dir}/config.build
-		mv .xcompile ${build_dir}/xcompile.build
-		mv ..config.tmp ${build_dir}/config.deps
-		cd $TARGET/${VENDOR}_${MAINBOARD}
-	fi
+	build_dir=$TARGET/${VENDOR}_${MAINBOARD}
+	eval $MAKE $silent -j $cpus obj=${build_dir} \
+		&> ${build_dir}/make.log
+	ret=$?
+	mv .config ${build_dir}/config.build
+	mv .xcompile ${build_dir}/xcompile.build
+	mv ..config.tmp ${build_dir}/config.deps
+	cd $TARGET/${VENDOR}_${MAINBOARD}
 	etime=`perl -e 'print time();'`
 	duration=$(( $etime - $stime ))
 	if [ $ret -eq 0 ]; then
@@ -692,15 +522,15 @@ target=""
 buildall=false
 verbose=false
 
-test -f util/newconfig/config.g && ROOT=$( pwd )
-test -f ../util/newconfig/config.g && ROOT=$( cd ..; pwd )
+test -f util/sconfig/config.g && ROOT=$( pwd )
+test -f ../util/sconfig/config.g && ROOT=$( cd ..; pwd )
 test "$ROOT" = "" && ROOT=$( cd ../..; pwd )
 
 # parse parameters.. try to find out whether we're running GNU getopt
 getoptbrand="`getopt -V`"
 if [ "${getoptbrand:0:6}" == "getopt" ]; then
 	# Detected GNU getopt that supports long options.
-	args=`getopt -l version,verbose,help,all,target:,broken,payloads:,test,cpus:,silent,xml,config,loglevel:,oldconfig Vvhat:bp:Tc:sxCl:o -- "$@"`
+	args=`getopt -l version,verbose,help,all,target:,broken,payloads:,test,cpus:,silent,xml,config,loglevel: Vvhat:bp:Tc:sxCl: -- "$@"`
 	eval set "$args"
 else
 	# Detected non-GNU getopt
@@ -731,7 +561,6 @@ while true ; do
 		-sb|--scan-build) shift; scanbuild=true;;
 		-C|--config)    shift; configureonly=1;;
 		-l|--loglevel)  shift; loglevel="$1"; shift;;
-		-o|--oldconfig) shift; oldconfig=1;;
 		--)		shift; break;;
 		-*)		printf "Invalid option\n\n"; myhelp; exit 1;;
 		*)		break;;
diff --git a/util/analysis/Makefile b/util/analysis/Makefile
deleted file mode 100644
index 91b1186..0000000
--- a/util/analysis/Makefile
+++ /dev/null
@@ -1,135 +0,0 @@
-#  Coreboot codebase analysis tool
-#
-#  This makefile collects source usage information for all working targets.
-#
-#  Written 7/2006 by Josiah England <josiah@lanl.gov>
-#
-#  This file is subject to the terms and conditions of the GNU General
-#  Public License. See the file COPYING in the main directory of this
-#  archive for more details.
-
-TOP := $(shell cd ../.. && pwd)
-BUILD_BASE := $(TOP)/targets
-
-IGNORE_ERRORS := 2>/dev/null # Comment out this line for some ugly verbosity
-IGNORE_VENDORS := emulation momentum embeddedplanet motorola totalimpact
-IGNORE_C := static.c# romcc.c
-
-quote = "#"
-
-VENDORS := $(shell ls -l $(TOP)/targets | grep ^d | grep -Eo [[:alnum:]_-]+$$$(foreach ignored, $(IGNORE_VENDORS), | grep -v $(ignored)))
-#<VENDOR>_BOARDS assignments
-$(foreach VENDOR, $(VENDORS), $(eval $(VENDOR)_BOARDS := $(shell ls $(TOP)/targets/$(VENDOR))))
-TARGETS := $(foreach VENDOR, $(VENDORS), $(addprefix $(VENDOR)/, $($(VENDOR)_BOARDS)))
-
-# The following delayed-evalutate variables are only to be used in rule commands.
-CONFIG_MAINBOARD = $(TOP)/src/mainboard/$(shell grep ^mainboard $(dir $*)/Config.lb|grep -Eo [-[:alnum:]_/]+[[:space:]]?$$)
-IMAGE_DIR = $(firstword $(shell grep -Eo ^romimage[[:space:]]+\"[[:alnum:]_-/]+ $(dir $*)/Config.lb|sed -r s/romimage[[:space:]]+\"//))
-
-# Evaluate one assignment to variable "$1" from file "$2"
-load_var = $(eval $(shell grep -E ^[[:space:]]*$1[[:space:]]*:*= $2 $(IGNORE_ERRORS)))
-
-.PHONY: clean analysis
-
-analysis: analysis.dat
-	gnuplot -persist '$<'
-
-# Generate gnuplot data file
-analysis.dat: analysis.txt
-	@ echo Writing gnuplot data file \($@\).
-	@ echo -e > $@ "# gnuplot dataset auto-generated $(shell date)" \
-	"\nset title \"Coreboot Codebase Analysis\"" \
-	"\nset style data boxes" \
-	"\nset style fill solid .5" \
-	$(foreach target, $(TARGETS), "\n"set label \"$(target)\" at $(words $(labels))$(eval labels += $(target)),-145 rotate front) \
-	"\nplot [-.5:] '-' t 'Source:' , '-' t 'Nested C:' , '-' t 'Headers:' , '-' t 'romcc Sources:' , '-' t 'romcc Headers:'"
-	@ grep -F "C files" $< | grep -Eo [[:digit:]]+ >> $@
-	@ echo e >> $@
-	@ grep -F "Nested C" $< | grep -Eo [[:digit:]]+ >> $@
-	@ echo e >> $@
-	@ grep -F "Headers" $< | grep -Eo [[:digit:]]+ | sed -r s/\([[:digit:]]+\)/'-'\\1/>> $@
-	@ echo e >> $@
-	@ grep -F "romcc C" $< | grep -Eo [[:digit:]]+ >> $@
-	@ echo e >> $@
-	@ grep -F "romcc H" $< | grep -Eo [[:digit:]]+ | sed -r s/\([[:digit:]]+\)/'-'\\1/>> $@
-	@ echo e >> $@
-
-analysis.txt: $(foreach target, $(TARGETS), $(BUILD_BASE)/$(target)/$(shell grep ^target $(BUILD_BASE)/$(target)/Config.lb | grep -Eo [[:alnum:]_-]+[[:space:]]?$$)/analysis/info)
-	@ echo -e "\n\n"Compiling individual target analysis info into $@.
-	cat $? | tee -a $@
-
-# Prevent automatic deletion of intermediate files
-.SECONDARY: $(prepend $(foreach target, $(TARGETS), $(BUILD_BASE)/$(target)/$(shell grep ^target $(BUILD_BASE)/$(target)/Config.lb | grep -Eo [[:alnum:]_-]+$$)), /analysis, /analysis/c_files, /analysis/h_files, /analysis/info, /Makefile)
-
-# FIXME: This rule is necessary even if the Makefile already exists.
-%/Makefile:
-	@ echo \*\*\* Building target: $(notdir $*) \*\*\*
-	-@ cd $(TOP)/targets && ./buildtarget $(dir $*) 1>>build.log 2>>builderrors.log
-	@ echo -e >> $*/$(IMAGE_DIR)/Makefile "depend:\n\t"'@ makedepend -v -f- -- $$(CPPFLAGS) -- $$(SOURCES)'
-
-%/analysis/c_files: %/Makefile
-	@ echo Analysis directory is $*/analysis
-	-@ mkdir $*/analysis $(IGNORE_ERRORS)
-	@ echo -n Finding C source files...
-	@ grep -Eo \\$$+[\(][A-Z_]+[\)][/-_[:alnum:]]+'\.c\>' $*/$(IMAGE_DIR)/Makefile | grep -v $(IGNORE_C) | sort -u > $@
-	@ echo " "Done.
-
-# Grep for .c files #included within others (only one level deep).
-# sed commands provide full pathname for included .c files, assuming two things:
-# 1. If include statement has no directory component, the file is in same dir.
-# 2. If included file has a directory component, it's base is from $(TOP)/src/.
-%/analysis/nested_c_files: %/analysis/c_files
-	@ echo -n Finding nested .c includes...
-	$(eval c_files := $(shell cat $<))
-	@ grep -Eo '\#'include[[:space:]\"]+[/-_[:alnum:]]+'\.c' $(c_files) | sed s/\#include[[:space:]]// > $@.tmp
-	@ sed -r s/\([/-_[:alnum:]]+\\/\)\([-_[:alnum:]]+'.c'\):\"\([-_[:alnum:]]+'.c'$$\)/\\1\\2:' '\\1\\3/ $@.tmp | \
-	sed -r s/\([/-_[:alnum:]]+\\/\)\([-_[:alnum:]]+'.c'\):\"\([/-_[:alnum:]]+'.c'$$\)/\\1\\2:' '\$$\(TOP\)\\/src\\/\\3/ > $@
-	@ rm $@.tmp
-	@ echo " "Done.
-
-%/analysis/h_files: %/analysis/c_files %/analysis/nested_c_files
-	@ echo -n Finding all included headers...
-	$(call load_var,TARGET_DIR, $*/Makefile.settings)
-	@ $(MAKE) -C $(TARGET_DIR)/$(IMAGE_DIR) depend $(IGNORE_ERRORS) | grep -v makedepend | grep -Eo [/-_[:alnum:]]+'\.h' | sort -u > $@ && \
-	$(MAKE) -C $(TARGET_DIR)/$(IMAGE_DIR) "SOURCES := $(shell grep [/-_[:alnum:]]+'.c' $(word 2, $?))" depend $(IGNORE_ERRORS) | grep -v makedepend | grep -Eo [/-_[:alnum:]]+'\.h' | sort -u >> $@
-	@ echo " "Done.
-
-#%/auto.inc:
-
-# Determine which sources use romcc by their inclusion in auto.inc #FIXME better
-%/analysis/romcc_files: %/analysis/c_files %/analysis/nested_c_files
-	$(call load_var,TARGET_DIR, $*/Makefile.settings)
-	@ $(if $(findstring cache_as_ram, $(shell cat $<)), \
-		echo none, \
-		echo -n \* Uses romcc - making auto.inc... && \
-		$(MAKE) -iC $(TARGET_DIR)/$(IMAGE_DIR) auto.inc $(IGNORE_ERRORS) 1>/dev/null && \
-		echo " "to find sources that use romcc. && \
-		grep -Eo [/-_[:alnum:]]+'\.c' $(TARGET_DIR)/$(IMAGE_DIR)/auto.inc | sort -u) \
-	> $@
-
-# Full pathnames of found files are gathered from  nested_c_files and c_files.
-%/analysis/romcc_sources: %/analysis/c_files %/analysis/nested_c_files %/analysis/romcc_files
-	@ echo -e $(foreach file, $(shell cat $(dir $@)/romcc_files), "\n"'$(firstword $(shell grep -Eho [/-_\$$\(\)[:alnum:]]+/'$(file)' $(dir $@)/nested_c_files $(dir $@)/c_files))') >$@
-
-%/analysis/romcc_headers: %/analysis/romcc_sources
-	@ echo -n Finding headers used by any romcc source...
-	$(eval romcc_sources = $(shell cat $(dir $@)/romcc_sources))
-	$(call load_var,TARGET_DIR, $*/Makefile.settings)
-	@ $(MAKE) -C $(TARGET_DIR)/$(IMAGE_DIR) "SOURCES := $(romcc_sources)" depend $(IGNORE_ERRORS) | grep -v makedepend | grep -Eo [/-_[:alnum:]]+'\.'h | sort -u > $@
-	@ echo " "Done.
-
-$(BUILD_BASE)/%/analysis/info: $(BUILD_BASE)/%/analysis/h_files $(BUILD_BASE)/%/analysis/romcc_headers
-	@ echo -e Target: $(subst /, , $(dir $*)) \
-	"\n"Uses $(if $(findstring cache_as_ram, $(shell grep -F '.c' $(dir $@)/c_files)),CAR,romcc) \
-	"\n"C files: $(shell grep -Eo [-_[:alnum:]]+'\.c' $(dir $@)/c_files $(dir $@)/nested_c_files $(dir $@)/romcc_sources | sort -u | grep -Fc '.c') \
-	"\n"Nested C: $(shell grep -Eo [-_[:alnum:]]+'\.c' $(dir $@)/nested_c_files | sort -u | grep -Fc '.c') \
-	"\n"Headers: $(shell grep -Eo [-_[:alnum:]]+'\.h' $(dir $@)/h_files $(dir $@)/romcc_headers | sort -u | grep -Fc '.h') \
-	"\n"romcc C: $(shell grep -Ec [-_[:alnum:]]+'\.c' $(dir $@)/romcc_sources) \
-	"\n"romcc H: $(shell grep -Ec [-_[:alnum:]]+'\.h' $(dir $@)/romcc_headers) \
-	"\n">> $@
-
-clean-builds:
-	rm -rf $(foreach target, $(TARGETS), $(BUILD_BASE)/$(target)/$(shell grep ^target $(BUILD_BASE)/$(target)/Config.lb | grep -Eo [[:alnum:]_-]+[[:space:]]?$$))
-
-clean:
-	rm -rf $(foreach target, $(TARGETS), $(BUILD_BASE)/$(target)/$(shell grep ^target $(BUILD_BASE)/$(target)/Config.lb | grep -Eo [[:alnum:]_-]+[[:space:]]?$$)/analysis) analysis.txt analysis.dat
diff --git a/util/compareboard/compareboard b/util/compareboard/compareboard
deleted file mode 100755
index 10b4682..0000000
--- a/util/compareboard/compareboard
+++ /dev/null
@@ -1,137 +0,0 @@
-#!/bin/bash
-# $1 board name
-
-normalize() {
-# $1 filename
-cat $1 | while read line; do
-	if echo $line | grep '= 0x' > /dev/null; then
-		first=`echo $line | cut -d= -f1`
-		last=`echo $line |cut -d= -f2 |cut -d\; -f1`
-		echo $first = $(($last + 0))\;
-	else
-		echo $line
-	fi
-done
-}
-
-BOARDPATH=`echo $1 | sed s,/,_,g`
-
-A=`mktemp tmp.XXXXXXXXXX`
-rm -rf $A
-mkdir -p $A
-
-sort coreboot-builds/$BOARDPATH/fallback/ldoptions > $A/old
-sort build/ldoptions > $A/new
-
-if [ `grep -c "^CONFIG_NORTHBRIDGE_AMD_AMDFAM10" $A/new` -eq 0 ]; then
-	sed \
-		-e "/^CONFIG_AMDMCT / d" \
-		-e "/^CONFIG_C[BD]B / d" \
-		-e "/^CONFIG_EXT_CONF_SUPPORT / d" \
-		-e "/^CONFIG_EXT_RT_TBL_SUPPORT / d" \
-		-e "/^CONFIG_HT3_SUPPORT / d" \
-		$A/old > $A/old.tmp && mv $A/old.tmp $A/old
-fi
-
-if [ `grep -c "^CONFIG_NORTHBRIDGE_AMD_AMDK8" $A/new` -eq 0 ]; then
-	sed \
-		-e "/^CONFIG_K8_HT_FREQ_1G_SUPPORT / d" \
-		$A/old > $A/old.tmp && mv $A/old.tmp $A/old
-fi
-
-if [ `grep -c "^CONFIG_NORTHBRIDGE_AMD_AMDFAM10" $A/new` -eq 0 -a `grep -c "^CONFIG_NORTHBRIDGE_AMD_AMDK8" $A/new` -eq 0 ]; then
-	sed \
-		-e "/^CONFIG_APIC_ID_OFFSET / d" \
-		-e "/^CONFIG_CPU_SOCKET_TYPE / d" \
-		-e "/^CONFIG_DIMM_SUPPORT / d" \
-		-e "/^CONFIG_HT_CHAIN_UNITID_BASE / d" \
-		-e "/^CONFIG_HT_CHAIN_END_UNITID_BASE / d" \
-		-e "/^CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC / d" \
-		-e "/^CONFIG_HW_MEM_HOLE_SIZEK / d" \
-		-e "/^CONFIG_MEM_TRAIN_SEQ / d" \
-		-e "/^CONFIG_SB_HT_CHAIN_ON_BUS0 / d" \
-		-e "/^CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY / d" \
-		$A/old > $A/old.tmp && mv $A/old.tmp $A/old
-fi
-
-sed \
-	-e "/^CONFIG_CONSOLE_/ d" \
-	-e "/^CONFIG_MAXIMUM_CONSOLE_LOGLEVEL/ d" \
-	-e "/^CONFIG_DEFAULT_CONSOLE_LOGLEVEL/ d" \
-	-e "/^CONFIG_RESET_/ d" \
-	-e "/^CONFIG_XIP_ROM_/ d" \
-	-e "/^CONFIG_PRECOMPRESSED_PAYLOAD / d" \
-	-e "/^CONFIG_K8_MEM_BANK_B_ONLY / d" \
-	-e "/^CONFIG_MULTIBOOT / d" \
-	-e "/^CONFIG_ARCH_POWERPC / d" \
-	-e "/^CONFIG_RESET / d" \
-	-e "/^CONFIG_ROM_PAYLOAD / d" \
-	-e "/^CONFIG_ROM_SECTION_/ d" \
-	-e "/^CONFIG_UNCOMPRESSED / d" \
-	-e "/^CONFIG_COMPRESS / d" \
-	-e "/^CONFIG_COMPRESSED_PAYLOAD_LZMA / d" \
-	-e "/^CONFIG_ASSEMBLER_DEBUG / d" \
-	-e "/^CONFIG_HAVE_FAILOVER_BOOT / d" \
-	-e "/^CONFIG_FAILOVER_SIZE / d" \
-	-e "/^CONFIG_FALLBACK_SIZE / d" \
-	-e "/^CONFIG_ROMBASE / d" \
-	-e "/^CONFIG_ROM_IMAGE_SIZE / d" \
-	-e "/^CONFIG_STACK_SIZE / d" \
-	-e "/^CONFIG_GDB_STUB / d" \
-	-e "/^CONFIG_VIDEO_MB / d" \
-	-e "/^CONFIG_HAVE_MOVNTI / d" \
-	-e "/^CONFIG_PCIE_CONFIGSPACE_HOLE / d" \
-	$A/old > $A/old.filtered
-sed \
-	-e "/^CONFIG_VENDOR_/ d" \
-	-e "/^CONFIG_ARCH_POWERPC / d" \
-	-e "/^CONFIG_MAXIMUM_CONSOLE_LOGLEVEL/ d" \
-	-e "/^CONFIG_DEFAULT_CONSOLE_LOGLEVEL/ d" \
-	-e "/^CONFIG_COREBOOT_ROMSIZE_/ d" \
-	-e "/^CONFIG_BOARD_/ d" \
-	-e "/^CONFIG_HAVE_MOVNTI / d" \
-	-e "/^CONFIG_[NORTHSOUTH]*BRIDGE_/ d" \
-	-e "/^CONFIG_SUPERIO_/ d" \
-	-e "/^CONFIG_GX1_VIDEOMODE_/ d" \
-	-e "/^CONFIG_CONSOLE_/ d" \
-	-e "/^CONFIG_PAYLOAD_/ d" \
-	-e "/^CONFIG_XIP_ROM_/ d" \
-	-e "/^CONFIG_MULTIBOOT/ d" \
-	-e "/^CONFIG_HAVE_FAILOVER_BOOT / d" \
-	-e "/^CONFIG_COMPRESSED_PAYLOAD_LZMA / d" \
-	-e "/^CONFIG_CPU_[A-Z]*_MODEL_/ d" \
-	-e "/^CONFIG_CPU_[A-Z]*_SOCKET_/ d" \
-	-e "/^CONFIG_CPU_AMD_/ d" \
-	-e "/^CONFIG_CPU_INTEL_/ d" \
-	-e "/^CONFIG_CPU_VIA_/ d" \
-	-e "/^CONFIG_ROMBASE / d" \
-	-e "/^CONFIG_ROM_IMAGE_SIZE / d" \
-	-e "/^CONFIG_STACK_SIZE / d" \
-	-e "/^CONFIG_GDB_STUB / d" \
-	-e "/^CONFIG_VIDEO_MB / d" \
-	-e "/^CONFIG_EXPERT / d" \
-	-e "/^CONFIG_SSE / d" \
-	-e "/^CONFIG_MMX / d" \
-	-e "/^CONFIG_VGA_BIOS / d" \
-	-e "/^CONFIG_WARNINGS_ARE_ERRORS / d" \
-	-e "/^CONFIG_TINY_BOOTBLOCK / d" \
-	-e "/^CONFIG_BIG_BOOTBLOCK / d" \
-	-e "/^CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT / d" \
-	-e "/^CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT / d" \
-	$A/new > $A/new.filtered
-
-normalize $A/old.filtered > $A/old.normalized
-normalize $A/new.filtered > $A/new.normalized
-
-diff -u $A/old.normalized $A/new.normalized | \
-    grep ^[+-][^+-] | \
-    sed -e "s,^+,p ," -e "s,^-,m ," | \
-    sort -k2,2 -k1,1 | \
-    sed -e "s,^p ,+," -e "s,^m ,-," | \
-    while read line; do
-	key=`echo $line|cut -f1 -d\=`
-	value=`echo $line|cut -f2 -d\= | tr -d \\;`
-	printf "%s = 0x%x\n" "$key" $value
-    done
-
-rm -rf $A
diff --git a/util/kbuildall/kbuildall b/util/kbuildall/kbuildall
deleted file mode 100755
index 062b590..0000000
--- a/util/kbuildall/kbuildall
+++ /dev/null
@@ -1,68 +0,0 @@
-#!/bin/sh
-#
-#  coreboot autobuilder for kconfig
-#
-#  This script builds coreboot images for all available targets.
-#
-#  (C) 2009 coresystems GmbH 
-#      written by Patrick Georgi <patrick.georgi@coresystems.de>
-#
-#  This file is subject to the terms and conditions of the GNU General
-#  Public License, version 2. See the file COPYING in the main directory
-#  of this archive for more details.
-
-TARGETDIR=kbuildall.results
-BOARD=$1
-
-if [ ! -f util/kbuildall/kbuildall ]; then
-	echo "This application must be run from the"
-	echo "toplevel directory of a coreboot checkout."
-	exit 1
-fi
-
-for make in make gmake gnumake; do
-	if [ "`$make --version 2>/dev/null | grep -c GNU`" -gt 0 ]; then
-		MAKE=$make
-		break
-	fi
-done
-
-builddefconfig() {
-# $1: mainboarddir
-	$MAKE distclean
-	grep "depends[\t ]on[\t ]*VENDOR" src/mainboard/$1/../Kconfig | sed "s,^.*\(VENDOR_.*\)[^A-Z0-9_]*,CONFIG_\1=y," > .config
-	grep "config[\t ]*BOARD" src/mainboard/$1/Kconfig | sed "s,^.*\(BOARD_.*\)[^A-Z0-9_]*,CONFIG_\1=y," >> .config
-	grep "select[\t ]*ARCH" src/mainboard/$1/Kconfig | sed "s,^.*\(ARCH_.*\)[^A-Z0-9_]*,CONFIG_\1=y," >> .config
-	echo "CONFIG_MAINBOARD_DIR=$1" >> .config
-	yes "" | $MAKE oldconfig
-}
-
-ALLTARGETS=`(cd src/mainboard; ls */*/Config.lb | sed s,/Config.lb,,)`
-TARGETCOUNT=`echo $ALLTARGETS | wc -w`
-
-if [ -n "$BOARD" ]; then
-	TARGETCOUNT=1
-	ALLTARGETS=$BOARD
-else
-	rm -rf $TARGETDIR
-fi
-mkdir -p $TARGETDIR
-i=0
-for dir in $ALLTARGETS; do
-	i=`expr $i + 1`
-	if [ ! -f src/mainboard/$dir/Kconfig ]; then
-		echo "[$i/$TARGETCOUNT] ($dir) no Kconfig"
-		echo "$dir nokconfig" >> $TARGETDIR/_overview.txt
-		continue
-	fi
-	name=`echo $dir | sed s,/,_,g`
-	printf "[$i/$TARGETCOUNT] $dir "
-	builddefconfig $dir > $TARGETDIR/$name.buildconfig.log 2>&1
-	result=`$MAKE > $TARGETDIR/$name.buildcoreboot.log 2>&1 && echo ok || echo fail`
-	echo "$result."
-	if [ "$result" = "ok" ]; then
-		util/abuild/abuild -o -C -t $dir
-		sh util/compareboard/compareboard $dir | tee $TARGETDIR/$name.variables.txt
-	fi
-	echo "$dir $result" >> $TARGETDIR/_overview.txt
-done
diff --git a/util/newconfig/LICENSE b/util/newconfig/LICENSE
deleted file mode 100644
index 64f38b8..0000000
--- a/util/newconfig/LICENSE
+++ /dev/null
@@ -1,18 +0,0 @@
-Permission is hereby granted, free of charge, to any person obtaining 
-a copy of this software and associated documentation files (the 
-"Software"), to deal in the Software without restriction, including 
-without limitation the rights to use, copy, modify, merge, publish, 
-distribute, sublicense, and/or sell copies of the Software, and to 
-permit persons to whom the Software is furnished to do so, subject to 
-the following conditions: 
-  
-The above copyright notice and this permission notice shall be included 
-in all copies or substantial portions of the Software. 
-  
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
-IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
-CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 
diff --git a/util/newconfig/Makefile b/util/newconfig/Makefile
deleted file mode 100644
index 3328380..0000000
--- a/util/newconfig/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
-ALL: $(shell echo *.g | sed s/\\.g/\\.py/g )
-
-%.py: %.g yapps2.py yappsrt.py Makefile
-	python yapps2.py $<
-
-DOC:	yapps2.ps yapps2.pdf manual/index.html
-
-yapps2.ps: yapps2.dvi
-	dvips -q yapps2.dvi -o yapps2.ps
-
-yapps2.pdf: yapps2.ps
-	ps2pdf yapps2.ps
-
-yapps2.dvi: yapps2.tex
-	latex yapps2.tex
-
-manual/index.html: yapps2.aux yapps2.tex
-	rm manual/yapps2.css
-	latex2html -dir 'manual' -mkdir -lcase_tags -font_size 12pt -split 4 -toc_depth 4 -html_version 4.0,unicode,table -t 'Yapps 2.0 Manual' -address 'Amit J Patel, amitp@cs.stanford.edu' -info 0 -show_section_numbers -up_title 'Yapps Page' -up_url 'http://theory.stanford.edu/~amitp/yapps/' -strict -image_type png yapps2.tex
-	echo '@import url("http://www-cs-students.stanford.edu/~amitp/amitp.css");' > manual/yapps2-new.css
-	echo 'hr { display:none; }' >> manual/yapps2-new.css
-	echo 'h1 br, h2 br { display:none; }' >>manual/yapps2-new.css
-	cat manual/yapps2.css >> manual/yapps2-new.css
-	rm manual/yapps2.css
-	mv manual/yapps2-new.css manual/yapps2.css
-
-DISTRIB:
-	cd ..; zip -u yapps2.zip yapps2/{LICENSE,yapps2.py,yappsrt.py,parsedesc.g,examples/*.g,NOTES,yapps2.tex,Makefile,manual/*.html,manual/*.css,manual/*.png}
-
-clean:
-	rm -f config.py yappsrt.pyc parsedesc.py
diff --git a/util/newconfig/NOTES b/util/newconfig/NOTES
deleted file mode 100644
index 325e76a..0000000
--- a/util/newconfig/NOTES
+++ /dev/null
@@ -1,46 +0,0 @@
-April 14, 2002:
-
-I haven't worked on Yapps for a while, mainly because I spent all my energy
-on trying to graduate.  Now that I've finished school, I have several projects
-I want to start working on again, including Yapps.
-
-Notes for myself:
-
-Add a debugging mode that helps you understand how the grammar
-  is constructed and how things are being parsed
-Look into an English output mode that would use natural language
-  to describe a grammar
-Optimize unused variables
-Add a convenience to automatically gather up the values returned 
-  from subpatterns, put them into a list, and return them
-Improve the documentation
-Write some larger examples
-Get rid of old-style regex support
-Use SRE's lex support to speed up lexing (this may be hard given that
-  yapps allows for context-sensitive lexers)
-Look over Dan Connoly's experience with Yapps (bugs, frustrations, etc.)
-  and see what improvements could be made
-Add something to pretty-print the grammar (without the actions)
-Maybe conditionals?  Follow this rule only if <condition> holds.
-  But this would be useful mainly when multiple rules match, and we
-  want the first matching rule.  The conditional would mean we skip to
-  the next rule.  Maybe this is part of the attribute grammar system,
-  where rule X<0> can be specified separately from X<N>.
-Convenience functions that could build return values for all rules
-  without specifying the code for each rule individually
-Patterns (abstractions over rules) -- for example, comma separated values
-  have a certain rule pattern that gets replicated all over the place
-"Gather" mode that simply outputs the return values for certain nodes.
-  For example, if you just want all expressions, you could ask yapps
-  to gather the results of the 'expr' rule into a list.  This would 
-  ignore all the higher level structure.
-Look at everyone's Yapps grammars, and come up with larger examples
-  http://www.w3.org/2000/10/swap/SemEnglish.g
-  http://www.w3.org/2000/10/swap/kifExpr.g
-  http://www.w3.org/2000/10/swap/rdfn3.g
-It would be nice if you could feed text into Yapps (push model) instead
-  of Yapps reading text out of a string (pull model).  However, I think
-  that would make the resulting parser code mostly unreadable 
-  (like yacc, etc.).  Coroutines/stacklesspython may be the answer.
-
-
diff --git a/util/newconfig/config.g b/util/newconfig/config.g
deleted file mode 100644
index fbe33bf..0000000
--- a/util/newconfig/config.g
+++ /dev/null
@@ -1,2580 +0,0 @@
-# -*- python -*-
-import sys
-import os
-import re
-import string
-import types
-
-import traceback
-
-warnings = 0
-errors = 0
-
-target_dir = ''
-target_name = ''
-treetop = ''
-full_mainboard_path = ''
-mainboard_path = ''
-global_options = {}
-global_options_by_order = []
-global_option_values = {}
-global_uses_options = {}
-global_exported_options = []
-romimages = {}
-buildroms = []
-pciroms = []
-rommapping = {}
-curimage = 0
-bootblocksize = 0
-alloptions = 0 # override uses at top level
-
-local_path = re.compile(r'^\.')
-include_pattern = re.compile(r'%%([^%]+)%%')
-
-# the cpu type for this mainboard
-cpu_type = 0
-
-# -----------------------------------------------------------------------------
-#                    Utility Classes
-# -----------------------------------------------------------------------------
-
-class stack:
-	"""Used to keep track of the current part or dir"""
-	class __stack_iter:
-		def __init__ (self, stack):
-			self.index = 0
-			self.len = len(stack)
-			self.stack = stack
-
-		def __iter__ (self):
-			return self
-
-		def next (self):
-			if (self.index < self.len):
-				s = self.stack[self.index]
-				self.index = self.index + 1
-				return s
-			raise StopIteration
-
-	def __init__ (self):
-		self.stack = []
-
-	def __len__ (self):
-		return len(self.stack)
-
-	def __getitem__ (self, i):
-		return self.stack[i]
-
-	def __iter__ (self):
-		return self.__stack_iter(self.stack)
-
-	def push(self, part):
-		self.stack.append(part)
-
-	def pop(self):
-		try:
-			return self.stack.pop()
-		except IndexError:
-			return 0
-
-	def tos(self):
-		try:
-			return self.stack[-1]
-		except IndexError:
-			return 0
-
-	def empty(self):
-		return (len(self.stack) == 0)
-partstack = stack()
-dirstack = stack()
-
-class debug_info:
-	none = 0
-	gencode = 1
-	dumptree = 2
-	object = 3
-	dict = 4
-	statement = 5
-	dump = 6
-	gengraph = 7
-
-	def __init__(self, *level):
-		self.__level = level
-
-	def setdebug(self, *level):
-		self.__level = level
-
-	def level(self, level):
-		return level in self.__level
-
-	def info(self, level, str):
-		if level in self.__level:
-			print str
-
-global debug
-debug = debug_info(debug_info.dumptree)
-debug = debug_info(debug_info.object)
-
-# -----------------------------------------------------------------------------
-#                    Error Handling
-# -----------------------------------------------------------------------------
-
-class location:
-	"""Used to keep track of our current location while parsing
-	configuration files"""
-	class __place:
-                def __init__(self, file, line, command):
-                        self.file = file
-                        self.line = line
-                        self.command = command
-                def next_line(self, command):
-                        self.line = self.line + 1
-                        self.command = command
-                def at(self):
-                        return "%s:%d" % (self.file, self.line)
-        
-        def __init__ (self):
-                self.stack = stack()
-
-	def __str__ (self):
-		s = ''
-		for p in self.stack:
-			if (s == ''):
-				s = p.at()
-			else:
-				s = s + '\n' + p.at()
-		return s
-
-        def file(self):
-                return self.stack.tos().file
-
-        def line(self):
-                return self.stack.tos().line
-
-        def command(self):
-                return self.stack.tos().command
-
-        def push(self, file):
-                self.stack.push(self.__place(os.path.normpath(file), 0, ""))
-
-        def pop(self):
-                self.stack.pop()
-
-        def next_line(self, command):
-                self.stack.tos().next_line(command)
-
-        def at(self):
-                return self.stack.tos().at()
-loc = location()
-
-def error(string):      
-	"""Print error message"""
-        global errors, loc
-	errors = errors + 1
-        print "===> ERROR: %s" % string
-        print "%s" % loc
-
-def fatal(string):      
-	"""Print error message and exit"""
-	error(string)
-        exitiferrors()
-
-def warning(string):
-	"""Print warning message"""
-        global warnings, loc
-	warnings = warnings + 1
-        print "===> WARNING: %s" % string
-
-def notice(string):
-	"""Print notice message"""
-	#print "===> NOTE: %s" % string
-
-def exitiferrors():
-	"""Exit parser if an error has been encountered"""
-	if (errors != 0):
-		sys.exit(1)
-
-def safe_open(file, mode):
-	try:
-		return open(file, mode)
-	except IOError:
-		fatal("Could not open file \"%s\"" % file)
-
-# -----------------------------------------------------------------------------
-#                    Main classes
-# -----------------------------------------------------------------------------
-
-class romimage:
-	"""A rom image is the ultimate goal of coreboot"""
-	def __init__ (self, name):
-		# name of this rom image
-		self.name = name
-
-		# set by 'arch' directive
-		self.arch = ''
-
-		# set by 'payload' directive
-		self.payload = ''
-
-		# set by 'init' directive
-		self.initfile = ''
-
-		# make rules added by 'makerule' directive
-		self.makebaserules = {}
-
-		# object files added by 'object' directive
-		self.objectrules = {}
-
-		# init object files added by 'initobject' directive
-		self.initobjectrules = {}
-
-		# driver files added by 'driver' directive
-		self.driverrules = {}
-
-		# smm object files added by 'smmobject' directive
-		self.smmobjectrules = {}
-
-		# loader scripts added by 'ldscript' directive
-		self.ldscripts = []
-
-		# user defines added by 'makedefine' directive
-		self.userdefines = []
-
-		# files to be included in crt0.S
-		self.initincludes = {}
-
-		# as above, but order is preserved
-		self.initincludesorder = []
-
-		# transitional flag to support old crtinclude format
-		self.useinitincludes = 0
-
-		# instance counter for parts
-		self.partinstance = 0
-
-		# chip config files included by the 'config' directive
-		self.configincludes = {}
-
-		# root of part tree
-		self.root = 0
-
-		# name of target directory specified by 'target' directive
-		self.target_dir = ''
-
-		# option values used in rom image
-		self.values = {}
-
-		# exported options
-		self.exported_options = []
-
-		# Last device built
-		self.last_device = 0
-
-	def getname(self):
-		return self.name
-
-	def getvalues(self):
-		return self.values
-
-	def setarch(self, arch):
-		self.arch = arch
-
-	def setpayload(self, payload):
-		global rommapping
-		self.payload = payload
-
-		rommapping[self.name] = payload
-
-	def setinitfile(self, initfile):
-		self.initfile = initfile
-
-	def getinitfile(self):
-		return self.initfile
-
-	def addmakerule(self, id):
-		o = getdict(self.makebaserules, id)
-		if (o):
-			warning("rule %s previously defined" % id)
-		o = makerule(id)
-		setdict(self.makebaserules, id, o)
-
-	def getmakerules(self):
-		return self.makebaserules
-
-	def getmakerule(self, id):
-		o = getdict(self.makebaserules, id)
-		if (o):
-			return o
-		fatal("No such make rule \"%s\"" % id)
-
-	def addmakeaction(self, id, str):
-		o = getdict(self.makebaserules, id)
-		if (o):
-			a = dequote(str)
-			o.addaction(a)
-			return
-		fatal("No such rule \"%s\" for addmakeaction" % id)
-
-	def addmakedepend(self, id, str):
-		o = getdict(self.makebaserules, id)
-		if (o):
-			a = dequote(str)
-			o.adddependency(a)
-			return
-		fatal("No such rule \"%s\" for addmakedepend" % id)
-
-	def addmakeobject(self, file, obj):
-		source = topify(obj[1])
-		type = obj[2]
-		if (type  == 'S'):
-			# for .S, .o depends on .s
-			file.write("%s: %s.s\n" % (obj[0], obj[3]))
-        		file.write("\t$(CC) -c $(CONFIG_CPU_OPT) -o $@ $<\n")
-			# and .s depends on .S
-			file.write("%s.s: %s\n" % (obj[3], source))
-			# Note: next 2 lines are ONE output line!
-        		file.write("\t$(CPP) $(CPPFLAGS) $< ")
-			file.write(">$@.new && mv $@.new $@\n")
-		else:
-			file.write("%s: %s\n" % (obj[0], source))
-			file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
-
-	# this is called with an an object name. 
-	# the easiest thing to do is add this object to the current 
-	# component.
-	# such kludgery. If the name starts with '.' then make the 
-	# dependency be on ./thing.x gag me.
-	def addobjectdriver(self, dict, object_name):
-		global dirstack
-		suffix = object_name[-2:]
-		if (suffix == '.o'):
-			suffix = '.c'
-		base = object_name[:-2]
-		type = object_name[-1:]
-		if (object_name[0] == '.'):
-			source = base + suffix
-			object = base + '.o'
-			rel_base = base
-		else:
-			rel_base = re.sub(treetop, "", os.path.join(dirstack.tos(), base))
-			source = "$(TOP)" + rel_base + suffix
-			if (rel_base[0] == '/'):
-				rel_base = re.sub("^/", "", rel_base)
-			object = rel_base + '.o'
-
-		debug.info(debug.object, "add object %s source %s" % (object, source))
-		l = getdict(dict, rel_base)
-		if (l):
-			warning("object/driver %s previously defined" % rel_base)
-		setdict(dict, rel_base, [object, source, type, rel_base])
-
-	def addinitobjectrule(self, name):
-		self.addobjectdriver(self.initobjectrules, name)
-
-	def addobjectrule(self, name):
-		self.addobjectdriver(self.objectrules, name)
-
-	def adddriverrule(self, name):
-		self.addobjectdriver(self.driverrules, name)
-
-	def addsmmobjectrule(self, name):
-		self.addobjectdriver(self.smmobjectrules, name)
-
-	def getinitobjectrules(self):
-		return self.initobjectrules
-
-	def getinitobjectrule(self, name):
-		o = getdict(self.initobjectrules, name)
-		if (o):
-			return o
-		fatal("No such init object rule \"%s\"" % name)
-
-	def getobjectrules(self):
-		return self.objectrules
-
-	def getobjectrule(self, name):
-		o = getdict(self.objectrules, name)
-		if (o):
-			return o
-		fatal("No such object rule \"%s\"" % name)
-
-	def getdriverrules(self):
-		return self.driverrules
-
-	def getdriverrule(self, name):
-		o = getdict(self.driverrules, name)
-		if (o):
-			return o
-		fatal("No such driver rule \"%s\"" % name)
-
-	def getsmmobjectrules(self):
-		return self.smmobjectrules
-
-	def getsmmobjectrule(self, name):
-		o = getdict(self.smmobjectrules, name)
-		if (o):
-			return o
-		fatal("No such smm object rule \"%s\"" % name)
-
-	def addldscript(self, path):
-		self.ldscripts.append(path)
-
-	def getldscripts(self):
-		return self.ldscripts
-
-	def adduserdefine(self, str):
-		self.userdefines.append(str)
-
-	def getuserdefines(self):
-		return self.userdefines
-
-	def addinitinclude(self, str, path):
-		if (str != 0):
-			self.useinitincludes = 1
-
-		debug.info(debug.object, "ADDCRT0: %s -> %s" % (str, path))
-		o = getdict(self.initincludes, path)
-		if (o):
-			warning("init include for %s previously defined" % path)
-		o = initinclude(str, path)
-		setdict(self.initincludes, path, o)
-		self.initincludesorder.append(path)
-
-	def getinitincludes(self):
-		return self.initincludesorder
-
-	def getinitinclude(self, path):
-		o = getdict(self.initincludes, path)
-		if (o):
-			return o
-		fatal("No such init include \"%s\"" % path)
-
-	def addconfiginclude(self, part, path):
-		setdict(self.configincludes, part, path)
-
-	def getconfigincludes(self):
-		return self.configincludes
-
-	def getincludefilename(self):
-		if (self.useinitincludes):
-			return "crt0.S"
-		else:
-			return "crt0_includes.h"
-	
-	def newformat(self):
-		return self.useinitincludes
-
-	def numparts(self):
-		return self.partinstance
-
-	def newpartinstance(self):
-		i = self.partinstance
-		self.partinstance = self.partinstance + 1
-		return i
-
-	def setroot(self, part):
-		self.root = part
-
-	def getroot(self):
-		return self.root
-
-	def settargetdir(self, path):
-		self.targetdir = path
-
-	def gettargetdir(self):
-		return self.targetdir
-
-class buildrom:
-	"""A buildrom statement"""
-	def __init__ (self, filename, size, roms):
-		self.name = filename
-		self.size = size
-		self.roms = roms
-	
-	def __len__ (self):
-		return len(self.roms)
-
-	def __getitem__(self,i):
-		return self.roms[i]
-
-class pci_rom:
-	"""A pci_rom statement"""
-	def __init__ (self, filename, vendor, device):
-		self.name = filename
-		self.pci_vid = vendor
-		self.pci_did = device
-	
-class initinclude:
-	"""include file for initialization code"""
-	def __init__ (self, str, path):
-		self.string = str
-		self.path = path
-
-	def getstring(self):
-		return self.string
-
-	def getpath(self):
-		return self.path
-
-class makerule:
-	"""Rule to be included in Makefile"""
-	def __init__ (self, target):
-		self.target = target
-		self.dependency = []
-		self.actions = []
-
-	def addaction(self, action):
-		self.actions.append(action)
-
-	def adddependency(self, dependency):
-		self.dependency.append(dependency)
-
-	def gtarget(self):
-		return self.target
-
-	def gdependency(self):
-		return self.dependency
-
-	def gaction(self):
-		return self.actions
-
-class option:
-	"""Configuration option"""
-	def __init__ (self, name):
-		self.name = name	# name of option
-		self.loc = 0		# current location
-		self.used = 0		# option has been used
-					# it is undefined)
-		self.comment = ''	# description of option
-		self.exportable = 0	# option is able to be exported
-		self.format = '%s'	# option print format
-		self.write = []		# parts that can set this option
-
-	def where(self):
-		return self.loc
-
-	def setcomment(self, comment, loc):
-		if (self.comment != ''):
-			print "%s: " % self.name
-			print "Attempt to modify comment at %s" % loc 
-			return
-		self.comment = comment
-
-	def setexportable(self):
-		self.exportable = 1
-
-	def setnoexport(self):
-		self.exportable = 0
-
-	def setformat(self, fmt):
-		self.format = fmt
-
-	def getformat(self):
-		return self.format
-
-	def setused(self):
-		if (self.exportable):
-			self.exported = 1
-		self.used = 1
-
-	def setwrite(self, part):
-		self.write.append(part)
-
-	def isexportable(self):
-		return self.exportable
-
-	def iswritable(self, part):
-		return (part in self.write)
-
-class option_value:
-	"""Value of a configuration option. The option has a default
-        value which can be changed at any time. Once an option has been
-	set the default value is no longer used."""
-	def __init__(self, name, prev):
-		self.name = name
-		self.value = ''
-		self.set = 0
-		if (prev):
-			self.value   = prev.value
-			self.set     = prev.set
-		
-
-	def setvalue(self, value):
-		if ((self.set & 2) == 2):
-			warning("Changing option %s" % self.name)
-		else:
-			self.set |= 2
-		self.value = value
-
-	def setdefault(self, value):
-		if ((self.set & 1) == 1):
-			notice("Changing default value of %s" % self.name)
-		
-		if ((self.set & 2) == 0):
-			self.value = value
-			self.set |= 1
-
-	def contents(self):
-		return self.value
-
-	def isset(self):
-		return (self.set & 2) == 2
-
-
-class partobj:
-	"""A configuration part"""
-	def __init__ (self, image, dir, parent, part, type_name, instance_name, chip_or_device):
-		if (parent):
-			debug.info(debug.object, "partobj dir %s parent %s part %s" \
-				% (dir, parent.instance_name, part))
-		else:
-			debug.info(debug.object, "partobj dir %s part %s" \
-				% (dir, part))
-
-		# romimage that is configuring this part
-		self.image = image
-
-		# links for static device tree
-		self.children = 0
-		self.prev_sibling = 0
-		self.next_sibling = 0
-		self.prev_device = 0
-		self.next_device = 0
-		self.chip_or_device = chip_or_device
-
-		# list of init code files
-		self.initcode = []
-
-		# initializers for static device tree
-		self.registercode = {}
-
-		# part name
-		self.part = part
-
-		# type name of this part
-		self.type_name = type_name
-
-		# object files needed to build this part
-		self.objects = []
-
-		# directory containg part files
-		self.dir = dir
-
-		# instance number, used to distinguish anonymous
-		# instances of this part
-		self.instance = image.newpartinstance()
-		debug.info(debug.object, "INSTANCE %d" % self.instance)
-
-		# Options used by this part
-		self.uses_options = {}
-
-		# Name of chip config file (0 if not needed)
-		self.chipconfig = 0
-
-		# Flag to indicate that we have generated type
-		# definitions for this part (only want to do it once)
-		self.done_types = 0
-
-		# Path to the device
-		self.path = ""
-
-		# Resources of the device
-		self.resoruce = ""
-		self.resources = 0
-
-		# Enabled state of the device
-		self.enabled = 1
-
-		# Flag if I am a dumplicate device
-		self.dup = 0
-
-		# If no instance name is supplied then generate
-		# a unique name
-		if (instance_name == 0):
-			self.instance_name = self.type_name + \
-					"_dev%d" % self.instance
-			self.chipinfo_name = "%s_info_%d" \
-					% (self.type_name, self.instance)
-		else:
-			self.instance_name = instance_name
-			self.chipinfo_name = "%s_info_%d" % (self.instance_name, self.instance)
-
-		# Link this part into the device list
-		if (self.chip_or_device == 'device'):
-			if (image.last_device):
-				image.last_device.next_device = self
-			self.prev_device = image.last_device
-			image.last_device = self
-
-		# Link this part into the tree
-		if (parent and (part != 'arch')):
-			debug.info(debug.gencode, "add to parent")
-			self.parent   = parent
-			# add current child as my sibling, 
-			# me as the child.
-			if (parent.children):
-				debug.info(debug.gencode, "add %s (%d) as sibling" % (parent.children.dir, parent.children.instance))
-				youngest = parent.children
-				while(youngest.next_sibling):
-					youngest = youngest.next_sibling
-				youngest.next_sibling = self
-				self.prev_sibling = youngest
-			else:
-				parent.children = self
-		else:
-			self.parent = self
-
-
-	def info(self):
-		return "%s: %s" % (self.part, self.type)
-	def type(self):
-		return self.chip_or_device
-
-	def readable_name(self):
-		name = ""
-		name = "%s_%d" % (self.type_name, self.instance)
-		if (self.chip_or_device == 'chip'):
-			name = "%s %s %s" % (name, self.part, self.dir)
-		else:
-			name = "%s %s" % (name, self.path)
-		return name
-
-	def graph_name(self):
-		name = "{ {_dev%d|" % self.instance
-		if (self.part):
-			name = "%s%s" % (name, self.part)
-		else:
-			name = "%s%s" % (name, self.chip_or_device)
-		if (self.type_name):
-			name = "%s}|%s}" % (name, self.type_name)
-		else:
-			name = "%s}|%s}" % (name, self.parent.type_name)
-		return name
-			
-	def dumpme(self, lvl):
-		"""Dump information about this part for debugging"""
-		print "%d: %s" % (lvl, self.readable_name())
-		print "%d: part %s" % (lvl, self.part)
-		print "%d: instance %d" % (lvl, self.instance)
-		print "%d: chip_or_device %s"  %  (lvl, self.chip_or_device)
-		print "%d: dir %s" % (lvl,self.dir)
-		print "%d: type_name %s" % (lvl,self.type_name)
-		print "%d: parent: %s" % (lvl, self.parent.readable_name())
-		if (self.children):
-			print "%d: child %s" % (lvl, self.children.readable_name())
-		if (self.next_sibling):
-			print "%d: siblings %s" % (lvl, self.next_sibling.readable_name())
-		print "%d: initcode " % lvl
-		for i in self.initcode:
-			print "\t%s" % i
-		print "%d: registercode " % lvl
-		for f, v in self.registercode.items():
-			print "\t%s = %s" % (f, v)
-		print "\n"
-
-	def firstchilddevice(self):
-		"""Find the first device in the children link."""
-		kid = self.children
-		while (kid):
-			if (kid.chip_or_device == 'device'):
-				return kid
-			else:
-				kid = kid.children
-		return 0
-
-	def firstparentdevice(self):
-		"""Find the first device in the parent link."""
-		parent = self.parent
-		while (parent and (parent.parent != parent) and (parent.chip_or_device != 'device')):
-			parent = parent.parent
-		if ((parent.parent != parent) and (parent.chip_or_device != 'device')):
-			parent = 0
-		while(parent and (parent.dup == 1)):
-			parent = parent.prev_sibling
-		if (not parent):
-			fatal("Device %s has no device parent; this is a config file error" % self.readable_name())
-		return parent
-
-	def firstparentdevicelink(self):
-		"""Find the first device in the parent link and record which link it is."""
-		link = 0
-		parent = self.parent
-		while (parent and (parent.parent != parent) and (parent.chip_or_device != 'device')):
-			parent = parent.parent
-		if ((parent.parent != parent) and (parent.chip_or_device != 'device')):
-			parent = 0
-		while(parent and (parent.dup == 1)):
-			parent = parent.prev_sibling
-			link = link + 1
-		if (not parent):
-			fatal("Device %s has no device parent; this is a config file error" % self.readable_name())
-		return link
-
-
-	def firstparentchip(self):
-		"""Find the first chip in the parent link."""
-		parent = self.parent
-		while (parent):
-			if ((parent.parent == parent) or (parent.chip_or_device == 'chip')):
-				return parent
-			else:
-				parent = parent.parent
-		fatal("Device %s has no chip parent; this is a config file error" % self.readable_name())
-
-	def firstsiblingdevice(self):
-		"""Find the first device in the sibling link."""
-		sibling = self.next_sibling
-		while(sibling and (sibling.path == self.path)):
-			sibling = sibling.next_sibling
-		if ((not sibling) and (self.parent.chip_or_device == 'chip')):
-			sibling = self.parent.next_sibling
-		while(sibling):
-			if (sibling.chip_or_device == 'device'):
-				return sibling
-			else:
-				sibling = sibling.children
-		return 0
-
-	def gencode(self, file, pass_num):
-		"""Generate static initalizer code for this part. Two passes
-		are used - the first generates type information, and the second
-		generates instance information"""
-		if (pass_num == 0):
-			if (self.chip_or_device == 'chip'):
-				return;
-			else:
-				if (self.instance):
-					file.write("struct device %s;\n" \
-						% self.instance_name)
-				else:
-					file.write("struct device dev_root;\n")
-			return
-		# This is pass the second, which is pass number 1
-		# this is really just a case statement ...
-
-		if (self.chip_or_device == 'chip'):
-			if (self.chipconfig):
-				debug.info(debug.gencode, "gencode: chipconfig(%d)" % \
-					self.instance)
-				file.write("struct %s_config %s" % (self.type_name ,\
-					self.chipinfo_name))
-				if (self.registercode):
-					file.write("\t= {\n")
-					for f, v in self.registercode.items():
-						file.write( "\t.%s = %s,\n" % (f, v))
-					file.write("};\n")
-				else:
-					file.write(";")
-				file.write("\n")
-
-			if (self.instance == 0):
-				self.instance_name = "dev_root"
-				file.write("struct device **last_dev_p = &%s.next;\n" % (self.image.last_device.instance_name))
-				file.write("struct device dev_root = {\n")
-				file.write("\t.ops = &default_dev_ops_root,\n")
-				file.write("\t.bus = &dev_root.link[0],\n")
-				file.write("\t.path = { .type = DEVICE_PATH_ROOT },\n")
-				file.write("\t.enabled = 1,\n\t.links = 1,\n")
-				file.write("\t.on_mainboard = 1,\n")
-				file.write("\t.link = {\n\t\t[0] = {\n")
-				file.write("\t\t\t.dev=&dev_root,\n\t\t\t.link = 0,\n")
-				file.write("\t\t\t.children = &%s,\n" % self.firstchilddevice().instance_name)
-				file.write("\t\t},\n")
-				file.write("\t},\n")
-				if (self.chipconfig):
-					file.write("\t.chip_ops = &%s_ops,\n" % self.type_name)
-					file.write("\t.chip_info = &%s_info_%s,\n" % (self.type_name, self.instance))
-				file.write("\t.next = &%s,\n" % self.firstchilddevice().instance_name)
-				file.write("};\n")
-			return
-
-		# Don't print duplicate devices, just print their children
-		if (self.dup):
-			return
-
-		file.write("struct device %s = {\n" % self.instance_name)
-		file.write("\t.ops = 0,\n")
-		file.write("\t.bus = &%s.link[%d],\n" % \
-			(self.firstparentdevice().instance_name, \
-			self.firstparentdevicelink()))
-		file.write("\t.path = {%s},\n" % self.path)
-		file.write("\t.enabled = %d,\n" % self.enabled)
-		file.write("\t.on_mainboard = 1,\n")
-		if (self.resources):
-			file.write("\t.resources = %d,\n" % self.resources)
-			file.write("\t.resource = {%s\n\t },\n" % self.resource)
-		file.write("\t.link = {\n");	
-		links = 0
-		bus = self
-		while(bus and (bus.path == self.path)):
-			child = bus.firstchilddevice()
-			if (child or (bus != self) or (bus.next_sibling and (bus.next_sibling.path == self.path))):
-				file.write("\t\t[%d] = {\n" % links)
-				file.write("\t\t\t.link = %d,\n" % links)
-				file.write("\t\t\t.dev = &%s,\n" % self.instance_name)
-				if (child):
-					file.write("\t\t\t.children = &%s,\n" %child.instance_name)
-				file.write("\t\t},\n")
-				links = links + 1
-			if (1):	
-				bus = bus.next_sibling
-			else:
-				bus = 0
-		file.write("\t},\n")
-		file.write("\t.links = %d,\n" % (links))
-		sibling = self.firstsiblingdevice(); 
-		if (sibling):
-			file.write("\t.sibling = &%s,\n" % sibling.instance_name)
-		chip = self.firstparentchip()
-		if (chip and chip.chipconfig):
-			file.write("\t.chip_ops = &%s_ops,\n" % chip.type_name)
-			file.write("\t.chip_info = &%s_info_%s,\n" % (chip.type_name, chip.instance))
-		if (self.next_device):	
-			file.write("\t.next=&%s\n" % self.next_device.instance_name)
-		file.write("};\n")
-		return
-
-    	def addinit(self, code):
-		"""Add init file to this part"""
-        	self.initcode.append(code)
-		
-    	def addconfig(self, path):
-		"""Add chip config file to this part"""
-        	self.chipconfig = os.path.join(self.dir, path)
-		self.image.addconfiginclude(self.type_name, self.chipconfig)
-
-    	def addregister(self, field, value):
-		"""Register static initialization information"""
-		if (self.chip_or_device != 'chip'):
-			fatal("Only chips can have register values")
-		field = dequote(field)
-		value = dequote(value)
-        	setdict(self.registercode, field, value)
-
-	def set_enabled(self, enabled):
-		self.enabled = enabled
-
-	def start_resources(self):
-		self.resource = ""
-		self.resources = 0
-
-	def end_resources(self):
-		self.resource = "%s" % (self.resource)
-
-	def add_resource(self, type, index, value):
-		""" Add a resource to a device """
-		self.resource = "%s\n\t\t{ .flags=%s, .index=0x%x, .base=0x%x}," % (self.resource, type, index, value)
-		self.resources = self.resources + 1
-
-	def set_path(self, path):
-		self.path = path
-		if (self.prev_sibling and (self.prev_sibling.path == self.path)):
-			self.dup = 1
-			if (self.prev_device):
-				self.prev_device.next_device = self.next_device
-			if (self.next_device):	
-				self.next_device.prev_device = self.prev_device
-			if (self.image.last_device == self):
-				self.image.last_device = self.prev_device
-			self.prev_device = 0
-			self.next_device = 0
-		
-	def addpcipath(self, slot, function):
-		""" Add a relative pci style path from our parent to this device """
-		if ((slot < 0) or (slot > 0x1f)):
-			fatal("Invalid device id")
-		if ((function < 0) or (function > 7)):
-			fatal("Invalid pci function %s" % function )
-		self.set_path(".type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%x,%d)}}" % (slot, function))
-
-	def addpnppath(self, port, device):
-		""" Add a relative path to a pnp device hanging off our parent """
-		if ((port < 0) or (port > 65536)):
-			fatal("Invalid port")
-		if ((device < 0) or (device > 0xffff)):
-			fatal("Invalid device")
-		self.set_path(".type=DEVICE_PATH_PNP,{.pnp={ .port = 0x%x, .device = 0x%x }}" % (port, device))
-		
-	def addi2cpath(self, device):
-		""" Add a relative path to a i2c device hanging off our parent """
-		if ((device < 0) or (device > 0x7f)):
-			fatal("Invalid device")
-		self.set_path(".type=DEVICE_PATH_I2C,{.i2c={ .device = 0x%x }}" % (device))
-
-	def addapicpath(self, apic_id):
-		""" Add a relative path to a cpu device hanging off our parent """
-		if ((apic_id < 0) or (apic_id > 255)):
-			fatal("Invalid device")
-		self.set_path(".type=DEVICE_PATH_APIC,{.apic={ .apic_id = 0x%x }}" % (apic_id))
-    
-	def addpci_domainpath(self, pci_domain):
-		""" Add a pci_domain number to a chip """
-		if ((pci_domain < 0) or (pci_domain > 0xffff)):
-			fatal("Invalid pci_domain: 0x%x is out of the range 0 to 0xffff" % pci_domain)
-		self.set_path(".type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%x }}" % (pci_domain))
-    
-	def addapic_clusterpath(self, cluster):
-		""" Add an apic cluster to a chip """
-		if ((cluster < 0) or (cluster > 15)):
-			fatal("Invalid apic cluster: %d is out of the range 0 to ff" % cluster)
-		self.set_path(".type=DEVICE_PATH_APIC_CLUSTER,{.apic_cluster={ .cluster = 0x%x }}" % (cluster))
-    
-	def addcpupath(self, cpu_id):
-		""" Add a relative path to a cpu device hanging off our parent """
-		if ((cpu_id < 0) or (cpu_id > 255)):
-			fatal("Invalid device")
-		self.set_path(".type=DEVICE_PATH_CPU,{.cpu={ .id = 0x%x }}" % (cpu_id))
-    
-
-	def addcpu_buspath(self, id):
-		""" Add a cpu_bus to a chip """
-		if ((id < 0) or (id > 255)):
-			fatal("Invalid device")
-		self.set_path(".type=DEVICE_PATH_CPU_BUS,{.cpu_bus={ .id = 0x%x }}" % (id))
-    
-	def usesoption(self, name):
-		"""Declare option that can be used by this part"""
-		global global_options
-		o = getdict(global_options, name)
-		if (o == 0):
-			fatal("can't use undefined option %s" % name)
-		o1 = getdict(self.uses_options, name)
-		if (o1):
-			return
-		setdict(self.uses_options, name, o)
-		exportoption(o, self.image.exported_options)
-
-# -----------------------------------------------------------------------------
-#                    statements 
-# -----------------------------------------------------------------------------
-
-def getdict(dict, name):
-	if name not in dict.keys(): 
-		debug.info(debug.dict, "Undefined: %s" % name)
-		return 0
-	v = dict.get(name, 0)
-	debug.info(debug.dict, "getdict %s returning %s" % (name, v))
-	return v
-
-def setdict(dict, name, value):
-	debug.info(debug.dict, "setdict sets %s to %s" % (name, value))
-	if name in dict.keys():
-		print "Duplicate in dict: %s" % name
-	dict[name] = value
-
-# options. 
-# to create an option, it has to not exist. 
-# When an option value is fetched, the fact that it was used is 
-# remembered. 
-# Legal things to do:
-# set a default value, then set a real value before the option is used.
-# set a value, try to set a default, default silently fails.
-# Illegal:
-# use the value, then try to set the value
-
-def newoption(name):
-	global global_options, global_options_by_order
-	o = getdict(global_options, name)
-	if (o):
-		fatal("option %s already defined" % name)
-	o = option(name)
-	setdict(global_options, name, o)
-	global_options_by_order.append(name)
-
-def newoptionvalue(name, image):
-	g = getdict(global_option_values, name)
-	v = option_value(name, g)
-	if (image):
-		setdict(image.getvalues(), name, v)
-	else:
-		setdict(global_option_values, name, v)
-	return v
-
-def getoptionvalue(name, op, image):
-	global global_option_values
-	#print "getoptionvalue name %s op %s image %s\n" % (name, op,image)
-	if (op == 0):
-		# we want to debug config files, not the config tool, so no:
-		# print_stack() 
-		fatal("Option %s undefined (missing use command?)" % name)
-	if (image):
-		v = getdict(image.getvalues(), name)
-	else:
-		v = getdict(global_option_values, name)
-	return v
-
-def getoption(name, image):
-	"""option must be declared before being used in a part
-	if we're not processing a part, then we must
-	be at the top level where all options are available"""
-
-	global global_uses_options, alloptions, curimage
-
-	#print "getoption: name %s image %s alloptions %s curimage %s\n\n" % (name, image, alloptions, curimage)
-	curpart = partstack.tos()
-	if (alloptions):
-		o = getdict(global_options, name)
-	elif (curpart):
-		o = getdict(curpart.uses_options, name)
-		if (o == 0):
-			print "curpart.uses_options is %s\n" % curpart.uses_options
-	else:
-		o = getdict(global_uses_options, name)
-	v = getoptionvalue(name, o, image)
-	if (v == 0):
-		v = getoptionvalue(name, o, 0)
-	if (v == 0):
-		fatal("No value for option %s" % name)
-	val = v.contents()
-	if (not (type(val) is types.StringType)):
-		return v.contents()
-	if (val == '' or val[0] != '{'):
-		return v.contents()
-	s = curimage
-	curimage = image
-	val = parse('delexpr', val)
-	curimage = s
-	exitiferrors()
-	return val
-
-def setoption(name, value, imp):
-	"""Set an option from within a configuration file. Normally this
-	is only permitted in the target (top level) configuration file.
-	If 'imp' is true, then set an option implicitly (e.g. 'arch' 
-	and 'mainboard' statements). Implicit options can be set anywhere 
-	the statements are legal, but also performs an implicit 'uses' 
-	for the option"""
-
-	global loc, global_options, global_option_values, curimage
-
-	curpart = partstack.tos()
-	if (not imp and curpart):
-		fatal("Options may only be set in target configuration file")
-	if (imp):
-		usesoption(name)
-	if (curpart):
-		o = getdict(curpart.uses_options, name)
-	else:
-		o = getdict(global_uses_options, name)
-	if (not o):
-		fatal("Attempt to set nonexistent option %s (missing USES?)" % name)
-	v = getoptionvalue(name, o, curimage)
-	if (v == 0):
-		v = newoptionvalue(name, curimage)
-	v.setvalue(value)
-
-def exportoption(op, exported_options):
-	if (not op.isexportable()):
-		return
-	if (not op in exported_options):
-		exported_options.append(op)
-
-def setdefault(name, value, isdef):
-	"""Set the default value of an option from within a configuration 
-	file. This is permitted from any configuration file, but will
-	result in a warning if the default is set more than once.
-	If 'isdef' is set, we're defining the option in Options.lb so
-	there is no need for 'uses'."""
-
-	global loc, global_options, curimage
-
-	if (isdef):
-		o = getdict(global_options, name)
-		if (not o):
-			return
-		image = 0
-	else:
-		curpart = partstack.tos()
-		if (curpart):
-			o = getdict(curpart.uses_options, name)
-		else:
-			o = getdict(global_uses_options, name)
-		if (not o):
-			fatal("Attempt to set default for nonexistent option %s (missing USES?)" % name)
-		image = curimage
-
-	v = getoptionvalue(name, o, image)
-	if (v == 0):
-		v = newoptionvalue(name, image)
-	v.setdefault(value)
-
-def setnodefault(name):
-	global loc, global_options
-	o = getdict(global_options, name)
-	if (not o):
-		return
-	v = getdict(global_option_values, name)
-	if (v != 0):
-		warning("removing default for %s" % name)
-		del global_option_values[name]
-
-def setcomment(name, value):
-	global loc, global_options
-	o = getdict(global_options, name)
-	if (not o):
-		fatal("setcomment: %s not here" % name)
-	o.setcomment(value, loc)
-
-def setexported(name):
-	global global_options
-	o = getdict(global_options, name)
-	if (not o):
-		fatal("setexported: %s not here" % name)
-	o.setexportable()
-	global_exported_options.append(o)
-
-def setnoexport(name):
-	global global_options
-	o = getdict(global_options, name)
-	if (not o):
-		fatal("setnoexport: %s not here" % name)
-	o.setnoexport()
-	if (o in global_exported_options):
-		global_exported_options.remove(o)
-
-def setexportable(name):
-	global global_options
-	o = getdict(global_options, name)
-	if (not o):
-		fatal("setexportable: %s not here" % name)
-	o.setexportable()
-
-def setformat(name, fmt):
-	global global_options
-	o = getdict(global_options, name)
-	if (not o):
-		fatal("setformat: %s not here" % name)
-	o.setformat(fmt)
-
-def getformated(name, image):
-	global global_options, global_option_values
-	o = getdict(global_options, name)
-	v = getoption(name, image)
-	f = o.getformat()
-	return (f % v)
-
-def setwrite(name, part):
-	global global_options
-	o = getdict(global_options, name)
-	if (not o):
-		fatal("setwrite: %s not here" % name)
-	o.setwrite(part)
-
-def hasvalue(name, image):
-	global global_options
-	o = getdict(global_options, name)
-	if (o == 0):
-		return 0
-	v = 0
-	if (image):
-		v = getdict(image.getvalues(), name)
-	if (v == 0):
-		v = getdict(global_option_values, name)
-	return (v != 0)
-
-def isset(name, part):
-	global global_uses_options, global_option_values, curimage
-	if (part):
-		o = getdict(part.uses_options, name)
-	else:
-		o = getdict(global_uses_options, name)
-	if (o == 0):
-		return 0
-	v = 0
-	if (curimage):
-		v = getdict(curimage.getvalues(), name)
-	if (v == 0):
-		v = getdict(global_option_values, name)
-	return (v != 0 and v.isset())
-
-def usesoption(name):
-	global global_options, global_uses_options
-	curpart = partstack.tos()
-	if (curpart):
-		curpart.usesoption(name)
-		return
-	o = getdict(global_options, name)
-	if (o == 0):
-		fatal("Can't use undefined option %s" % name)
-	o1 = getdict(global_uses_options, name)
-	if (o1):
-		return
-	setdict(global_uses_options, name, o)
-	exportoption(o, global_exported_options)
-
-def validdef(name, defval):
-	global global_options
-	o = getdict(global_options, name)
-	if (not o):
-		fatal("validdef: %s not here" % name)
-	if ((defval & 1) != 1):
-	    fatal("Must specify default value for option %s" % name)
-	if ((defval & 2) != 2):
-	    fatal("Must specify export for option %s" % name)
-	if ((defval & 4) != 4):
-	    fatal("Must specify comment for option %s" % name)
-
-def loadoptions(path, file, rule):
-	file = os.path.join('src', path, file)
-	optionsfile = os.path.join(treetop, file)
-	fp = safe_open(optionsfile, 'r')
-	loc.push(file)
-	if (not parse(rule, fp.read())):
-		fatal("Could not parse file")
-	loc.pop()
-
-def addinit(path):
-	global curimage, dirstack
-	if (path[0] == '/'):
-		curimage.setinitfile(treetop + '/src/' + path)
-	else:
-		curimage.setinitfile(dirstack.tos() + '/' + path)
-	print "Adding init file: %s" % path
-
-def addconfig(path):
-	global partstack
-	curpart = partstack.tos()
-	curpart.addconfig(path)
-
-def addregister(field, value):
-	global partstack
-	curpart = partstack.tos()
-	curpart.addregister(field, value)
-
-def addcrt0include(path):
-	"""we do the crt0include as a dictionary, so that if needed we
-	can trace who added what when. Also it makes the keys
-	nice and unique."""
-	global curimage
-	curimage.addinitinclude(0, path)
-
-def addinitinclude(str, path):
-	global curimage
-	curimage.addinitinclude(dequote(str), path)
-
-def addldscript(path):
-	global curimage, dirstack
-	curdir = dirstack.tos()
-	if (path[0] == '/'):
-		fullpath =  treetop + '/src/' + path
-	else:
-		fullpath = curdir + '/' + path
-	debug.info(debug.statement, "fullpath :%s: curdir :%s: path :%s:" % (fullpath, curdir, path))
-	curimage.addldscript(fullpath)
-
-def payload(path):
-	global curimage
-	curimage.setpayload(path)
-	adduserdefine("PAYLOAD:=%s"%path)
-
-def startromimage(name):
-	global romimages, curimage, target_dir, target_name
-	curpart = partstack.tos()
-	print "Configuring ROMIMAGE %s Curimage %s" % (name, curimage)
-	print "Curpart is %s\n" % curpart
-	o = getdict(romimages, name)
-	if (o):
-		fatal("romimage %s previously defined" % name)
-	curimage = romimage(name)
-	curimage.settargetdir(os.path.join(target_dir, name))
-	#o = partobj(curimage, target_dir, 0, 'board', target_name)
-	#curimage.setroot(o)
-	setdict(romimages, name, curimage)
-	dodir('/config', 'Config.lb')
-
-def endromimage():
-	global curimage
-	global bootblocksize
-	mainboard()
-	imagesize = getoption("CONFIG_ROM_IMAGE_SIZE", curimage)
-	bootblocksize += imagesize
-	print "End ROMIMAGE"
-	curimage = 0
-	#curpart = 0
-
-def mainboardsetup(path):
-	global full_mainboard_path, mainboard_path
-	mainboard_path = os.path.join('mainboard', path)
-	loadoptions(mainboard_path, 'Options.lb', 'mainboardvariables')
-	full_mainboard_path = os.path.join(treetop, 'src', 'mainboard', path)
-	vendor = re.sub("/.*", "", path)
-        part_number = re.sub("[^/]*/", "", path)
-	setdefault('CONFIG_MAINBOARD', full_mainboard_path, 0)
-	setdefault('CONFIG_MAINBOARD_VENDOR', vendor, 0)
-	setdefault('CONFIG_MAINBOARD_PART_NUMBER', part_number, 0)
-
-def mainboard():
-	global curimage, dirstack, partstack
-	file = 'Config.lb'
-	partdir = mainboard_path
-	srcdir = os.path.join(treetop, 'src')
-	fulldir = os.path.join(srcdir, partdir)
-	type_name = flatten_name(partdir)
-	newpart = partobj(curimage, fulldir, partstack.tos(), 'mainboard', \
-		'mainboard', 0, 'chip')
-	#print "Configuring PART %s" % (type)
-	partstack.push(newpart)
-	#print "  new PART tos is now %s\n" %partstack.tos().info()
-	dirstack.push(fulldir)
-	loadoptions(mainboard_path, 'Options.lb', 'mainboardvariables')
-	# special case for 'cpu' parts.
-	# we could add a new function too, but this is rather trivial.
-	# if the part is a cpu, and we haven't seen it before,
-	# arrange to source the directory /cpu/'type'
-	doconfigfile(srcdir, partdir, file, 'cfgfile')
-	curimage.setroot(partstack.tos())
-	partpop()
-
-def addbuildrom(filename, size, roms):
-	global buildroms
-	print "Build ROM size %d" % size
-	b = buildrom(filename, size, roms)
-	buildroms.append(b)
-
-def addpci_rom(filename, vendor, device):
-	global pciroms
-	print "Add PCI ROM %s" %filename
-	p = pci_rom(filename, vendor, device)
-	pciroms.append(p)
-
-def addinitobject(object_name):
-	global curimage
-	curimage.addinitobjectrule(object_name)
-
-def addobject(object_name):
-	global curimage
-	curimage.addobjectrule(object_name)
-
-def adddriver(driver_name):
-	global curimage
-	curimage.adddriverrule(driver_name)
-
-def addsmmobject(object_name):
-	global curimage
-	curimage.addsmmobjectrule(object_name)
-
-def target(name):
-        global target_dir, target_name
-	print "Configuring TARGET %s" % name
-	target_name = name
-	target_dir = os.path.join(os.path.dirname(loc.file()), name)
-	if not os.path.isdir(target_dir):
-		print "Creating directory %s" % target_dir
-		os.makedirs(target_dir)
-	print "Will place Makefile, crt0.S, etc. in %s" % target_dir
-
-
-def cpudir(path):
-	global cpu_type
-	if (cpu_type and (cpu_type != path)):
-		fatal("Two different CPU types: %s and %s" % (cpu_type, path))
-	srcdir = "/cpu/%s" % path
-	dodir(srcdir, "Config.lb")
-	cpu_type = path
-	
-def devicepart(type):
-	global curimage, dirstack, partstack
-	newpart = partobj(curimage, 0, partstack.tos(), type, \
-			'', 0, 'device')
-	#print "Configuring PART %s" % (type)
-	partstack.push(newpart)
-	#print "  new PART tos is now %s\n" %partstack.tos().info()
-	# just push TOS, so that we can pop later. 
-	dirstack.push(dirstack.tos())
-	
-def part(type, path, file, name):
-	global curimage, dirstack, partstack
-        partdir = os.path.join(type, path)
-	srcdir = os.path.join(treetop, 'src')
-	fulldir = os.path.join(srcdir, partdir)
-	type_name = flatten_name(partdir)
-	newpart = partobj(curimage, fulldir, partstack.tos(), type, \
-			type_name, name, 'chip')
-	#print "Configuring PART %s, path %s" % (type, path)
-	partstack.push(newpart)
-	#print "  new PART tos is now %s\n" %partstack.tos().info()
-	dirstack.push(fulldir)
-	# special case for 'cpu' parts. 
-	# we could add a new function too, but this is rather trivial.
-	# if the part is a cpu, and we haven't seen it before, 
-	# arrange to source the directory /cpu/'type'
-	if (type == 'cpu'):
-		cpudir(path)
-	else:
-		doconfigfile(srcdir, partdir, file, 'cfgfile')
-
-def partpop():
-	global dirstack, partstack
-	curpart = partstack.tos()
-	if (curpart == 0):
-		fatal("Trying to pop non-existent part")
-	#print "End PART %s" % curpart.part
-	# Warn if options are used without being set in this part
-	for op in curpart.uses_options.keys():
-		if (not isset(op, curpart)):
-			notice("Option %s using default value %s" % (op, getformated(op, curpart.image)))
-	oldpart = partstack.pop()
-	dirstack.pop()
-	#print "partstack.pop, TOS is now %s\n" % oldpart.info()
-
-def dodir(path, file):
-	"""dodir is like part but there is no new part"""
-	global dirstack
-	# if the first char is '/', it is relative to treetop, 
-	# else relative to curdir
-	# os.path.join screws up if the name starts with '/', sigh.
-	print "Configuring DIR %s" % os.path.join(path, file)
-	if (path[0] == '/'):
-		fullpath = os.path.join(treetop, 'src')
-		path = re.sub('^/*', '', path)
-	else:
-		fullpath = dirstack.tos()
-	debug.info(debug.statement, "DODIR: path %s, fullpath %s" % (path, fullpath))
-	dirstack.push(os.path.join(fullpath, path))
-	doconfigfile(fullpath, path, file, 'cfgfile')
-	dirstack.pop()
-
-def dofile(path):
-	"""dofile is a simple include for single files"""
-	# if the first char is '/', it is relative to treetop, 
-	# else relative to curdir
-	# os.path.join screws up if the name starts with '/', sigh.
-	if (path[0] == '/'):
-		fullpath = os.path.join(treetop, 'src')
-		path = re.sub('^/*', '', path)
-	else:
-		fullpath = dirstack.tos()
-	print "INCLUDE %s" %path
-	debug.info(debug.statement, "DOFILE: path %s, fullpath %s" % (path, fullpath))
-	doconfigfile(fullpath, '', path, 'cfgfile')
-
-def lookup(name):
-	global curimage
-	return getoption(name, curimage)
-
-def addrule(id):
-	global curimage
-	curimage.addmakerule(id)
-	
-def adduserdefine(str):
-	global curimage
-	curimage.adduserdefine(str)
-
-def addaction(id, str):
-	global curimage
-	curimage.addmakeaction(id, str)
-
-def adddep(id, str):
-	global curimage
-	curimage.addmakedepend(id, str)
-
-def setarch(my_arch):
-	"""arch is 'different' ... darn it."""
-	global curimage
-	print "SETTING CONFIG_ARCH %s\n" % my_arch
-	curimage.setarch(my_arch)
-	setdefault('CONFIG_ARCH', my_arch, 1)
-	part('arch', my_arch, 'Config.lb', 0)
-
-def doconfigfile(path, confdir, file, rule):
-	rname = os.path.join(confdir, file)
-	loc.push(rname)
-	fullpath = os.path.join(path, rname)
-	fp = safe_open(fullpath, 'r')
-	if (not parse(rule, fp.read())):
-		fatal("Could not parse file")
-	exitiferrors()
-	loc.pop()
-
-#=============================================================================
-#		MISC FUNCTIONS
-#=============================================================================
-def ternary(val, yes, no):
-	debug.info(debug.statement, "ternary %s" % expr)
-	debug.info(debug.statement, "expr %s a %d yes %d no %d"% (expr, a, yes, no))
-        if (val == 0):
-		debug.info(debug.statement, "Ternary returns %d" % yes)
-		return yes
-        else:
-		debug.info(debug.statement, "Ternary returns %d" % no)
-		return no
-
-def tohex(name):
-	"""atoi is in the python library, but not strtol? Weird!"""
-	return eval('int(%s)' % name)
-
-def IsInt(str):
-	""" Is the given string an integer?"""
-	try:
-		num = long(str)
-		return 1
-	except ValueError:
-		return 0
-
-def dequote(str):
-	a = re.sub("^\"", "", str)
-	a = re.sub("\"$", "", a)
-	# highly un-intuitive, need four \!
-	a = re.sub("\\\\\"", "\"", a)
-	return a
-
-def flatten_name(str):
-	a = re.sub("[/-]", "_", str)
-	return a
-
-def topify(path):
-	"""If the first part of <path> matches treetop, replace 
-	that part with $(TOP)"""
-	if path[0:len(treetop)] == treetop:
-		path = path[len(treetop):len(path)]
-		if (path[0:1] == "/"):
-			path = path[1:len(path)]
-		path = "$(TOP)/" + path
-	return path
-
-%%
-# to make if work without 2 passses, we use an old hack from SIMD, the 
-# context bit. If the bit is 1, then ops get done, otherwise
-# ops don't get done. From the top level, context is always
-# 1. In an if, context depends on eval of the if condition
-
-parser Config:
-    ignore:			r'\s+'
-    ignore:			"#.*?\r?\n"
-
-    # less general tokens should come first, otherwise they get matched
-    # by the re's
-    token ACTION:		'action'
-    token ADDACTION:		'addaction'
-    token ALWAYS:		'always'
-    token ARCH:			'arch'
-    token BUILDROM:		'buildrom'
-    token COMMENT:		'comment'
-    token CONFIG:		'config'
-    token CPU:			'cpu'
-    token CPU_BUS:		'cpu_bus'
-    token CHIP:			'chip'
-    token DEFAULT:		'default'
-    token DEFINE:		'define'
-    token DEPENDS:		'depends'
-    token DEVICE:		'device'
-    token DEVICE_ID:		'device_id'
-    token DIR:			'dir'
-    token DRIVER:		'driver'
-    token DRQ:			'drq'
-    token ELSE:			'else'
-    token END:			'end'
-    token EOF:			'$'
-    token EQ:			'='
-    token EXPORT:		'export'
-    token FORMAT:		'format'
-    token IF:			'if'
-    token INIT:			'init'
-    token INITOBJECT:		'initobject'
-    token INITINCLUDE:		'initinclude'
-    token INCLUDE:		'include'
-    token IO:			'io'
-    token IRQ:			'irq'
-    token LDSCRIPT:		'ldscript'
-    token LOADOPTIONS:		'loadoptions'
-    token MAINBOARD:		'mainboard'
-    token MAINBOARDINIT:	'mainboardinit'
-    token MAKEDEFINE:		'makedefine'
-    token MAKERULE:		'makerule'
-    token MEM:			'mem'
-    token NEVER:		'never'
-    token NONE:			'none'
-    token NORTHBRIDGE:		'northbridge'
-    token OBJECT:		'object'
-    token OPTION:		'option'
-    token PAYLOAD:		'payload'
-    token PCI_ROM:		'pci_rom'
-    token PMC:			'pmc'
-    token PRINT:		'print'
-    token REGISTER:		'register'
-    token ROMIMAGE:		'romimage'
-    token SMMOBJECT:		'smmobject'
-    token SOUTHBRIDGE:		'southbridge'
-    token SUPERIO:		'superio'
-    token TARGET:		'target'
-    token USED:			'used'
-    token USES:			'uses'
-    token VENDOR_ID:		'vendor_id'
-    token WRITE:		'write'
-    token NUM:			'[0-9]+'
-    token HEX_NUM:		'[0-9a-fA-F]+'
-    token HEX_PREFIX:		'0x'
-    # Why is path separate? Because paths to resources have to at least
-    # have a slash, we thinks
-    token PATH:			r'[-a-zA-Z0-9_.][-a-zA-Z0-9/_.]+[-a-zA-Z0-9_.]+'
-    # Dir's on the other hand are abitrary
-    # this may all be stupid.
-    token RULE:			r'[-a-zA-Z0-9_$()./]+[-a-zA-Z0-9_ $()./]+[-a-zA-Z0-9_$()./]+'
-    token DIRPATH:		r'[-a-zA-Z0-9_$()./,]+'
-    token ID:			r'[a-zA-Z_.]+[a-zA-Z0-9_.]*'
-    token DELEXPR:		r'{([^}]+|\\.)*}'
-    token STR:			r'"([^\\"]+|\\.)*"'
-    token RAWTEXT:		r'.*'
-    token ON:			'on'
-    token OFF:			'off'
-    token PCI:			'pci'
-    token PNP:			'pnp'
-    token I2C:			'i2c'
-    token APIC:			'apic'
-    token APIC_CLUSTER:		'apic_cluster'
-    token CPU:			'cpu'
-    token CPU_BUS:		'cpu_bus'
-    token PCI_DOMAIN:		'pci_domain'
-
-
-    rule expr:		logical			{{ l = logical }}
-			( "&&" logical		{{ l = l and logical }}
-			| "[|][|]" logical	{{ l = l or logical }}
-			)*			{{ return l }}
-
-    rule logical:	factor			{{ n = factor }}
-			( "[+]" factor		{{ n = n+factor }}
-			| "-"  factor		{{ n = n-factor }}
-			)*			{{ return n }}
-
-    rule factor:	term			{{ v = term }}
-			( "[*]" term		{{ v = v*term }}
-			| "/"  term		{{ v = v/term }}
-			| "<<"  term		{{ v = v << term }}
-			| ">=" term		{{ v = (v < term)}}
-			)*			{{ return v }}
-
-    # A term is a number, variable, or an expression surrounded by parentheses
-    rule term:		NUM			{{ return long(NUM, 10) }}
-		|	HEX_PREFIX HEX_NUM	{{ return long(HEX_NUM, 16) }}
-		|	ID			{{ return lookup(ID) }}
-		|	unop			{{ return unop }}
-		|	"\\(" expr "\\)"	{{ return expr }}
-
-    rule unop:		"!" expr		{{ return not(expr) }}
-
-    rule partend<<C>>:	(stmt<<C>>)* END 	{{ if (C): partpop()}}
-
-    # This is needed because the legacy cpu command could not distinguish
-    # between cpu vendors. It should just be PATH, but getting this change
-    # into the source tree will be tricky... 
-    # DO NOT USE ID AS IT MAY GO AWAY IN THE FUTURE
-    rule partid:	ID 			{{ return ID }}
-		|	PATH			{{ return PATH }}
-
-#    rule parttype:	NORTHBRIDGE		{{ return 'northbridge' }} 
-#    		|	SUPERIO 		{{ return 'superio' }}
-#		|	PMC			{{ return 'pmc' }}
-#		|	SOUTHBRIDGE		{{ return 'southbridge' }}
-#		|	CPU			{{ return 'cpu' }}
-#		|	CHIP                    {{ return '' }}
-#
-    rule parttype:	CHIP                    {{ return '' }}
-
-    rule partdef<<C>>:				{{ name = 0 }} 
-			parttype partid		
-			[ STR			{{ name = dequote(STR) }}
-			]                       {{ if (C): part(parttype, partid, 'Config.lb', name) }}
-			partend<<C>> 		
-
-    rule arch<<C>>:	ARCH ID			{{ if (C): setarch(ID) }}
-			partend<<C>>
-    
-    rule mainboardinit<<C>>:
-			MAINBOARDINIT DIRPATH	{{ if (C): addcrt0include(DIRPATH)}}
-
-    rule initinclude<<C>>: 
-			INITINCLUDE 
-			STR 
-			DIRPATH			{{ if (C): addinitinclude(STR, DIRPATH)}}
-
-    rule initobject<<C>>:
-			INITOBJECT DIRPATH	{{ if (C): addinitobject(DIRPATH)}}
-
-    rule object<<C>>:	OBJECT DIRPATH		{{ if (C): addobject(DIRPATH)}}
-
-    rule driver<<C>>:	DRIVER DIRPATH		{{ if (C): adddriver(DIRPATH)}}
-
-    rule smmobject<<C>>:
-    			SMMOBJECT DIRPATH	{{ if (C): addsmmobject(DIRPATH)}}
-
-
-    rule dir<<C>>:	DIR DIRPATH 		{{ if (C): dodir(DIRPATH, 'Config.lb') }}
-
-    rule default<<C>>:	DEFAULT ID EQ value	{{ if (C): setdefault(ID, value, 0) }}
-
-    rule ldscript<<C>>:	LDSCRIPT DIRPATH	{{ if (C): addldscript(DIRPATH) }}
-
-    rule iif<<C>>:	IF ID			{{ c = lookup(ID) }}
-			(stmt<<C and c>>)* 
-			[ ELSE (stmt<<C and not c>>)* ]
-			END
-
-    rule makerule<<C>>:	MAKERULE RULE		{{ if (C): addrule(RULE) }}
-			( DEPENDS STR		{{ if (C): adddep(RULE, STR) }}
-			| ACTION STR		{{ if (C): addaction(RULE, STR) }}
-			)*
-			END
-
-    rule makedefine<<C>>:
-			MAKEDEFINE RAWTEXT	{{ if (C): adduserdefine(RAWTEXT) }}
-
-    rule addaction<<C>>:
-			ADDACTION ID STR	{{ if (C): addaction(ID, STR) }}
-
-    rule init<<C>>:	INIT DIRPATH		{{ if (C): addinit(DIRPATH) }}
-
-    rule field:		STR			{{ return STR }}
-
-    rule register<<C>>:	REGISTER field '=' STR	{{ if (C): addregister(field, STR) }}
-
-    rule enable<<C>>:				{{ val = 1 }}
-	    		( ON 			{{ val = 1 }}
-			| OFF			{{ val = 0 }}
-			) 			{{ if(C): partstack.tos().set_enabled(val) }}
-
-    rule resource<<C>>:				{{ type = "" }}
-	    		(  IO			{{ type = "IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO" }}
-			|   MEM			{{ type = "IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_MEM" }}
-			|   IRQ			{{ type = "IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IRQ" }}
-			|   DRQ			{{ type = "IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_DRQ" }}
-			)
-			term '='		{{ index = term }}
-			term			{{ value = term }}
-						{{ if (C): partstack.tos().add_resource(type, index, value) }}
-    
-			     
-    rule resources<<C>>:			{{ if (C): partstack.tos().start_resources() }}
-	    		( resource<<C>> )*
-						{{ if (C): partstack.tos().end_resources() }}
-	    
-    
-    rule pci<<C>>:	PCI 			{{ if (C): devicepart('pci') }}
-
-    			HEX_NUM			{{ slot = int(HEX_NUM,16) }}
-			'.' HEX_NUM		{{ function = int(HEX_NUM, 16) }}
-						{{ if (C): partstack.tos().addpcipath(slot, function) }}
-    rule pci_domain<<C>>:	
-			PCI_DOMAIN 		{{ if (C): devicepart('pci_domain') }}
-			HEX_NUM			{{ pci_domain = int(HEX_NUM, 16) }}
-						{{ if (C): partstack.tos().addpci_domainpath(pci_domain) }}
-
-    rule pnp<<C>>:	PNP  			{{ if (C): devicepart('pnp') }}
-			HEX_NUM			{{ port = int(HEX_NUM,16) }}
-			'.' HEX_NUM		{{ device = int(HEX_NUM, 16) }}
-						{{ if (C): partstack.tos().addpnppath(port, device) }}
-						
-    rule i2c<<C>>:	I2C   			{{ if (C): devicepart('i2c') }}
-			HEX_NUM			{{ device = int(HEX_NUM, 16) }}
-						{{ if (C): partstack.tos().addi2cpath(device) }}
-
-    rule apic<<C>>:	APIC   			{{ if (C): devicepart('apic') }}
-			HEX_NUM			{{ apic_id = int(HEX_NUM, 16) }}
-						{{ if (C): partstack.tos().addapicpath(apic_id) }}
-
-    rule apic_cluster<<C>>: APIC_CLUSTER 	{{ if (C): devicepart('apic_cluster') }}
-			HEX_NUM			{{ cluster = int(HEX_NUM, 16) }}
-						{{ if (C): partstack.tos().addapic_clusterpath(cluster) }}
-
-    rule include<<C>>:	INCLUDE DIRPATH 	{{ dofile(DIRPATH) }}
-
-    rule cpu<<C>>:	CPU			{{ if (C): devicepart('cpu') }}
-    			HEX_NUM			{{ id = int(HEX_NUM, 16) }}
-						{{ if (C): partstack.tos().addcpupath(id) }}
-
-    rule cpu_bus<<C>>:	CPU_BUS			{{ if (C): devicepart('cpu_bus') }}
-    			HEX_NUM			{{ id = int(HEX_NUM, 16) }}
-						{{ if (C): partstack.tos().addcpu_buspath(id) }}
-
-    rule dev_path<<C>>:
-	    		pci<<C>>		{{ return pci }}
-		|	pci_domain<<C>>		{{ return pci_domain }}
-	    	|	pnp<<C>>		{{ return pnp }}
-		|	i2c<<C>>		{{ return i2c }}
-		|	apic<<C>>		{{ return apic }}
-		|	apic_cluster<<C>>	{{ return apic_cluster }}
-		|	cpu<<C>>		{{ return cpu }}
-		|	cpu_bus<<C>>		{{ return cpu_bus }}
-		
-    rule prtval:	expr			{{ return str(expr) }}
-		|	STR			{{ return STR }}
-
-    rule prtlist:	prtval			{{ el = "%(" + prtval }}
-			( "," prtval 		{{ el = el + "," + prtval }}
-			)*			{{ return el + ")" }}	
-
-    rule prtstmt<<C>>:	PRINT STR 		{{ val = STR }}
-			[ "," prtlist 		{{ val = val + prtlist }}
-			]			{{ if (C): print eval(val) }}
-
-    rule config<<C>>:	CONFIG PATH		{{ if (C): addconfig(PATH) }}
-
-    rule device<<C>>:   DEVICE dev_path<<C>>
-    			enable<<C>>			
-			resources<<C>>
-			partend<<C>> 
-
-    rule stmt<<C>>:	arch<<C>>		{{ return arch}}
-		|	addaction<<C>>		{{ return addaction }}
-    		|	config<<C>>		{{ return config}}
-		|	default<<C>>		{{ return default}}
-		|	dir<<C>>		{{ return dir}}
-		|	driver<<C>>		{{ return driver }}
-		|	iif<<C>>	 	{{ return iif }}
-		|	init<<C>>	 	{{ return init }}
-		|	initinclude<<C>>	{{ return initinclude }}
-		|	include<<C>>		{{ return include }}
-		|	initobject<<C>>		{{ return initobject }}
-		|	ldscript<<C>>		{{ return ldscript}}
-		|	mainboardinit<<C>>	{{ return mainboardinit }}
-		|	makedefine<<C>> 	{{ return makedefine }}
-		|	makerule<<C>>		{{ return makerule }}
-		|	object<<C>>		{{ return object }}
-		|	option<<C>>		{{ return option }}
-		|	partdef<<C>>		{{ return partdef }}
-		| 	prtstmt<<C>>		{{ return prtstmt }}
-		|	register<<C>> 		{{ return register }}
-		|	device<<C>>		{{ return device }}
-		|	smmobject<<C>>		{{ return smmobject }}
-
-    # ENTRY for parsing Config.lb file
-    rule cfgfile:	(uses<<1>>)* 
-    			(stmt<<1>>)*
-			EOF			{{ return 1 }}
-
-    rule usesid<<C>>:	ID			{{ if (C): usesoption(ID) }}
-
-    rule uses<<C>>:	USES (usesid<<C>>)+
-
-    rule mainboardvariables:	(uses<<1>>)*
-				(default<<1>>)*
-				(option<<1>>)*
-				END		{{ return 1}}
-
-    rule value:		STR			{{ return dequote(STR) }} 
-		| 	expr			{{ return expr }}
-		|	DELEXPR			{{ return DELEXPR }}
-
-    rule option<<C>>:	OPTION ID EQ value	{{ if (C): setoption(ID, value, 0) }}
-
-    rule opif<<C>>:	IF ID			{{ c = lookup(ID) }}
-			(opstmt<<C and c>>)* 
-			[ ELSE (opstmt<<C and not c>>)* ] 
-			END
-
-    rule opstmt<<C>>:	option<<C>>
-		|	opif<<C>>
-		|	prtstmt<<C>>
-
-    rule payload<<C>>:	PAYLOAD DIRPATH		{{ if (C): payload(DIRPATH) }}
-
-    rule mainboard:
-			MAINBOARD PATH		{{ mainboardsetup(PATH) }}
-
-    rule romif<<C>>:	IF ID			{{ c = lookup(ID) }}
-			(romstmt<<C and c>>)* 
-			[ ELSE (romstmt<<C and not c>>)* ]
-			END
-
-    rule romstmt<<C>>:	romif<<C>>
-		|	option<<C>>
-		|	payload<<C>>
-
-    rule romimage:	ROMIMAGE STR		{{ startromimage(dequote(STR)) }}
-			(romstmt<<1>>)*
-			END			{{ endromimage() }}
-
-    rule roms:		STR			{{ s = '[' + STR }}
-			( STR			{{ s = s + "," + STR }}
-			)*			{{ return eval(s + ']') }}
-
-    rule buildrom:	BUILDROM DIRPATH expr roms	{{ addbuildrom(DIRPATH, expr, roms) }}
-
-    rule pci_vid:	VENDOR_ID EQ term	{{ return term }}
-
-    rule pci_did:	DEVICE_ID EQ term	{{ return term }}
-
-
-    rule pci_rom:	PCI_ROM DIRPATH pci_vid pci_did	{{ addpci_rom(DIRPATH, pci_vid, pci_did) }}
-
-    rule romstmts:	romimage 
-		|	buildrom
-		|	opstmt<<1>>
-		|	pci_rom
-
-    # ENTRY for parsing root part
-    rule board:		{{ loadoptions("config", "Options.lb", "options") }}
-	    		TARGET DIRPATH		{{ target(DIRPATH) }}
-			mainboard
-			(romstmts)*		
-			EOF			{{ return 1 }}
-
-    # ENTRY for parsing a delayed value
-    rule delexpr:	"{" expr "}" EOF	{{ return expr }}
-
-    rule wrstr<<ID>>:	STR			{{ setwrite(ID, dequote(STR)) }}
-
-    rule defstmts<<ID>>:			{{ d = 0 }}
-			( DEFAULT
-			  ( value		{{ setdefault(ID, value, 1) }}
-			  | NONE		{{ setnodefault(ID) }}
-			  )			{{ d = d | 1 }}
-			| FORMAT STR		{{ setformat(ID, dequote(STR)) }}
-			| EXPORT 
-			  ( ALWAYS		{{ setexported(ID) }}
-			  | USED		{{ setexportable(ID) }}
-			  | NEVER		{{ setnoexport(ID) }}
-			  )			{{ d = d | 2 }}
-			| COMMENT STR 		{{ setcomment(ID, dequote(STR)); d = d | 4 }}
-			| WRITE (wrstr<<ID>>)+
-			)+			{{ return d }}
-		
-    rule define:	DEFINE ID 		{{ newoption(ID) }}
-			defstmts<<ID>> END	{{ validdef(ID, defstmts) }}
-
-    # ENTRY for parsing Options.lb file
-    rule options:	(define)* EOF		{{ return 1 }}
-%%
-
-#=============================================================================
-#		FILE OUTPUT 
-#=============================================================================
-def writemakefileheader(file, fname):
-	file.write("# File: %s is autogenerated\n" % fname)
-
-def writemakefilefooter(file, fname):
-	file.write("\n\n%s: %s %s\n"
-		% (os.path.basename(fname), os.path.abspath(sys.argv[0]), top_config_file))
-	file.write("\t(cd %s ; export PYTHONPATH=%s/util/newconfig ; python %s %s %s)\n\n"
-		% (os.getcwd(), treetop, sys.argv[0], sys.argv[1], sys.argv[2]))
-
-def writemakefilesettings(path):
-	""" Write Makefile.settings to seperate the settings
-	from the actual makefile creation."""
-
-	global treetop, target_dir
-
-	filename = os.path.join(path, "Makefile.settings")
-	print "Creating", filename
-	file = safe_open(filename, 'w+')
-	writemakefileheader(file, filename)
-	file.write("TOP:=%s\n" % (treetop))
-	file.write("TARGET_DIR:=%s\n" % target_dir)
-	writemakefilefooter(file, filename)
-	file.close()
-
-def writeimagesettings(image):
-	"""Write Makefile.settings to seperate the settings
-	from the actual makefile creation."""
-
-	global treetop
-	global global_options_by_order
-
-	filename = os.path.join(image.gettargetdir(), "Makefile.settings")
-	print "Creating", filename
-	file = safe_open(filename, 'w+')
-	writemakefileheader(file, filename)
-	file.write("TOP:=%s\n" % (treetop))
-	file.write("TARGET_DIR:=%s\n" % (image.gettargetdir()))
-	file.write("\n")
-	exported = []
-	for o in global_exported_options:
-		exported.append(o)
-	for o in image.exported_options:
-		if (not o in exported):
-			exported.append(o)
-	for o in exported:
-		file.write("export %s:=" % o.name)
-		if (hasvalue(o.name, image)):
-			file.write("%s" % getformated(o.name, image))
-		file.write("\n")
-	file.write("\n")
-	file.write("export VARIABLES :=\n")
-	for o in exported:
-		file.write("export VARIABLES += %s\n" % o.name)
-	file.write("\n")
-	# writemakefilefooter(file,filename)
-	file.close()
-
-# write the romimage makefile
-# let's try the Makefile
-# first, dump all the -D stuff
-
-def writeimagemakefile(image):
-	makefilepath = os.path.join(image.gettargetdir(), "Makefile")
-	print "Creating", makefilepath
-	file = safe_open(makefilepath, 'w+')
-	writemakefileheader(file, makefilepath)
-
-	# main rule
-	file.write("\nall: coreboot.rom\n\n")
-	file.write(".PHONY: all\n\n")
-	#file.write("include cpuflags\n")
-	# Putting "include cpuflags" in the Makefile has the problem that the
-	# cpuflags file would be generated _after_ we want to include it.
-	# Instead, let make do the work of computing CPUFLAGS:
-	file.write("# Get the value of TOP, VARIABLES, and several other variables.\n")
-	file.write("include Makefile.settings\n\n")
-	file.write("# Function to create an item like -Di586 or -DCONFIG_MAX_CPUS='1' or -Ui686\n")
-	file.write("D_item = $(shell echo '$(if $(subst undefined,,$(origin $1)),\\#define $1$(if $($1), $($1),),\\#undef $1)' >> settings.h)\n\n")
-	file.write("# Compute the value of CPUFLAGS here during make's first pass.\n")
-	file.write("CPUFLAGS := $(strip $(shell echo '/* autogenerated */' > settings.h)$(foreach _var_,$(VARIABLES),$(call D_item,$(_var_)))-include $(CURDIR)/settings.h)\n\n")
-
-	for i in image.getuserdefines():
-		file.write("%s\n" %i)
-	file.write("\n")
-
-	# print out all the object dependencies
-	file.write("\n# object dependencies (objectrules:)\n")
-	file.write("INIT-OBJECTS :=\n")
-	file.write("OBJECTS :=\n")
-	file.write("DRIVER :=\n")
-	file.write("\nSOURCES :=\n")
-	for irule, init in image.getinitobjectrules().items():
-		i_name = init[0]
-		i_source = init[1]
-		file.write("INIT-OBJECTS += %s\n" % (i_name))
-		file.write("SOURCES += %s\n" % (i_source))
-
-	for objrule, obj in image.getobjectrules().items():
-		obj_name = obj[0]
-		obj_source = obj[1]
-		file.write("OBJECTS += %s\n" % (obj_name))
-		file.write("SOURCES += %s\n" % (obj_source))
-
-	for srule, smm in image.getsmmobjectrules().items():
-		s_name = smm[0]
-		s_source = smm[1]
-		file.write("SMM-OBJECTS += %s\n" % (s_name))
-		file.write("SOURCES += %s\n" % (s_source))
-
-
-	# for chip_target.c
-	file.write("OBJECTS += static.o\n")
-	file.write("SOURCES += static.c\n")
-
-	for driverrule, driver in image.getdriverrules().items():
-		obj_name = driver[0]
-		obj_source = driver[1]
-		file.write("DRIVER += %s\n" % (obj_name))
-		file.write("SOURCES += %s\n" % (obj_source))
-
-	# Print out all ldscript.ld dependencies.
-	file.write("\n# ldscript.ld dependencies:\n")
-	file.write("LDSUBSCRIPTS-1 := \n" )
-	for script in image.getldscripts():
-		file.write("LDSUBSCRIPTS-1 += %s\n" % topify(script))
-
-	# Print out the dependencies for crt0_includes.h
-	file.write("\n# Dependencies for crt0_includes.h\n")
-	file.write("CRT0_INCLUDES:=\n")
-	for inc in image.getinitincludes():
-		if (local_path.match(inc)):
-			file.write("CRT0_INCLUDES += %s\n" % inc)
-		else:
-			file.write("CRT0_INCLUDES += $(TOP)/src/%s\n" % inc)
-
-	# Print out the user defines.
-	file.write("\n# userdefines:\n")
-		
-	# Print out the base rules.
-	# Need to have a rule that counts on 'all'.
-	file.write("\n# mainrulelist:")
-
-	# Print out any user rules.
-	file.write("\n# From makerule or docipl commands:\n")
-
-	file.write("\n# initobjectrules:\n")
-	for irule, init in image.getinitobjectrules().items():
-		image.addmakeobject(file, init);
-
-	file.write("\n# objectrules (don't duplicate initobjects):\n")
-	for objrule, obj in image.getobjectrules().items():
-
-		if (getdict(image.getinitobjectrules(), obj[3])):
-			debug.info(debug.object, "skipping %s" % (obj[3]))
-		else:
-			image.addmakeobject(file, obj);
-
-	for driverrule, driver in image.getdriverrules().items():
-		source = topify(driver[1])
-		file.write("%s: %s\n" % (driver[0], source))
-		file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
-		#file.write("%s\n" % objrule[2])
-
-	file.write("\n# smmobjectrules:\n")
-	for irule, smm in image.getsmmobjectrules().items():
-		image.addmakeobject(file, smm);
-
-	# special rule for chip_target.c
-	file.write("static.o: static.c\n")
-	file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
-
-	# Print out the rules that will make cause the files
-	# generated by NLBConfig.py to be remade if any dependencies change.
-
-	file.write("\n# Remember the automatically generated files\n")
-	file.write("GENERATED:=\n")
-	for genfile in ['Makefile',
-			'nsuperio.c',
-			'static.c',
-			'corebootDoc.config' ]:
-		file.write("GENERATED += %s\n" % genfile)
-	file.write("GENERATED += %s\n" % image.getincludefilename())
-
-	keys = global_options_by_order
-	keys.sort()
-	file.write("\necho:\n")
-	for key in keys:
-		 file.write("\t@echo %s='$(%s)'\n"% (key,key))
-
-	for i, m in image.getmakerules().items():
-		file.write("%s: " %i)
-		for i in m.dependency:
-			file.write("%s " % i)
-		file.write("\n")
-		for i in m.actions:
-			file.write("\t%s\n" % i)
-	writemakefilefooter(file, makefilepath)
-	file.close()
-
-#
-def writemakefile(path):
-	global rommapping
-	global bootblocksize
-	makefilepath = os.path.join(path, "Makefile")
-	print "Creating", makefilepath
-	file = safe_open(makefilepath, 'w+')
-	writemakefileheader(file, makefilepath)
-
-	# Hack to get the necessary settings (CONFIG_COMPRESSED_PAYLOAD_LZMA):
-	file.write("include %s/Makefile.settings\n\n" % romimages.keys()[0])
-
-	# main rule
-	file.write("\nall: ")
-	for i in buildroms:
-		file.write(" %s" % i.name)
-	file.write("\n")
-
-	# cbfstool rules
-	file.write("\ncbfstool:\n\tmkdir -p cbfs\n\t$(MAKE) -C $(TOP)/util/cbfstool obj=$(shell pwd)/cbfs\n")
-	file.write("\ncbfstool-clean:\n\t$(MAKE) -C $(TOP)/util/cbfstool obj=$(shell pwd)/cbfs clean\n\n")
-
-	file.write("include Makefile.settings\n\n")
-	for i, o in romimages.items():
-		file.write("%s/coreboot.rom:\n" % o.getname())
-		file.write("\t$(MAKE) -C %s coreboot.rom\n" % o.getname())
-	file.write("clean: ")
-	for i in romimages.keys():
-		file.write(" %s-clean" % i)
-	file.write(" base-clean")
-	file.write("\n\n")
-	for i, o in romimages.items():
-		file.write("%s-clean:\n" % o.getname())
-		file.write("\t(cd %s; $(MAKE) clean)\n\n" % o.getname())
-	file.write("base-clean:\n")
-	file.write("\trm -f romcc*\n\n")
-
-	file.write("CBFS_COMPRESS_FLAG:=\n")
-	file.write("CBFS_STAGE_COMPRESS_FLAG:=\n")
-	file.write("ifeq \"$(CONFIG_COMPRESSED_PAYLOAD_LZMA)\" \"1\"\nCBFS_COMPRESS_FLAG:=l\nendif\n\n")
-	file.write("ifeq \"$(CONFIG_COMPRESS)\" \"1\"\nCBFS_STAGE_COMPRESS_FLAG:=l\nendif\n\n")
-
-	for i in buildroms:
-		file.write("%s: cbfstool" %(i.name))
-		for j in i.roms:
-			file.write(" %s/coreboot.rom " % j)
-		file.write("\n")
-
-		romsize = getoption("CONFIG_ROM_SIZE", image)
-
-		file.write("\n\trm -f %s\n" %(i.name))
-
-		# build the bootblock here.
-		file.write("\n\tcat")
-		for j in i.roms:
-			file.write(" %s/coreboot.rom " % j)
-		file.write("> %s.bootblock\n\n" %i.name)
-		file.write("\t./cbfs/cbfstool %s create %s %s.bootblock\n"
-			   %(i.name, romsize, i.name))
-		for j in pciroms:
-			file.write("\t./cbfs/cbfstool %s add %s pci%04x,%04x.rom optionrom\n" % (i.name, j.name, j.pci_vid, j.pci_did))
-		for j in i.roms:
-			#failover is a hack that will go away soon. 
-			if (j != "failover") and (rommapping[j] != "/dev/null"):
-				file.write("\t./cbfs/cbfstool %s add-payload %s %s/payload $(CBFS_COMPRESS_FLAG)\n" % (i.name, rommapping[j], j,))
-			if (j != "failover"):
-				file.write("\t./cbfs/cbfstool %s add-stage %s/coreboot_ram %s/coreboot_ram $(CBFS_STAGE_COMPRESS_FLAG)\n" % (i.name, j, j,))
-			file.write("\tif [ -f %s/coreboot_apc ]; then ./cbfs/cbfstool %s add-stage %s/coreboot_apc %s/coreboot_apc $(CBFS_COMPRESS_FLAG); fi\n" % (j, i.name, j, j,))
-		file.write("\t./cbfs/cbfstool %s print\n" % i.name)
-		file.write("\n")
-
-	file.write(".PHONY: all clean cbfstool")
-	for i in romimages.keys():
-		file.write(" %s-clean" % i)
-	for i, o in romimages.items():
-		file.write(" %s/coreboot.rom" % o.getname())
-	file.write("\n\n")
-
-	writemakefilefooter(file, makefilepath)
-	file.close()
-
-def writeinitincludes(image):
-	global include_pattern
-	filepath = os.path.join(image.gettargetdir(), image.getincludefilename())
-	print "Creating", filepath
-	outfile = safe_open(filepath, 'w+')
-	if (image.newformat()):
-		infile = safe_open(image.getinitfile(), 'r')
-
-		line = infile.readline()
-		while (line):
-			p = include_pattern.match(line)
-			if (p):
-				for i in image.getinitincludes():
-					inc = image.getinitinclude(i)
-					if (inc.getstring() == p.group(1)):
-						outfile.write("#include \"%s\"\n" % inc.getpath())
-			else:
-				outfile.write(line)
-			line = infile.readline()
-
-		infile.close()
-	else:
-		for i in image.getinitincludes():
-			outfile.write("#include <%s>\n" % i)
-	outfile.close()
-
-def writeldoptions(image):
-	"""Write ldoptions file."""
-	filename = os.path.join(image.gettargetdir(), "ldoptions")
-	print "Creating", filename
-	file = safe_open(filename, 'w+')
-	for o in global_exported_options:
-		if (hasvalue(o.name, image) and IsInt(getoption(o.name, image))):
-			file.write("%s = %s;\n" % (o.name, getformated(o.name, image)))
-	for o in image.exported_options:
-		if (not o in global_exported_options and hasvalue(o.name, image) and IsInt(getoption(o.name, image))):
-			file.write("%s = %s;\n" % (o.name, getformated(o.name, image)))
-	file.close()
-
-def dumptree(part, lvl):
-	debug.info(debug.dumptree, "DUMPTREE ME is")
-	part.dumpme(lvl)
-	# dump the siblings -- actually are there any? not sure
-	# siblings are:
-	debug.info(debug.dumptree, "DUMPTREE SIBLINGS are")
-	kid = part.next_sibling
-	while (kid):
-		kid.dumpme(lvl)
-		kid = kid.next_sibling
-	# dump the kids
-	debug.info(debug.dumptree, "DUMPTREE KIDS are")
-	#for kid in part.children:
-	if (part.children):
-		dumptree(part.children, lvl+1)
-	kid = part.next_sibling
-	while (kid):
-		if (kid.children):
-			dumptree(kid.children, lvl + 1)
-		kid = kid.next_sibling
-	debug.info(debug.dumptree, "DONE DUMPTREE")
-
-def writecode(image):
-	filename = os.path.join(img_dir, "static.c")
-	print "Creating", filename
-	file = safe_open(filename, 'w+')
-	file.write("#include <device/device.h>\n")
-	file.write("#include <device/pci.h>\n")
-	for path in image.getconfigincludes().values():
-		file.write("#include \"%s\"\n" % path)
-	file.write("\n/* pass 0 */\n")
-	gencode(image.getroot(), file, 0)
-	file.write("\n/* pass 1 */\n")
-	gencode(image.getroot(), file, 1)
-	file.close()
-
-def gencode(part, file, pass_num):
-	debug.info(debug.gencode, "GENCODE ME is")
-	part.gencode(file, pass_num)
-	# dump the siblings -- actually are there any? not sure
-	debug.info(debug.gencode, "GENCODE SIBLINGS are")
-	kid = part.next_sibling
-	while (kid):
-		kid.gencode(file, pass_num)
-		kid = kid.next_sibling
-	# now dump the children 
-	debug.info(debug.gencode, "GENCODE KIDS are")
-	if (part.children):
-		gencode(part.children, file, pass_num)
-	kid = part.next_sibling
-	while (kid):
-		if (kid.children):
-			gencode(kid.children, file, pass_num)
-		kid = kid.next_sibling
-	debug.info(debug.gencode, "DONE GENCODE")
-
-def writegraph(image):
-	filename = os.path.join(img_dir, "static.dot")
-	print "Creating", filename
-	file = safe_open(filename, 'w+')
-	file.write("digraph devicetree {\n")
-	file.write("	rankdir=LR\n")
-	genranks(image.getroot(), file, 0)
-	gennodes(image.getroot(), file)
-	gengraph(image.getroot(), file)
-	file.write("}\n")
-	file.close()
-
-def genranks(part, file, level):
-	#file.write("	# Level %d\n" % level )
-	file.write("	{ rank = same; \"dev_%s_%d\"" % (part.type_name,part.instance ))
-	sib = part.next_sibling
-	while (sib):
-		file.write("; \"dev_%s_%d\"" % (sib.type_name, sib.instance))
-		sib = sib.next_sibling
-	file.write("}\n" )
-	# now dump the children 
-	if (part.children):
-		genranks(part.children, file, level + 1)
-
-	kid = part.next_sibling
-	while (kid):
-		if (kid.children):
-			genranks(kid.children, file, level + 1)
-		kid = kid.next_sibling
-
-
-def gennodes(part, file):
-	file.write("	dev_%s_%d[shape=record, label=\"%s\"];\n" % (part.type_name,part.instance,part.graph_name() ))
-	sib = part.next_sibling
-	while (sib):
-		file.write("	dev_%s_%d[shape=record, label=\"%s\"];\n" % (sib.type_name,sib.instance,sib.graph_name() ))
-		sib = sib.next_sibling
-	# now dump the children
-	if (part.children):
-		gennodes(part.children, file)
-
-	kid = part.next_sibling
-	while (kid):
-		if (kid.children):
-			gennodes(kid.children, file)
-		kid = kid.next_sibling
-
-
-def gengraph(part, file):
-	if (part.parent != part):
-		file.write("	dev_%s_%d -> dev_%s_%d;\n" % \
-				(part.parent.type_name, part.parent.instance, \
-				 part.type_name, part.instance ))
-	sib = part.next_sibling
-	while (sib):
-		file.write("	dev_%s_%d -> dev_%s_%d;\n" % \
-				(sib.parent.type_name, sib.parent.instance, \
-				 sib.type_name, sib.instance ))
-		sib = sib.next_sibling
-
-	kid = part.next_sibling
-	while (kid):
-		if (kid.children):
-			gengraph(kid.children, file)
-		kid = kid.next_sibling
-
-	if (part.children):
-		gengraph(part.children, file)
-
-def verifyparse():
-	"""Add any run-time checks to verify that parsing the configuration
-	was successful"""
-
-	for image in romimages.values():
-		print("Verifying ROMIMAGE %s" % image.name)
-		if (image.newformat() and image.getinitfile() == ''):
-			fatal("An init file must be specified")
-		for op in image.exported_options:
-			if (getoptionvalue(op.name, op, image) == 0 and getoptionvalue(op.name, op, 0) == 0):
-				warning("Exported option %s has no value (check Options.lb)" % op.name);
-	print("Verifing global options")
-	for op in global_exported_options:
-		if (getoptionvalue(op.name, op, 0) == 0):
-			notice("Exported option %s has no value (check Options.lb)" % op.name);
-			
-#=============================================================================
-#		MAIN PROGRAM
-#=============================================================================
-if __name__=='__main__':
-	from sys import argv
-	if (len(argv) < 3):
-		fatal("Args: <file> <path to coreboot>")
-
-	top_config_file = os.path.abspath(sys.argv[1])
-
-	treetop = os.path.abspath(sys.argv[2])
-
-	# Now read in the customizing script...
-	loc.push(argv[1])
-	fp = safe_open(argv[1], 'r')
-	if (not parse('board', fp.read())):
-		fatal("Could not parse file")
-	loc.pop()
-
-	verifyparse()
-
-	# no longer need to check if an options has been used
-	alloptions = 1
-
-	for image_name, image in romimages.items():
-		if (debug.level(debug.dumptree)):
-			debug.info(debug.dumptree, "DEVICE TREE:")
-			dumptree(image.getroot(), 0)
-
-		img_dir = image.gettargetdir()
-		if not os.path.isdir(img_dir):
-			print "Creating directory %s" % img_dir
-			os.makedirs(img_dir)
-
-		for objrule, obj in image.getobjectrules().items():
-			sub_dir = img_dir + '/' + os.path.dirname(obj[0])
-			if not os.path.isdir(sub_dir):
-				print "Creating sub directory %s" % sub_dir
-				os.makedirs(sub_dir)
-
-		for driverrule, driver in image.getdriverrules().items():
-			sub_dir = img_dir + '/' + os.path.dirname(driver[0])
-			if not os.path.isdir(sub_dir):
-				print "Creating sub directory %s" % sub_dir
-				os.makedirs(sub_dir)
-
-		for srule, smm in image.getsmmobjectrules().items():
-			sub_dir = img_dir + '/' + os.path.dirname(smm[0])
-			if not os.path.isdir(sub_dir):
-				print "Creating sub directory %s" % sub_dir
-				os.makedirs(sub_dir)
-
-		for irule, init in image.getinitobjectrules().items():
-			sub_dir = img_dir + '/' + os.path.dirname(init[0])
-			if not os.path.isdir(sub_dir):
-				print "Creating sub directory %s" % sub_dir
-				os.makedirs(sub_dir)
-
-		if (debug.level(debug.dump)):
-			for i in image.getinitincludes():
-				debug.info(debug.dump, "crt0include file %s" % i)
-			for i in image.getdriverrules().keys():
-				debug.info(debug.dump, "driver file %s" % i)
-			for i in image.getldscripts():
-				debug.info(debug.dump, "ldscript file %s" % i)
-			for i, m in image.getmakerules().items():
-				debug.info(debug.dump, " makerule %s dep %s act %s" % (i, m.dependency, m.actions))
-
-		writecode(image)
-		writeimagesettings(image)
-		writeinitincludes(image)
-		writeimagemakefile(image)
-		writeldoptions(image)
-		writegraph(image)
-
-	writemakefilesettings(target_dir)
-	writemakefile(target_dir)
-
-	sys.exit(0)
diff --git a/util/newconfig/parsedesc.g b/util/newconfig/parsedesc.g
deleted file mode 100644
index 7113c6d..0000000
--- a/util/newconfig/parsedesc.g
+++ /dev/null
@@ -1,196 +0,0 @@
-######################################################################
-# The remainder of this file is from parsedesc.{g,py}
-
-def append(lst, x):
-    "Imperative append"
-    lst.append(x)
-    return lst
-
-def add_inline_token(tokens, str):
-    tokens.insert( 0, (str, eval(str, {}, {})) )
-    return Terminal(str)
-
-def cleanup_choice(lst):
-    if len(lst) == 0: return Sequence([])
-    if len(lst) == 1: return lst[0]
-    return apply(Choice, tuple(lst))
-
-def cleanup_sequence(lst):
-    if len(lst) == 1: return lst[0]
-    return apply(Sequence, tuple(lst))
-
-def cleanup_rep(node, rep):
-    if rep == 'star':   return Star(node)
-    elif rep == 'plus': return Plus(node)
-    else:               return node
-
-def resolve_name(tokens, id, args):
-    if id in map(lambda x: x[0], tokens):
-	# It's a token
-	if args: 
-	    print 'Warning: ignoring parameters on TOKEN %s<<%s>>' % (id, args)
-        return Terminal(id)
-    else:
-        # It's a name, so assume it's a nonterminal
-        return NonTerminal(id, args)
-
-%%
-parser ParserDescription:
-    option:      "context-insensitive-scanner"
-
-    ignore:      "[ \t\r\n]+"
-    ignore:      "#.*?\r?\n"
-    token END:   "$"
-    token ATTR:  "<<.+?>>"
-    token STMT:  "{{.+?}}"
-    token ID:    '[a-zA-Z_][a-zA-Z_0-9]*'
-    token STR:   '[rR]?\'([^\\n\'\\\\]|\\\\.)*\'|[rR]?"([^\\n"\\\\]|\\\\.)*"'
-    token LP:    '\\('
-    token RP:    '\\)'
-    token LB:    '\\['
-    token RB:    '\\]'
-    token OR:    '[|]'
-    token STAR:  '[*]'
-    token PLUS:  '[+]'
-    token QUEST: '[?]'
-    token COLON: ':'
-
-    rule Parser: "parser" ID ":"
-                   Options
-                   Tokens
-                   Rules<<Tokens>> 
-                 END 
-                 {{ return Generator(ID,Options,Tokens,Rules) }}
-
-    rule Options: {{ opt = {} }}
-                  ( "option" ":" Str {{ opt[Str] = 1 }} )*
-                  {{ return opt }}
-
-    rule Tokens:  {{ tok = [] }}
-                  (
-                    "token" ID ":" Str {{ tok.append( (ID,Str) ) }}
-                  | "ignore"   ":" Str {{ tok.append( ('#ignore',Str) ) }}
-                  )*
-                  {{ return tok }}
-
-    rule Rules<<tokens>>:
-                  {{ rul = [] }}
-                  (
-                    "rule" ID OptParam ":" ClauseA<<tokens>>
-                    {{ rul.append( (ID,OptParam,ClauseA) ) }}
-                  )*
-                  {{ return rul }}
-
-    rule ClauseA<<tokens>>:
-                  ClauseB<<tokens>>
-                  {{ v = [ClauseB] }}
-                  ( OR ClauseB<<tokens>> {{ v.append(ClauseB) }} )*
-                  {{ return cleanup_choice(v) }}
-
-    rule ClauseB<<tokens>>:
-                  {{ v = [] }}
-                  ( ClauseC<<tokens>> {{ v.append(ClauseC) }} )*
-                  {{ return cleanup_sequence(v) }}
-
-    rule ClauseC<<tokens>>:
-                  ClauseD<<tokens>>
-                  ( PLUS {{ return Plus(ClauseD) }}
-                  | STAR {{ return Star(ClauseD) }}
-                  |      {{ return ClauseD }} )
-
-    rule ClauseD<<tokens>>:
-                  STR {{ t = (STR, eval(STR,{},{})) }}
-                      {{ if t not in tokens: tokens.insert( 0, t ) }} 
-                      {{ return Terminal(STR) }}
-                | ID OptParam {{ return resolve_name(tokens, ID, OptParam) }}
-                | LP ClauseA<<tokens>> RP {{ return ClauseA }}
-                | LB ClauseA<<tokens>> RB {{ return Option(ClauseA) }}
-                | STMT {{ return Eval(STMT[2:-2]) }}
-
-    rule OptParam: [ ATTR {{ return ATTR[2:-2] }} ] {{ return '' }}
-    rule Str:   STR {{ return eval(STR,{},{}) }}
-%%
-
-# This replaces the default main routine
-
-yapps_options = [
-    ('context-insensitive-scanner', 'context-insensitive-scanner',
-     'Scan all tokens (see docs)')
-    ]
-
-def generate(inputfilename, outputfilename='', dump=0, **flags):
-    """Generate a grammar, given an input filename (X.g)
-    and an output filename (defaulting to X.py)."""
-
-    if not outputfilename:
-	if inputfilename[-2:]=='.g': outputfilename = inputfilename[:-2]+'.py'
-	else: raise "Invalid Filename", outputfilename
-        
-    print 'Input Grammar:', inputfilename
-    print 'Output File:', outputfilename
-    
-    DIVIDER = '\n%%\n' # This pattern separates the pre/post parsers
-    preparser, postparser = None, None # Code before and after the parser desc
-
-    # Read the entire file
-    s = open(inputfilename,'r').read()
-
-    # See if there's a separation between the pre-parser and parser
-    f = find(s, DIVIDER)
-    if f >= 0: preparser, s = s[:f]+'\n\n', s[f+len(DIVIDER):]
-
-    # See if there's a separation between the parser and post-parser
-    f = find(s, DIVIDER)
-    if f >= 0: s, postparser = s[:f], '\n\n'+s[f+len(DIVIDER):]
-
-    # Create the parser and scanner
-    p = ParserDescription(ParserDescriptionScanner(s))
-    if not p: return
-    
-    # Now parse the file
-    t = wrap_error_reporter(p, 'Parser')
-    if not t: return # Error
-    if preparser is not None: t.preparser = preparser
-    if postparser is not None: t.postparser = postparser
-
-    # Check the options
-    for f in t.options.keys():
-        for opt,_,_ in yapps_options:
-            if f == opt: break
-        else:
-            print 'Warning: unrecognized option', f
-    # Add command line options to the set
-    for f in flags.keys(): t.options[f] = flags[f]
-            
-    # Generate the output
-    if dump:
-        t.dump_information()
-    else:
-        t.output = open(outputfilename, 'w')
-        t.generate_output()
-
-if __name__=='__main__':
-    import sys, getopt
-    optlist, args = getopt.getopt(sys.argv[1:], 'f:', ['dump'])
-    if not args or len(args) > 2:
-        print 'Usage:'
-        print '  python', sys.argv[0], '[flags] input.g [output.py]'
-        print 'Flags:'
-        print ('  --dump' + ' '*40)[:35] + 'Dump out grammar information'
-        for flag, _, doc in yapps_options:
-            print ('  -f' + flag + ' '*40)[:35] + doc
-    else:
-        # Read in the options and create a list of flags
-	flags = {}
-	for opt in optlist:
-	    for flag, name, _ in yapps_options:
-		if opt == ('-f', flag):
-		    flags[name] = 1
-		    break
-	    else:
-                if opt == ('--dump', ''):
-                    flags['dump'] = 1
-		else:
-                    print 'Warning - unrecognized option:  ', opt[0], opt[1]
-
-        apply(generate, tuple(args), flags)
diff --git a/util/newconfig/test.config b/util/newconfig/test.config
deleted file mode 100644
index c492f20..0000000
--- a/util/newconfig/test.config
+++ /dev/null
@@ -1,6 +0,0 @@
-target x
-mainboard amd/solo
-#  option X=1
-#  makerule x y "z"
-  payload /dev/null
-end
diff --git a/util/newconfig/yapps2.py b/util/newconfig/yapps2.py
deleted file mode 100644
index 71bfa05..0000000
--- a/util/newconfig/yapps2.py
+++ /dev/null
@@ -1,779 +0,0 @@
-# Yapps 2.0 - yet another python parser system
-# Amit J Patel, January 1999
-# See http://theory.stanford.edu/~amitp/Yapps/ for documentation and updates
-
-# v2.0.1 changes (October 2001):
-# * The exceptions inherit the standard Exception class (thanks Rich Salz)
-# * The scanner can use either a different set of regular expressions
-#   per instance, or allows the subclass to define class fields with
-#   the patterns.  This improves performance when many Scanner objects
-#   are being created, because the regular expressions don't have to
-#   be recompiled each time. (thanks Amaury Forgeot d'Arc)
-# v2.0.2 changes (April 2002)
-# * Fixed a bug in generating the 'else' clause when the comment was too
-#   long.  v2.0.1 was missing a newline.  (thanks Steven Engelhardt)
-# v2.0.3 changes (August 2002)
-# * Fixed a bug with inline tokens using the r"" syntax.
-
-from string import *
-from yappsrt import *
-import re
-
-INDENT = " "*4
-
-class Generator:
-    def __init__(self, name, options, tokens, rules):
-        self.change_count = 0
-        self.name = name
-        self.options = options
-        self.preparser = ''
-        self.postparser = None
-        
-        self.tokens = {} # Map from tokens to regexps
-        self.ignore = [] # List of token names to ignore in parsing
-        self.terminals = [] # List of token names (to maintain ordering)
-        for n,t in tokens:
-            if n == '#ignore':
-                n = t
-                self.ignore.append(n)
-            if n in self.tokens.keys() and self.tokens[n] != t:
-                print 'Warning: token', n, 'multiply defined.'
-            self.tokens[n] = t
-            self.terminals.append(n)
-            
-        self.rules = {} # Map from rule names to parser nodes
-        self.params = {} # Map from rule names to parameters
-        self.goals = [] # List of rule names (to maintain ordering)
-        for n,p,r in rules:
-            self.params[n] = p
-            self.rules[n] = r
-            self.goals.append(n)
-            
-        import sys
-        self.output = sys.stdout
-
-    def __getitem__(self, name):
-        # Get options
-        return self.options.get(name, 0)
-    
-    def non_ignored_tokens(self):
-        return filter(lambda x, i=self.ignore: x not in i, self.terminals)
-    
-    def changed(self):
-        self.change_count = 1+self.change_count
-
-    def subset(self, a, b):
-        "See if all elements of a are inside b"
-        for x in a:
-            if x not in b: return 0
-        return 1
-    
-    def equal_set(self, a, b):
-        "See if a and b have the same elements"
-        if len(a) != len(b): return 0
-        if a == b: return 1
-        return self.subset(a, b) and self.subset(b, a)
-    
-    def add_to(self, parent, additions):
-        "Modify parent to include all elements in additions"
-        for x in additions:
-            if x not in parent:
-                parent.append(x)
-                self.changed()
-
-    def equate(self, a, b):
-        self.add_to(a, b)
-        self.add_to(b, a)
-
-    def write(self, *args):
-        for a in args:
-            self.output.write(a)
-
-    def in_test(self, x, full, b):
-        if not b: return '0'
-        if len(b)==1: return '%s == %s' % (x, `b[0]`)
-        if full and len(b) > len(full)/2:
-            # Reverse the sense of the test.
-            not_b = filter(lambda x, b=b: x not in b, full)
-            return self.not_in_test(x, full, not_b)
-        return '%s in %s' % (x, `b`)
-    
-    def not_in_test(self, x, full, b):
-        if not b: return '1'
-        if len(b)==1: return '%s != %s' % (x, `b[0]`)
-        return '%s not in %s' % (x, `b`)
-
-    def peek_call(self, a):
-        a_set = (`a`[1:-1])
-        if self.equal_set(a, self.non_ignored_tokens()): a_set = ''
-        if self['context-insensitive-scanner']: a_set = ''
-        return 'self._peek(%s)' % a_set
-    
-    def peek_test(self, a, b):
-        if self.subset(a, b): return '1'
-        if self['context-insensitive-scanner']: a = self.non_ignored_tokens()
-        return self.in_test(self.peek_call(a), a, b)
-
-    def not_peek_test(self, a, b):
-        if self.subset(a, b): return '0'
-        return self.not_in_test(self.peek_call(a), a, b)
-
-    def calculate(self):
-        while 1:
-            for r in self.goals:
-                self.rules[r].setup(self, r)
-            if self.change_count == 0: break
-            self.change_count = 0
-
-        while 1:
-            for r in self.goals:
-                self.rules[r].update(self)                
-            if self.change_count == 0: break
-            self.change_count = 0
-
-    def dump_information(self):
-        self.calculate()
-        for r in self.goals:
-            print '    _____' + '_'*len(r)
-            print ('___/Rule '+r+'\\' + '_'*80)[:79]
-            queue = [self.rules[r]]
-            while queue:
-                top = queue[0]
-                del queue[0]
-
-                print `top`
-                top.first.sort()
-                top.follow.sort()
-                eps = []
-                if top.accepts_epsilon: eps = ['(null)']
-                print '     FIRST:', join(top.first+eps, ', ')
-                print '    FOLLOW:', join(top.follow, ', ')
-                for x in top.get_children(): queue.append(x)
-                
-    def generate_output(self):
-        self.calculate()
-        self.write(self.preparser)
-        self.write("from string import *\n")
-        self.write("import re\n")
-        self.write("from yappsrt import *\n")
-	self.write("\n")
-	self.write("class ", self.name, "Scanner(Scanner):\n")
-        self.write("    patterns = [\n")
-        for p in self.terminals:
-            self.write("        (%s, re.compile(%s)),\n" % (
-                `p`, `self.tokens[p]`))
-        self.write("    ]\n")
-	self.write("    def __init__(self, str):\n")
-	self.write("        Scanner.__init__(self,None,%s,str)\n" %
-                   `self.ignore`)
-	self.write("\n")
-        
-        self.write("class ", self.name, "(Parser):\n")
-        for r in self.goals:
-            self.write(INDENT, "def ", r, "(self")
-            if self.params[r]: self.write(", ", self.params[r])
-            self.write("):\n")
-            self.rules[r].output(self, INDENT+INDENT)
-            self.write("\n")
-
-        self.write("\n")
-        self.write("def parse(rule, text):\n")
-        self.write("    P = ", self.name, "(", self.name, "Scanner(text))\n")
-        self.write("    return wrap_error_reporter(P, rule)\n")
-        self.write("\n")
-        if self.postparser is not None:
-            self.write(self.postparser)
-        else:
-            self.write("if __name__=='__main__':\n")
-            self.write(INDENT, "from sys import argv, stdin\n")
-            self.write(INDENT, "if len(argv) >= 2:\n")
-            self.write(INDENT*2, "if len(argv) >= 3:\n")
-            self.write(INDENT*3, "f = open(argv[2],'r')\n")
-            self.write(INDENT*2, "else:\n")
-            self.write(INDENT*3, "f = stdin\n")
-            self.write(INDENT*2, "print parse(argv[1], f.read())\n")
-            self.write(INDENT, "else: print 'Args:  <rule> [<filename>]'\n")
-
-######################################################################
-class Node:
-    def __init__(self):
-        self.first = []
-        self.follow = []
-        self.accepts_epsilon = 0
-        self.rule = '?'
-        
-    def setup(self, gen, rule):
-        # Setup will change accepts_epsilon,
-        # sometimes from 0 to 1 but never 1 to 0.
-        # It will take a finite number of steps to set things up
-        self.rule = rule
-
-    def used(self, vars):
-        "Return two lists: one of vars used, and the other of vars assigned"
-        return vars, []
-
-    def get_children(self):
-        "Return a list of sub-nodes"
-        return []
-    
-    def __repr__(self):
-        return str(self)
-    
-    def update(self, gen):
-        if self.accepts_epsilon:
-            gen.add_to(self.first, self.follow)
-
-    def output(self, gen, indent):
-        "Write out code to _gen_ with _indent_:string indentation"
-        gen.write(indent, "assert 0 # Invalid parser node\n")
-    
-class Terminal(Node):
-    def __init__(self, token):
-        Node.__init__(self)
-        self.token = token
-        self.accepts_epsilon = 0
-
-    def __str__(self):
-        return self.token
-
-    def update(self, gen):
-        Node.update(self, gen)
-        if self.first != [self.token]:
-            self.first = [self.token]
-            gen.changed()
-
-    def output(self, gen, indent):
-        gen.write(indent)
-        if re.match('[a-zA-Z_]+$', self.token):
-            gen.write(self.token, " = ")
-        gen.write("self._scan(%s)\n" % `self.token`)
-        
-class Eval(Node):
-    def __init__(self, expr):
-        Node.__init__(self)
-        self.expr = expr
-
-    def setup(self, gen, rule):
-        Node.setup(self, gen, rule)
-        if not self.accepts_epsilon:
-            self.accepts_epsilon = 1
-            gen.changed()
-
-    def __str__(self):
-        return '{{ %s }}' % strip(self.expr)
-
-    def output(self, gen, indent):
-        gen.write(indent, strip(self.expr), '\n')
-        
-class NonTerminal(Node):
-    def __init__(self, name, args):
-        Node.__init__(self)
-        self.name = name
-        self.args = args
-
-    def setup(self, gen, rule):
-        Node.setup(self, gen, rule)
-        try:
-            self.target = gen.rules[self.name]
-            if self.accepts_epsilon != self.target.accepts_epsilon:
-                self.accepts_epsilon = self.target.accepts_epsilon
-                gen.changed()
-        except KeyError: # Oops, it's nonexistent
-            print 'Error: no rule <%s>' % self.name
-            self.target = self
-            
-    def __str__(self):
-        return '<%s>' % self.name
-
-    def update(self, gen):
-        Node.update(self, gen)
-        gen.equate(self.first, self.target.first)
-        gen.equate(self.follow, self.target.follow)
-
-    def output(self, gen, indent):
-        gen.write(indent)
-        gen.write(self.name, " = ")
-        gen.write("self.", self.name, "(", self.args, ")\n")
-        
-class Sequence(Node):
-    def __init__(self, *children):
-        Node.__init__(self)
-        self.children = children
-
-    def setup(self, gen, rule):
-        Node.setup(self, gen, rule)
-        for c in self.children: c.setup(gen, rule)
-        
-        if not self.accepts_epsilon:
-            # If it's not already accepting epsilon, it might now do so.
-            for c in self.children:
-                # any non-epsilon means all is non-epsilon
-                if not c.accepts_epsilon: break 
-            else:
-                self.accepts_epsilon = 1
-                gen.changed()
-
-    def get_children(self):
-        return self.children
-    
-    def __str__(self):
-        return '( %s )' % join(map(lambda x: str(x), self.children))
-
-    def update(self, gen):
-        Node.update(self, gen)
-        for g in self.children:
-            g.update(gen)
-
-        empty = 1
-        for g_i in range(len(self.children)):
-            g = self.children[g_i]
-            
-            if empty:  gen.add_to(self.first, g.first)
-            if not g.accepts_epsilon: empty = 0
-            
-            if g_i == len(self.children)-1: 
-                next = self.follow
-            else:
-                next = self.children[1+g_i].first
-            gen.add_to(g.follow, next)
-
-        if self.children:
-            gen.add_to(self.follow, self.children[-1].follow)
-
-    def output(self, gen, indent):
-        if self.children:
-            for c in self.children:
-                c.output(gen, indent)
-        else:
-            # Placeholder for empty sequences, just in case
-            gen.write(indent, 'pass\n')
-            
-class Choice(Node):
-    def __init__(self, *children):
-        Node.__init__(self)
-        self.children = children
-
-    def setup(self, gen, rule):
-        Node.setup(self, gen, rule)
-        for c in self.children: c.setup(gen, rule)
-            
-        if not self.accepts_epsilon:
-            for c in self.children:
-                if c.accepts_epsilon:
-                    self.accepts_epsilon = 1
-                    gen.changed()
-
-    def get_children(self):
-        return self.children
-    
-    def __str__(self):
-        return '( %s )' % join(map(lambda x: str(x), self.children), ' | ')
-
-    def update(self, gen):
-        Node.update(self, gen)
-        for g in self.children:
-            g.update(gen)
-
-        for g in self.children:
-            gen.add_to(self.first, g.first)
-            gen.add_to(self.follow, g.follow)
-        for g in self.children:
-            gen.add_to(g.follow, self.follow)
-        if self.accepts_epsilon:
-            gen.add_to(self.first, self.follow)
-
-    def output(self, gen, indent):
-        test = "if"
-        gen.write(indent, "_token_ = ", gen.peek_call(self.first), "\n")
-        tokens_seen = []
-        tokens_unseen = self.first[:]
-        if gen['context-insensitive-scanner']:
-            # Context insensitive scanners can return ANY token,
-            # not only the ones in first.
-            tokens_unseen = gen.non_ignored_tokens()
-        for c in self.children:
-            testset = c.first[:]
-            removed = []
-            for x in testset:
-                if x in tokens_seen:
-                    testset.remove(x)
-                    removed.append(x)
-                if x in tokens_unseen: tokens_unseen.remove(x)
-            tokens_seen = tokens_seen + testset
-            if removed:
-                if not testset:
-                    print 'Error in rule', self.rule+':', c, 'never matches.'
-                else:
-                    print 'Warning:', self
-                print ' * These tokens are being ignored:', join(removed, ', ')
-                print '   due to previous choices using them.'
-                
-            if testset:
-                if not tokens_unseen: # context sensitive scanners only!
-                    if test=='if':
-                        # if it's the first AND last test, then
-                        # we can simply put the code without an if/else
-                        c.output(gen, indent)
-                    else:
-                        gen.write(indent, "else: ")
-                        t = gen.in_test('', [], testset)
-                        if len(t) < 70-len(indent):
-                            gen.write("#", t)
-                        gen.write("\n")
-                        c.output(gen, indent+INDENT)
-                else:
-                    gen.write(indent, test, " ",
-                              gen.in_test('_token_', tokens_unseen, testset),
-                              ":\n")
-                    c.output(gen, indent+INDENT)
-                test = "elif"
-
-        if gen['context-insensitive-scanner'] and tokens_unseen:
-            gen.write(indent, "else:\n")
-            gen.write(indent, INDENT, "raise SyntaxError(self._pos, ")
-            gen.write("'Could not match ", self.rule, "')\n")
-
-class Wrapper(Node):
-    def __init__(self, child):
-        Node.__init__(self)
-        self.child = child
-
-    def setup(self, gen, rule):
-        Node.setup(self, gen, rule)
-        self.child.setup(gen, rule)
-
-    def get_children(self):
-        return [self.child]
-    
-    def update(self, gen):
-        Node.update(self, gen)
-        self.child.update(gen)
-        gen.add_to(self.first, self.child.first)
-        gen.equate(self.follow, self.child.follow)
-
-class Option(Wrapper):
-    def setup(self, gen, rule):
-        Wrapper.setup(self, gen, rule)
-        if not self.accepts_epsilon:
-            self.accepts_epsilon = 1
-            gen.changed()
-
-    def __str__(self):
-        return '[ %s ]' % str(self.child)
-
-    def output(self, gen, indent):
-        if self.child.accepts_epsilon:
-            print 'Warning in rule', self.rule+': contents may be empty.'
-        gen.write(indent, "if %s:\n" %
-                  gen.peek_test(self.first, self.child.first))
-        self.child.output(gen, indent+INDENT)
-        
-class Plus(Wrapper):
-    def setup(self, gen, rule):
-        Wrapper.setup(self, gen, rule)
-        if self.accepts_epsilon != self.child.accepts_epsilon:
-            self.accepts_epsilon = self.child.accepts_epsilon
-            gen.changed()
-
-    def __str__(self):
-        return '%s+' % str(self.child)
-
-    def update(self, gen):
-        Wrapper.update(self, gen)
-        gen.add_to(self.follow, self.first)
-
-    def output(self, gen, indent):
-        if self.child.accepts_epsilon:
-            print 'Warning in rule', self.rule+':'
-            print ' * The repeated pattern could be empty.  The resulting'
-            print '   parser may not work properly.'
-        gen.write(indent, "while 1:\n")
-        self.child.output(gen, indent+INDENT)
-        union = self.first[:]
-        gen.add_to(union, self.follow)
-        gen.write(indent+INDENT, "if %s: break\n" %
-                  gen.not_peek_test(union, self.child.first))
-
-class Star(Plus):
-    def setup(self, gen, rule):
-        Wrapper.setup(self, gen, rule)
-        if not self.accepts_epsilon:
-            self.accepts_epsilon = 1
-            gen.changed()
-
-    def __str__(self):
-        return '%s*' % str(self.child)
-
-    def output(self, gen, indent):
-        if self.child.accepts_epsilon:
-            print 'Warning in rule', self.rule+':'
-            print ' * The repeated pattern could be empty.  The resulting'
-            print '   parser probably will not work properly.'
-        gen.write(indent, "while %s:\n" %
-                  gen.peek_test(self.follow, self.child.first))
-        self.child.output(gen, indent+INDENT)
-
-######################################################################
-# The remainder of this file is from parsedesc.{g,py}
-
-def append(lst, x):
-    "Imperative append"
-    lst.append(x)
-    return lst
-
-def add_inline_token(tokens, str):
-    tokens.insert( 0, (str, eval(str, {}, {})) )
-    return Terminal(str)
-
-def cleanup_choice(lst):
-    if len(lst) == 0: return Sequence([])
-    if len(lst) == 1: return lst[0]
-    return apply(Choice, tuple(lst))
-
-def cleanup_sequence(lst):
-    if len(lst) == 1: return lst[0]
-    return apply(Sequence, tuple(lst))
-
-def cleanup_rep(node, rep):
-    if rep == 'star':   return Star(node)
-    elif rep == 'plus': return Plus(node)
-    else:               return node
-
-def resolve_name(tokens, id, args):
-    if id in map(lambda x: x[0], tokens):
-	# It's a token
-	if args: 
-	    print 'Warning: ignoring parameters on TOKEN %s<<%s>>' % (id, args)
-        return Terminal(id)
-    else:
-        # It's a name, so assume it's a nonterminal
-        return NonTerminal(id, args)
-
-
-from string import *
-import re
-from yappsrt import *
-
-class ParserDescriptionScanner(Scanner):
-    def __init__(self, str):
-        Scanner.__init__(self,[
-            ('"rule"', 'rule'),
-            ('"ignore"', 'ignore'),
-            ('"token"', 'token'),
-            ('"option"', 'option'),
-            ('":"', ':'),
-            ('"parser"', 'parser'),
-            ('[ \011\015\012]+', '[ \011\015\012]+'),
-            ('#.*?\015?\012', '#.*?\015?\012'),
-            ('END', '$'),
-            ('ATTR', '<<.+?>>'),
-            ('STMT', '{{.+?}}'),
-            ('ID', '[a-zA-Z_][a-zA-Z_0-9]*'),
-            ('STR', '[rR]?\'([^\\n\'\\\\]|\\\\.)*\'|[rR]?"([^\\n"\\\\]|\\\\.)*"'),
-            ('LP', '\\('),
-            ('RP', '\\)'),
-            ('LB', '\\['),
-            ('RB', '\\]'),
-            ('OR', '[|]'),
-            ('STAR', '[*]'),
-            ('PLUS', '[+]'),
-            ], ['[ \011\015\012]+', '#.*?\015?\012'], str)
-
-class ParserDescription(Parser):
-    def Parser(self):
-        self._scan('"parser"')
-        ID = self._scan('ID')
-        self._scan('":"')
-        Options = self.Options()
-        Tokens = self.Tokens()
-        Rules = self.Rules(Tokens)
-        END = self._scan('END')
-        return Generator(ID,Options,Tokens,Rules)
-
-    def Options(self):
-        opt = {}
-        while self._peek('"option"', '"token"', '"ignore"', 'END', '"rule"') == '"option"':
-            self._scan('"option"')
-            self._scan('":"')
-            Str = self.Str()
-            opt[Str] = 1
-        return opt
-
-    def Tokens(self):
-        tok = []
-        while self._peek('"token"', '"ignore"', 'END', '"rule"') in ['"token"', '"ignore"']:
-            _token_ = self._peek('"token"', '"ignore"')
-            if _token_ == '"token"':
-                self._scan('"token"')
-                ID = self._scan('ID')
-                self._scan('":"')
-                Str = self.Str()
-                tok.append( (ID,Str) )
-            else: # == '"ignore"'
-                self._scan('"ignore"')
-                self._scan('":"')
-                Str = self.Str()
-                tok.append( ('#ignore',Str) )
-        return tok
-
-    def Rules(self, tokens):
-        rul = []
-        while self._peek('"rule"', 'END') == '"rule"':
-            self._scan('"rule"')
-            ID = self._scan('ID')
-            OptParam = self.OptParam()
-            self._scan('":"')
-            ClauseA = self.ClauseA(tokens)
-            rul.append( (ID,OptParam,ClauseA) )
-        return rul
-
-    def ClauseA(self, tokens):
-        ClauseB = self.ClauseB(tokens)
-        v = [ClauseB]
-        while self._peek('OR', 'RP', 'RB', '"rule"', 'END') == 'OR':
-            OR = self._scan('OR')
-            ClauseB = self.ClauseB(tokens)
-            v.append(ClauseB)
-        return cleanup_choice(v)
-
-    def ClauseB(self, tokens):
-        v = []
-        while self._peek('STR', 'ID', 'LP', 'LB', 'STMT', 'OR', 'RP', 'RB', '"rule"', 'END') in ['STR', 'ID', 'LP', 'LB', 'STMT']:
-            ClauseC = self.ClauseC(tokens)
-            v.append(ClauseC)
-        return cleanup_sequence(v)
-
-    def ClauseC(self, tokens):
-        ClauseD = self.ClauseD(tokens)
-        _token_ = self._peek('PLUS', 'STAR', 'STR', 'ID', 'LP', 'LB', 'STMT', 'OR', 'RP', 'RB', '"rule"', 'END')
-        if _token_ == 'PLUS':
-            PLUS = self._scan('PLUS')
-            return Plus(ClauseD)
-        elif _token_ == 'STAR':
-            STAR = self._scan('STAR')
-            return Star(ClauseD)
-        else: 
-            return ClauseD
-
-    def ClauseD(self, tokens):
-        _token_ = self._peek('STR', 'ID', 'LP', 'LB', 'STMT')
-        if _token_ == 'STR':
-            STR = self._scan('STR')
-            t = (STR, eval(STR,{},{}))
-            if t not in tokens: tokens.insert( 0, t )
-            return Terminal(STR)
-        elif _token_ == 'ID':
-            ID = self._scan('ID')
-            OptParam = self.OptParam()
-            return resolve_name(tokens, ID, OptParam)
-        elif _token_ == 'LP':
-            LP = self._scan('LP')
-            ClauseA = self.ClauseA(tokens)
-            RP = self._scan('RP')
-            return ClauseA
-        elif _token_ == 'LB':
-            LB = self._scan('LB')
-            ClauseA = self.ClauseA(tokens)
-            RB = self._scan('RB')
-            return Option(ClauseA)
-        else: # == 'STMT'
-            STMT = self._scan('STMT')
-            return Eval(STMT[2:-2])
-
-    def OptParam(self):
-        if self._peek('ATTR', '":"', 'PLUS', 'STAR', 'STR', 'ID', 'LP', 'LB', 'STMT', 'OR', 'RP', 'RB', '"rule"', 'END') == 'ATTR':
-            ATTR = self._scan('ATTR')
-            return ATTR[2:-2]
-        return ''
-
-    def Str(self):
-        STR = self._scan('STR')
-        return eval(STR,{},{})
-
-
-
-
-
-# This replaces the default main routine
-
-yapps_options = [
-    ('context-insensitive-scanner', 'context-insensitive-scanner',
-     'Scan all tokens (see docs)')
-    ]
-
-def generate(inputfilename, outputfilename='', dump=0, **flags):
-    """Generate a grammar, given an input filename (X.g)
-    and an output filename (defaulting to X.py)."""
-
-    if not outputfilename:
-	if inputfilename[-2:]=='.g': outputfilename = inputfilename[:-2]+'.py'
-	else: raise "Invalid Filename", outputfilename
-        
-    print 'Input Grammar:', inputfilename
-    print 'Output File:', outputfilename
-    
-    DIVIDER = '\n%%\n' # This pattern separates the pre/post parsers
-    preparser, postparser = None, None # Code before and after the parser desc
-
-    # Read the entire file
-    s = open(inputfilename,'r').read()
-
-    # See if there's a separation between the pre-parser and parser
-    f = find(s, DIVIDER)
-    if f >= 0: preparser, s = s[:f]+'\n\n', s[f+len(DIVIDER):]
-
-    # See if there's a separation between the parser and post-parser
-    f = find(s, DIVIDER)
-    if f >= 0: s, postparser = s[:f], '\n\n'+s[f+len(DIVIDER):]
-
-    # Create the parser and scanner
-    p = ParserDescription(ParserDescriptionScanner(s))
-    if not p: return
-    
-    # Now parse the file
-    t = wrap_error_reporter(p, 'Parser')
-    if not t: return # Error
-    if preparser is not None: t.preparser = preparser
-    if postparser is not None: t.postparser = postparser
-
-    # Check the options
-    for f in t.options.keys():
-        for opt,_,_ in yapps_options:
-            if f == opt: break
-        else:
-            print 'Warning: unrecognized option', f
-    # Add command line options to the set
-    for f in flags.keys(): t.options[f] = flags[f]
-            
-    # Generate the output
-    if dump:
-        t.dump_information()
-    else:
-        t.output = open(outputfilename, 'w')
-        t.generate_output()
-
-if __name__=='__main__':
-    import sys, getopt
-    optlist, args = getopt.getopt(sys.argv[1:], 'f:', ['dump'])
-    if not args or len(args) > 2:
-        print 'Usage:'
-        print '  python', sys.argv[0], '[flags] input.g [output.py]'
-        print 'Flags:'
-        print ('  --dump' + ' '*40)[:35] + 'Dump out grammar information'
-        for flag, _, doc in yapps_options:
-            print ('  -f' + flag + ' '*40)[:35] + doc
-    else:
-        # Read in the options and create a list of flags
-	flags = {}
-	for opt in optlist:
-	    for flag, name, _ in yapps_options:
-		if opt == ('-f', flag):
-		    flags[name] = 1
-		    break
-	    else:
-                if opt == ('--dump', ''):
-                    flags['dump'] = 1
-		else:
-                    print 'Warning - unrecognized option:  ', opt[0], opt[1]
-
-        apply(generate, tuple(args), flags)
diff --git a/util/newconfig/yapps2.tex b/util/newconfig/yapps2.tex
deleted file mode 100644
index 9d2bddf..0000000
--- a/util/newconfig/yapps2.tex
+++ /dev/null
@@ -1,1225 +0,0 @@
-\documentclass[10pt]{article}
-\usepackage{palatino}
-\usepackage{html}
-\usepackage{color}
-
-\setlength{\headsep}{0in}
-\setlength{\headheight}{0in}
-\setlength{\textheight}{8.5in}
-\setlength{\textwidth}{5.9in}
-\setlength{\oddsidemargin}{0.25in}
-
-\definecolor{darkblue}{rgb}{0,0,0.6}
-\definecolor{darkerblue}{rgb}{0,0,0.3}
-
-%% \newcommand{\mysection}[1]{\section{\textcolor{darkblue}{#1}}}
-%% \newcommand{\mysubsection}[1]{\subsection{\textcolor{darkerblue}{#1}}}
-\newcommand{\mysection}[1]{\section{#1}}
-\newcommand{\mysubsection}[1]{\subsection{#1}}
-
-\bodytext{bgcolor=white text=black link=#004080 vlink=#006020}
-
-\newcommand{\first}{\textsc{first}}
-\newcommand{\follow}{\textsc{follow}}
-
-\begin{document}
-
-\begin{center}
-\hfill \begin{tabular}{c}
-{\Large The \emph{Yapps} Parser Generator System}\\
-\verb|http://theory.stanford.edu/~amitp/Yapps/|\\
-                Version 2\\
-\\
-Amit J. Patel\\
-\htmladdnormallink{http://www-cs-students.stanford.edu/~amitp/}
-{http://www-cs-students.stanford.edu/~amitp/}
-
-\end{tabular} \hfill \rule{0in}{0in}
-\end{center}
-
-\mysection{Introduction}
-
-\emph{Yapps} (\underline{Y}et \underline{A}nother \underline{P}ython
-\underline{P}arser \underline{S}ystem) is an easy to use parser
-generator that is written in Python and generates Python code.  There
-are several parser generator systems already available for Python,
-including \texttt{PyLR, kjParsing, PyBison,} and \texttt{mcf.pars,}
-but I had different goals for my parser.  Yapps is simple, is easy to
-use, and produces human-readable parsers.  It is not the fastest or
-most powerful parser.  Yapps is designed to be used when regular
-expressions are not enough and other parser systems are too much:
-situations where you may write your own recursive descent parser.
-
-Some unusual features of Yapps that may be of interest are:
-
-\begin{enumerate}
-   
- \item Yapps produces recursive descent parsers that are readable by
-   humans, as opposed to table-driven parsers that are difficult to
-   read.  A Yapps parser for a simple calculator looks similar to the
-   one that Mark Lutz wrote by hand for \emph{Programming Python.}
-        
- \item Yapps also allows for rules that accept parameters and pass
-   arguments to be used while parsing subexpressions.  Grammars that
-   allow for arguments to be passed to subrules and for values to be
-   passed back are often called \emph{attribute grammars.}  In many
-   cases parameterized rules can be used to perform actions at ``parse
-   time'' that are usually delayed until later.  For example,
-   information about variable declarations can be passed into the
-   rules that parse a procedure body, so that undefined variables can
-   be detected at parse time.  The types of defined variables can be
-   used in parsing as well---for example, if the type of {\tt X} is
-   known, we can determine whether {\tt X(1)} is an array reference or 
-   a function call.
-   
- \item Yapps grammars are fairly easy to write, although there are
-   some inconveniences having to do with ELL(1) parsing that have to be
-   worked around.  For example, rules have to be left factored and
-   rules may not be left recursive.  However, neither limitation seems 
-   to be a problem in practice.  
-   
-   Yapps grammars look similar to the notation used in the Python
-   reference manual, with operators like \verb:*:, \verb:+:, \verb:|:,
-   \verb:[]:, and \verb:(): for patterns, names ({\tt tim}) for rules,
-   regular expressions (\verb:"[a-z]+":) for tokens, and \verb:#: for
-   comments.
-
- \item The Yapps parser generator is written as a single Python module
-   with no C extensions.  Yapps produces parsers that are written
-   entirely in Python, and require only the Yapps run-time module (5k)
-   for support.
-   
- \item Yapps's scanner is context-sensitive, picking tokens based on
-   the types of the tokens accepted by the parser.  This can be
-   helpful when implementing certain kinds of parsers, such as for a
-   preprocessor.
-
-\end{enumerate}
-
-There are several disadvantages of using Yapps over another parser system:
-
-\begin{enumerate}
-   
- \item Yapps parsers are \texttt{ELL(1)} (Extended LL(1)), which is
-   less powerful than \texttt{LALR} (used by \texttt{PyLR}) or
-   \texttt{SLR} (used by \texttt{kjParsing}), so Yapps would not be a
-   good choice for parsing complex languages.  For example, allowing
-   both \texttt{x := 5;} and \texttt{x;} as statements is difficult
-   because we must distinguish based on only one token of lookahead.
-   Seeing only \texttt{x}, we cannot decide whether we have an
-   assignment statement or an expression statement.  (Note however
-   that this kind of grammar can be matched with backtracking; see
-   section \ref{sec:future}.)
-
- \item The scanner that Yapps provides can only read from strings, not
-   files, so an entire file has to be read in before scanning can
-   begin.  It is possible to build a custom scanner, though, so in
-   cases where stream input is needed (from the console, a network, or
-   a large file are examples), the Yapps parser can be given a custom
-   scanner that reads from a stream instead of a string.
-   
- \item Yapps is not designed with efficiency in mind.
-
-\end{enumerate}
-
-Yapps provides an easy to use parser generator that produces parsers
-similar to what you might write by hand.  It is not meant to be a
-solution for all parsing problems, but instead an aid for those times
-you would write a parser by hand rather than using one of the more
-powerful parsing packages available.
-
-Yapps 2.0 is easier to use than Yapps 1.0.  New features include a
-less restrictive input syntax, which allows mixing of sequences,
-choices, terminals, and nonterminals; optional matching; the ability
-to insert single-line statements into the generated parser; and
-looping constructs \verb|*| and \verb|+| similar to the repetitive
-matching constructs in regular expressions.  Unfortunately, the
-addition of these constructs has made Yapps 2.0 incompatible with
-Yapps 1.0, so grammars will have to be rewritten.  See section
-\ref{sec:Upgrading} for tips on changing Yapps 1.0 grammars for use
-with Yapps 2.0.
-
-\mysection{Examples}
-
-In this section are several examples that show the use of Yapps.
-First, an introduction shows how to construct grammars and write them
-in Yapps form.  This example can be skipped by someone familiar with
-grammars and parsing.  Next is a Lisp expression grammar that produces
-a parse tree as output.  This example demonstrates the use of tokens
-and rules, as well as returning values from rules.  The third example
-is a expression evaluation grammar that evaluates during parsing
-(instead of producing a parse tree).
-
-\mysubsection{Introduction to Grammars}
-
-A \emph{grammar} for a natural language specifies how words can be put
-together to form large structures, such as phrases and sentences.  A
-grammar for a computer language is similar in that it specifies how
-small components (called \emph{tokens}) can be put together to form
-larger structures.  In this section we will write a grammar for a tiny
-subset of English.
-
-Simple English sentences can be described as being a noun phrase
-followed by a verb followed by a noun phrase.  For example, in the
-sentence, ``Jack sank the blue ship,'' the word ``Jack'' is the first
-noun phrase, ``sank'' is the verb, and ``the blue ship'' is the second
-noun phrase.  In addition we should say what a noun phrase is; for
-this example we shall say that a noun phrase is an optional article
-(a, an, the) followed by any number of adjectives followed by a noun.
-The tokens in our language are the articles, nouns, verbs, and
-adjectives.  The \emph{rules} in our language will tell us how to
-combine the tokens together to form lists of adjectives, noun phrases,
-and sentences:
-
-\begin{itemize}
-  \item \texttt{sentence: noun\_phrase verb noun\_phrase}
-  \item \texttt{noun\_phrase: [article] adjective* noun}
-\end{itemize}
-
-Notice that some things that we said easily in English, such as
-``optional article,'' are expressed using special syntax, such as
-brackets.  When we said, ``any number of adjectives,'' we wrote
-\texttt{adjective*}, where the \texttt{*} means ``zero or more of the
-preceding pattern''.
-
-The grammar given above is close to a Yapps grammar.  We also have to
-specify what the tokens are, and what to do when a pattern is matched.
-For this example, we will do nothing when patterns are matched; the
-next example will explain how to perform match actions.
-
-\begin{verbatim}
-parser TinyEnglish:
-  ignore:          "\\W+"
-  token noun:      "(Jack|spam|ship)"
-  token verb:      "(sank|threw)"
-  token article:   "(a|an|the)"
-  token adjective: "(blue|red|green)"
-
-  rule sentence:       noun_phrase verb noun_phrase
-  rule noun_phrase:    [article] adjective* noun
-\end{verbatim}
-
-The tokens are specified as Python \emph{regular expressions}.  Since
-Yapps produces Python code, you can write any regular expression that
-would be accepted by Python.  (\emph{Note:} These are Python 1.5
-regular expressions from the \texttt{re} module, not Python 1.4
-regular expressions from the \texttt{regex} module.)  In addition to
-tokens that you want to see (which are given names), you can also
-specify tokens to ignore, marked by the \texttt{ignore} keyword.  In
-this parser we want to ignore whitespace.
-
-The TinyEnglish grammar shows how you define tokens and rules, but it
-does not specify what should happen once we've matched the rules.  In
-the next example, we will take a grammar and produce a \emph{parse
-tree} from it.
-
-\mysubsection{Lisp Expressions}
-
-Lisp syntax, although hated by many, has a redeeming quality: it is
-simple to parse.  In this section we will construct a Yapps grammar to
-parse Lisp expressions and produce a parse tree as output.
-
-\subsubsection*{Defining the Grammar}
-
-The syntax of Lisp is simple.  It has expressions, which are
-identifiers, strings, numbers, and lists.  A list is a left
-parenthesis followed by some number of expressions (separated by
-spaces) followed by a right parenthesis.  For example, \verb|5|,
-\verb|"ni"|, and \verb|(print "1+2 = " (+ 1 2))| are Lisp expressions.
-Written as a grammar,
-
-\begin{verbatim}
-    expr:   ID | STR | NUM | list
-    list:   ( expr* )  
-\end{verbatim}
-
-In addition to having a grammar, we need to specify what to do every
-time something is matched.  For the tokens, which are strings, we just
-want to get the ``value'' of the token, attach its type (identifier,
-string, or number) in some way, and return it.  For the lists, we want
-to construct and return a Python list.
-
-Once some pattern is matched, we enclose a return statement enclosed
-in \verb|{{...}}|.  The braces allow us to insert any one-line
-statement into the parser.  Within this statement, we can refer to the
-values returned by matching each part of the rule.  After matching a
-token such as \texttt{ID}, ``ID'' will be bound to the text of the
-matched token.  Let's take a look at the rule:
-
-\begin{verbatim}
-    rule expr: ID   {{ return ('id', ID) }}
-      ...
-\end{verbatim}
-
-In a rule, tokens return the text that was matched.  For identifiers,
-we just return the identifier, along with a ``tag'' telling us that
-this is an identifier and not a string or some other value.  Sometimes
-we may need to convert this text to a different form.  For example, if
-a string is matched, we want to remove quotes and handle special forms
-like \verb|\n|.  If a number is matched, we want to convert it into a
-number.  Let's look at the return values for the other tokens:
-
-\begin{verbatim}
-      ...
-             | STR  {{ return ('str', eval(STR)) }}
-             | NUM  {{ return ('num', atoi(NUM)) }}
-      ...
-\end{verbatim}
-
-If we get a string, we want to remove the quotes and process any
-special backslash codes, so we run \texttt{eval} on the quoted string.
-If we get a number, we convert it to an integer with \texttt{atoi} and
-then return the number along with its type tag.
-
-For matching a list, we need to do something slightly more
-complicated.  If we match a Lisp list of expressions, we want to
-create a Python list with those values.
-
-\begin{verbatim}
-    rule list: "\\("                 # Match the opening parenthesis
-               {{ result = [] }}     # Create a Python list
-               ( 
-                  expr               # When we match an expression,
-                  {{ result.append(expr) }}   # add it to the list
-               )*                    # * means repeat this if needed
-               "\\)"                 # Match the closing parenthesis
-               {{ return result }}   # Return the Python list
-\end{verbatim}
-
-In this rule we first match the opening parenthesis, then go into a
-loop.  In this loop we match expressions and add them to the list.
-When there are no more expressions to match, we match the closing
-parenthesis and return the resulting.  Note that \verb:#: is used for
-comments, just as in Python.
-
-The complete grammar is specified as follows:
-\begin{verbatim}
-parser Lisp:
-    ignore:      '\\s+'
-    token NUM:   '[0-9]+'
-    token ID:    '[-+*/!@%^&=.a-zA-Z0-9_]+' 
-    token STR:   '"([^\\"]+|\\\\.)*"'
-
-    rule expr:   ID     {{ return ('id', ID) }}
-               | STR    {{ return ('str', eval(STR)) }}
-               | NUM    {{ return ('num', atoi(NUM)) }}
-               | list   {{ return list }}
-    rule list: "\\("    {{ result = [] }} 
-               ( expr   {{ result.append(expr) }}
-               )*  
-               "\\)"    {{ return result }} 
-\end{verbatim}
-
-One thing you may have noticed is that \verb|"\\("| and \verb|"\\)"|
-appear in the \texttt{list} rule.  These are \emph{inline tokens}:
-they appear in the rules without being given a name with the
-\texttt{token} keyword.  Inline tokens are more convenient to use, but
-since they do not have a name, the text that is matched cannot be used
-in the return value.  They are best used for short simple patterns
-(usually punctuation or keywords).
-
-Another thing to notice is that the number and identifier tokens
-overlap.  For example, ``487'' matches both NUM and ID.  In Yapps, the
-scanner only tries to match tokens that are acceptable to the parser.
-This rule doesn't help here, since both NUM and ID can appear in the
-same place in the grammar.  There are two rules used to pick tokens if
-more than one matches.  One is that the \emph{longest} match is
-preferred.  For example, ``487x'' will match as an ID (487x) rather
-than as a NUM (487) followed by an ID (x).  The second rule is that if
-the two matches are the same length, the \emph{first} one listed in
-the grammar is preferred.  For example, ``487'' will match as an NUM
-rather than an ID because NUM is listed first in the grammar.  Inline
-tokens have preference over any tokens you have listed.
-
-Now that our grammar is defined, we can run Yapps to produce a parser,
-and then run the parser to produce a parse tree.
-
-\subsubsection*{Running Yapps}
-
-In the Yapps module is a function \texttt{generate} that takes an
-input filename and writes a parser to another file.  We can use this
-function to generate the Lisp parser, which is assumed to be in
-\texttt{lisp.g}.
-
-\begin{verbatim}
-% python
-Python 1.5.1 (#1, Sep  3 1998, 22:51:17)  [GCC 2.7.2.3] on linux-i386
-Copyright 1991-1995 Stichting Mathematisch Centrum, Amsterdam
->>> import yapps
->>> yapps.generate('lisp.g')
-\end{verbatim}
-
-At this point, Yapps has written a file \texttt{lisp.py} that contains
-the parser.  In that file are two classes (one scanner and one parser)
-and a function (called \texttt{parse}) that puts things together for
-you.
-
-Alternatively, we can run Yapps from the command line to generate the
-parser file:
-
-\begin{verbatim}
-% python yapps.py lisp.g
-\end{verbatim}
-
-After running Yapps either from within Python or from the command
-line, we can use the Lisp parser by calling the \texttt{parse}
-function.  The first parameter should be the rule we want to match,
-and the second parameter should be the string to parse.
-
-\begin{verbatim}
->>> import lisp
->>> lisp.parse('expr', '(+ 3 4)')
-[('id', '+'), ('num', 3), ('num', 4)]
->>> lisp.parse('expr', '(print "3 = " (+ 1 2))')
-[('id', 'print'), ('str', '3 = '), [('id', '+'), ('num', 1), ('num', 2)]]
-\end{verbatim}
-
-The \texttt{parse} function is not the only way to use the parser;
-section \ref{sec:Parser-Objects} describes how to access parser objects
-directly.
-
-We've now gone through the steps in creating a grammar, writing a
-grammar file for Yapps, producing a parser, and using the parser.  In
-the next example we'll see how rules can take parameters and also how
-to do computations instead of just returning a parse tree.
-
-\mysubsection{Calculator}
-
-A common example parser given in many textbooks is that for simple
-expressions, with numbers, addition, subtraction, multiplication,
-division, and parenthesization of subexpressions.  We'll write this
-example in Yapps, evaluating the expression as we parse.
-
-Unlike \texttt{yacc}, Yapps does not have any way to specify
-precedence rules, so we have to do it ourselves.  We say that an
-expression is the sum of terms, and that a term is the product of
-factors, and that a factor is a number or a parenthesized expression:
-
-\begin{verbatim}
-    expr:           factor ( ("+"|"-") factor )*
-    factor:         term   ( ("*"|"/") term )*
-    term:           NUM | "(" expr ")"
-\end{verbatim}
-
-In order to evaluate the expression as we go, we should keep along an
-accumulator while evaluating the lists of terms or factors.  Just as
-we kept a ``result'' variable to build a parse tree for Lisp
-expressions, we will use a variable to evaluate numerical
-expressions.  The full grammar is given below:
-
-\begin{verbatim}
-parser Calculator:
-    token END: "$"         # $ means end of string
-    token NUM: "[0-9]+"
-
-    rule goal:           expr END         {{ return expr }}
-
-    # An expression is the sum and difference of factors
-    rule expr:           factor           {{ v = factor }}
-                       ( "[+]" factor       {{ v = v+factor }}
-                       |  "-"  factor       {{ v = v-factor }}
-                       )*                 {{ return v }}
-
-    # A factor is the product and division of terms
-    rule factor:         term             {{ v = term }}
-                       ( "[*]" term         {{ v = v*term }}
-                       |  "/"  term         {{ v = v/term }}
-                       )*                 {{ return v }}
-
-    # A term is either a number or an expression surrounded by parentheses
-    rule term:           NUM              {{ return atoi(NUM) }}
-                       | "\\(" expr "\\)" {{ return expr }}
-\end{verbatim}
-
-The top-level rule is \emph{goal}, which says that we are looking for
-an expression followed by the end of the string.  The \texttt{END}
-token is needed because without it, it isn't clear when to stop
-parsing.  For example, the string ``1+3'' could be parsed either as
-the expression ``1'' followed by the string ``+3'' or it could be
-parsed as the expression ``1+3''.  By requiring expressions to end
-with \texttt{END}, the parser is forced to take ``1+3''.
-
-In the two rules with repetition, the accumulator is named \texttt{v}.
-After reading in one expression, we initialize the accumulator.  Each
-time through the loop, we modify the accumulator by adding,
-subtracting, multiplying by, or dividing the previous accumulator by
-the expression that has been parsed.  At the end of the rule, we
-return the accumulator.
-
-The calculator example shows how to process lists of elements using
-loops, as well as how to handle precedence of operators.
-
-\emph{Note:} It's often important to put the \texttt{END} token in, so 
-put it in unless you are sure that your grammar has some other
-non-ambiguous token marking the end of the program.
-
-\mysubsection{Calculator with Memory}
-
-In the previous example we learned how to write a calculator that
-evaluates simple numerical expressions.  In this section we will
-extend the example to support both local and global variables.
-
-To support global variables, we will add assignment statements to the
-``goal'' rule.
-
-\begin{verbatim}
-    rule goal:           expr END         {{ return expr }}
-              | 'set' ID expr END         {{ global_vars[ID] = expr }}
-                                          {{ return expr }}   
-\end{verbatim}
-
-To use these variables, we need a new kind of terminal:
-
-\begin{verbatim}
-    rule term: ... | ID {{ return global_vars[ID] }} 
-\end{verbatim}
-
-So far, these changes are straightforward.  We simply have a global
-dictionary \texttt{global\_vars} that stores the variables and values, 
-we modify it when there is an assignment statement, and we look up
-variables in it when we see a variable name.
-
-To support local variables, we will add variable declarations to the
-set of allowed expressions.
-
-\begin{verbatim}
-    rule term: ... | 'let' VAR '=' expr 'in' expr ...
-\end{verbatim}
-
-This is where it becomes tricky.  Local variables should be stored in
-a local dictionary, not in the global one.  One trick would be to save 
-a copy of the global dictionary, modify it, and then restore it
-later.  In this example we will instead use \emph{attributes} to
-create local information and pass it to subrules.
-
-A rule can optionally take parameters.  When we invoke the rule, we
-must pass in arguments.  For local variables, let's use a single
-parameter, \texttt{local\_vars}:
-
-\begin{verbatim}
-    rule expr<<local_vars>>:   ...
-    rule factor<<local_vars>>: ...
-    rule term<<local_vars>>:   ...
-\end{verbatim}
-
-Each time we want to match \texttt{expr}, \texttt{factor}, or
-\texttt{term}, we will pass the local variables in the current rule to
-the subrule.  One interesting case is when we pass as an argument
-something \emph{other} than \texttt{local\_vars}:
-
-\begin{verbatim}
-   rule term<<local_vars>>: ...
-                | 'let' VAR '=' expr<<local_vars>>
-                  {{ local_vars = [(VAR, expr)] + local_vars }}
-                  'in' expr<<local_vars>>
-                  {{ return expr }}
-\end{verbatim}
-
-Note that the assignment to the local variables list does not modify
-the original list.  This is important to keep local variables from
-being seen outside the ``let''.
-
-The other interesting case is when we find a variable:
-
-\begin{verbatim}
-global_vars = {}
-
-def lookup(map, name):
-    for x,v in map:  if x==name: return v
-    return global_vars[name]
-%%
-   ...
-   rule term<<local_vars>: ...
-                | VAR {{ return lookup(local_vars, VAR) }}
-\end{verbatim}
-
-The lookup function will search through the local variable list, and
-if it cannot find the name there, it will look it up in the global
-variable dictionary.
-
-A complete grammar for this example, including a read-eval-print loop
-for interacting with the calculator, can be found in the examples
-subdirectory included with Yapps.
-
-In this section we saw how to insert code before the parser.  We also
-saw how to use attributes to transmit local information from one rule
-to its subrules.
-
-\mysection{Grammars}
-
-Each Yapps grammar has a name, a list of tokens, and a set of
-production rules.  A grammar named \texttt{X} will be used to produce
-a parser named \texttt{X} and a scanner anmed \texttt{XScanner}.  As
-in Python, names are case sensitive, start with a letter, and contain
-letters, numbers, and underscores (\_).
-
-There are three kinds of tokens in Yapps: named, inline, and ignored.
-As their name implies, named tokens are given a name, using the token
-construct: \texttt{token \emph{name} : \emph{regexp}}.  In a rule, the
-token can be matched by using the name.  Inline tokens are regular
-expressions that are used in rules without being declared.  Ignored
-tokens are declared using the ignore construct: \texttt{ignore:
-  \emph{regexp}}.  These tokens are ignored by the scanner, and are
-not seen by the parser.  Often whitespace is an ignored token.  The
-regular expressions used to define tokens should use the syntax
-defined in the \texttt{re} module, so some symbols may have to be
-backslashed.
-
-Production rules in Yapps have a name and a pattern to match.  If the
-rule is parameterized, the name should be followed by a list of
-parameter names in \verb|<<...>>|.  A pattern can be a simple pattern
-or a compound pattern.  Simple patterns are the name of a named token,
-a regular expression in quotes (inline token), the name of a
-production rule (followed by arguments in \verb|<<...>>|, if the rule
-has parameters), and single line Python statements (\verb|{{...}}|).
-Compound patterns are sequences (\verb|A B C ...|), choices (
-\verb:A | B | C | ...:), options (\verb|[...]|), zero-or-more repetitions
-(\verb|...*|), and one-or-more repetitions (\verb|...+|).  Like
-regular expressions, repetition operators have a higher precedence
-than sequences, and sequences have a higher precedence than choices.
-
-Whenever \verb|{{...}}| is used, a legal one-line Python statement
-should be put inside the braces.  The token \verb|}}| should not
-appear within the \verb|{{...}}| section, even within a string, since
-Yapps does not attempt to parse the Python statement.  A workaround
-for strings is to put two strings together (\verb|"}" "}"|), or to use
-backslashes (\verb|"}\}"|).  At the end of a rule you should use a
-\verb|{{ return X }}| statement to return a value.  However, you
-should \emph{not} use any control statements (\texttt{return},
-\texttt{continue}, \texttt{break}) in the middle of a rule.  Yapps
-needs to make assumptions about the control flow to generate a parser,
-and any changes to the control flow will confuse Yapps.
-
-The \verb|<<...>>| form can occur in two places: to define parameters
-to a rule and to give arguments when matching a rule.  Parameters use
-the syntax used for Python functions, so they can include default
-arguments and the special forms (\verb|*args| and \verb|**kwargs|).
-Arguments use the syntax for Python function call arguments, so they
-can include normal arguments and keyword arguments.  The token
-\verb|>>| should not appear within the \verb|<<...>>| section.
-
-In both the statements and rule arguments, you can use names defined
-by the parser to refer to matched patterns.  You can refer to the text
-matched by a named token by using the token name.  You can use the
-value returned by a production rule by using the name of that rule.
-If a name \texttt{X} is matched more than once (such as in loops), you
-will have to save the earlier value(s) in a temporary variable, and
-then use that temporary variable in the return value.  The next
-section has an example of a name that occurs more than once.
-
-\mysubsection{Left Factoring}
-\label{sec:Left-Factoring}
-
-Yapps produces ELL(1) parsers, which determine which clause to match
-based on the first token available.  Sometimes the leftmost tokens of
-several clauses may be the same.  The classic example is the
-\emph{if/then/else} construct in Pascal:
-
-\begin{verbatim}
-rule stmt:  "if" expr "then" stmt {{ then_part = stmt }} 
-                      "else" stmt {{ return ('If',expr,then_part,stmt) }}
-          | "if" expr "then" stmt {{ return ('If',expr,stmt,[]) }}
-\end{verbatim}
-
-(Note that we have to save the first \texttt{stmt} into a variable
-because there is another \texttt{stmt} that will be matched.)  The
-left portions of the two clauses are the same, which presents a
-problem for the parser.  The solution is \emph{left-factoring}: the
-common parts are put together, and \emph{then} a choice is made about
-the remaining part:
-
-\begin{verbatim}
-rule stmt:  "if" expr 
-              "then" stmt {{ then_part = stmt }}
-              {{ else_part = [] }}
-              [ "else" stmt {{ else_part = stmt }} ]
-            {{ return ('If', expr, then_part, else_part) }}
-\end{verbatim}
-
-Unfortunately, the classic \emph{if/then/else} situation is
-\emph{still} ambiguous when you left-factor.  Yapps can deal with this
-situation, but will report a warning; see section
-\ref{sec:Ambiguous-Grammars} for details.
-
-In general, replace rules of the form:
-
-\begin{verbatim}
-rule A:   a b1 {{ return E1 }}
-        | a b2 {{ return E2 }}
-        | c3   {{ return E3 }}
-        | c4   {{ return E4 }}
-\end{verbatim}
-
-with rules of the form:
-
-\begin{verbatim}
-rule A:   a ( b1 {{ return E1 }}
-            | b2 {{ return E2 }}
-            )
-        | c3   {{ return E3 }}
-        | c4   {{ return E4 }}
-\end{verbatim}
-
-\mysubsection{Left Recursion}
-
-A common construct in grammars is for matching a list of patterns,
-sometimes separated with delimiters such as commas or semicolons.  In
-LR-based parser systems, we can parse a list with something like this:
-
-\begin{verbatim}
-rule sum:  NUM             {{ return NUM }}
-         | sum "+" NUM     {{ return (sum, NUM) }}
-\end{verbatim}
-
-Parsing \texttt{1+2+3+4} would produce the output
-\texttt{(((1,2),3),4)}, which is what we want from a left-associative
-addition operator.  Unfortunately, this grammar is \emph{left
-recursive,} because the \texttt{sum} rule contains a clause that
-begins with \texttt{sum}.  (The recursion occurs at the left side of
-the clause.)
-
-We must restructure this grammar to be \emph{right recursive} instead:
-
-\begin{verbatim}
-rule sum:  NUM             {{ return NUM }}
-         | NUM "+" sum     {{ return (NUM, sum) }}
-\end{verbatim}
-
-Unfortunately, using this grammar, \texttt{1+2+3+4} would be parsed as
-\texttt{(1,(2,(3,4)))}, which no longer follows left associativity.
-The rule also needs to be left-factored.  Instead, we write the
-pattern as a loop instead:
-
-\begin{verbatim}
-rule sum:       NUM {{ v = NUM }}
-                ( "[+]" NUM {{ v = (v,NUM) }} )*
-                {{ return v }}
-\end{verbatim}
-
-In general, replace rules of the form:
-
-\begin{verbatim}
-rule A:  A a1 -> << E1 >> 
-       | A a2 -> << E2 >>
-       | b3   -> << E3 >>
-       | b4   -> << E4 >>
-\end{verbatim}
-
-with rules of the form:
-
-\begin{verbatim}
-rule A:  ( b3 {{ A = E3 }} 
-         | b4 {{ A = E4 }} )
-         ( a1 {{ A = E1 }}
-         | a2 {{ A = E2 }} )*
-         {{ return A }}
-\end{verbatim}
-
-We have taken a rule that proved problematic for with recursion and
-turned it into a rule that works well with looping constructs.
-
-\mysubsection{Ambiguous Grammars}
-\label{sec:Ambiguous-Grammars}
-
-In section \ref{sec:Left-Factoring} we saw the classic if/then/else
-ambiguity, which occurs because the ``else \ldots'' portion of an ``if
-\ldots then \ldots else \ldots'' construct is optional.  Programs with 
-nested if/then/else constructs can be ambiguous when one of the else
-clauses is missing:
-\begin{verbatim}
-if 1 then            if 1 then
-    if 5 then            if 5 then
-        x := 1;              x := 1;
-    else             else
-        y := 9;          y := 9;
-\end{verbatim}
-
-The indentation shows that the program can be parsed in two different
-ways.  (Of course, if we all would adopt Python's indentation-based
-structuring, this would never happen!)  Usually we want the parsing on
-the left: the ``else'' should be associated with the closest ``if''
-statement.  In section \ref{sec:Left-Factoring} we ``solved'' the
-problem by using the following grammar:
-
-\begin{verbatim}
-rule stmt:  "if" expr 
-              "then" stmt {{ then_part = stmt }}
-              {{ else_part = [] }}
-              [ "else" stmt {{ else_part = stmt }} ]
-            {{ return ('If', expr, then_part, else_part) }}
-\end{verbatim}
-
-Here, we have an optional match of ``else'' followed by a statement.
-The ambiguity is that if an ``else'' is present, it is not clear
-whether you want it parsed immediately or if you want it to be parsed
-by the outer ``if''.
-
-Yapps will deal with the situation by matching when the else pattern
-when it can.  The parser will work in this case because it prefers the
-\emph{first} matching clause, which tells Yapps to parse the ``else''.
-That is exactly what we want!
-
-For ambiguity cases with choices, Yapps will choose the \emph{first}
-matching choice.  However, remember that Yapps only looks at the first 
-token to determine its decision, so {\tt (a b | a c)} will result in
-Yapps choosing {\tt a b} even when the input is {\tt a c}.  It only
-looks at the first token, {\tt a}, to make its decision.
-
-\mysection{Customization}
-
-Both the parsers and the scanners can be customized.  The parser is
-usually extended by subclassing, and the scanner can either be
-subclassed or completely replaced.
-
-\mysubsection{Customizing Parsers}
-
-If additional fields and methods are needed in order for a parser to
-work, Python subclassing can be used.  (This is unlike parser classes
-written in static languages, in which these fields and methods must be
-defined in the generated parser class.)  We simply subclass the
-generated parser, and add any fields or methods required.  Expressions
-in the grammar can call methods of the subclass to perform any actions
-that cannot be expressed as a simple expression.  For example,
-consider this simple grammar:
-
-\begin{verbatim}
-parser X:
-    rule goal:  "something"  {{ self.printmsg() }}
-\end{verbatim}
-
-The \texttt{printmsg} function need not be implemented in the parser
-class \texttt{X}; it can be implemented in a subclass:
-
-\begin{verbatim}
-import Xparser
-
-class MyX(Xparser.X):
-    def printmsg(self):
-        print "Hello!"
-\end{verbatim}
-
-\mysubsection{Customizing Scanners}
-
-The generated parser class is not dependent on the generated scanner
-class.  A scanner object is passed to the parser object's constructor
-in the \texttt{parse} function.  To use a different scanner, write
-your own function to construct parser objects, with an instance of a
-different scanner.  Scanner objects must have a \texttt{token} method
-that accepts an integer \texttt{N} as well as a list of allowed token
-types, and returns the Nth token, as a tuple.  The default scanner
-raises \texttt{NoMoreTokens} if no tokens are available, and
-\texttt{SyntaxError} if no token could be matched.  However, the
-parser does not rely on these exceptions; only the \texttt{parse}
-convenience function (which calls \texttt{wrap\_error\_reporter}) and
-the \texttt{print\_error} error display function use those exceptions.
-
-The tuples representing tokens have four elements.  The first two are
-the beginning and ending indices of the matched text in the input
-string.  The third element is the type tag, matching either the name
-of a named token or the quoted regexp of an inline or ignored token.
-The fourth element of the token tuple is the matched text.  If the
-input string is \texttt{s}, and the token tuple is
-\texttt{(b,e,type,val)}, then \texttt{val} should be equal to
-\texttt{s[b:e]}.
-
-The generated parsers do not the beginning or ending index.  They use
-only the token type and value.  However, the default error reporter
-uses the beginning and ending index to show the user where the error
-is.
-
-\mysection{Parser Mechanics}
-
-The base parser class (Parser) defines two methods, \texttt{\_scan}
-and \texttt{\_peek}, and two fields, \texttt{\_pos} and
-\texttt{\_scanner}.  The generated parser inherits from the base
-parser, and contains one method for each rule in the grammar.  To
-avoid name clashes, do not use names that begin with an underscore
-(\texttt{\_}).
-
-\mysubsection{Parser Objects}
-\label{sec:Parser-Objects}
-
-Yapps produces as output two exception classes, a scanner class, a
-parser class, and a function \texttt{parse} that puts everything
-together.  The \texttt{parse} function does not have to be used;
-instead, one can create a parser and scanner object and use them
-together for parsing.
-
-\begin{verbatim}
-    def parse(rule, text):
-        P = X(XScanner(text))
-        return wrap_error_reporter(P, rule)
-\end{verbatim}
-
-The \texttt{parse} function takes a name of a rule and an input string
-as input.  It creates a scanner and parser object, then calls
-\texttt{wrap\_error\_reporter} to execute the method in the parser
-object named \texttt{rule}.  The wrapper function will call the
-appropriate parser rule and report any parsing errors to standard
-output.
-
-There are several situations in which the \texttt{parse} function
-would not be useful.  If a different parser or scanner is being used,
-or exceptions are to be handled differently, a new \texttt{parse}
-function would be required.  The supplied \texttt{parse} function can
-be used as a template for writing a function for your own needs.  An
-example of a custom parse function is the \texttt{generate} function
-in \texttt{Yapps.py}.
-
-\mysubsection{Context Sensitive Scanner}
-
-Unlike most scanners, the scanner produced by Yapps can take into
-account the context in which tokens are needed, and try to match only
-good tokens.  For example, in the grammar:
-
-\begin{verbatim}
-parser IniFile:
-   token ID:   "[a-zA-Z_0-9]+"
-   token VAL:  ".*"
-
-   rule pair:  ID "[ \t]*=[ \t]*" VAL "\n"
-\end{verbatim}
-
-we would like to scan lines of text and pick out a name/value pair.
-In a conventional scanner, the input string \texttt{shell=progman.exe}
-would be turned into a single token of type \texttt{VAL}.  The Yapps
-scanner, however, knows that at the beginning of the line, an
-\texttt{ID} is expected, so it will return \texttt{"shell"} as a token
-of type \texttt{ID}.  Later, it will return \texttt{"progman.exe"} as
-a token of type \texttt{VAL}.
-
-Context sensitivity decreases the separation between scanner and
-parser, but it is useful in parsers like \texttt{IniFile}, where the
-tokens themselves are not unambiguous, but \emph{are} unambiguous
-given a particular stage in the parsing process.
-
-Unfortunately, context sensitivity can make it more difficult to
-detect errors in the input.  For example, in parsing a Pascal-like
-language with ``begin'' and ``end'' as keywords, a context sensitive
-scanner would only match ``end'' as the END token if the parser is in
-a place that will accept the END token.  If not, then the scanner
-would match ``end'' as an identifier.  To disable the context
-sensitive scanner in Yapps, add the
-\texttt{context-insensitive-scanner} option to the grammar:
-
-\begin{verbatim}
-Parser X:
-    option:  "context-insensitive-scanner"
-\end{verbatim}
-
-Context-insensitive scanning makes the parser look cleaner as well.
-
-\mysubsection{Internal Variables}
-
-There are two internal fields that may be of use.  The parser object
-has two fields, \texttt{\_pos}, which is the index of the current
-token being matched, and \texttt{\_scanner}, which is the scanner
-object.  The token itself can be retrieved by accessing the scanner
-object and calling the \texttt{token} method with the token index.  However, if you call \texttt{token} before the token has been requested by the parser, it may mess up a context-sensitive scanner.\footnote{When using a context-sensitive scanner, the parser tells the scanner what the valid token types are at each point.  If you call \texttt{token} before the parser can tell the scanner the valid token types, the scanner will attempt to match without considering the context.}  A
-potentially useful combination of these fields is to extract the
-portion of the input matched by the current rule.  To do this, just save the scanner state (\texttt{\_scanner.pos}) before the text is matched and then again after the text is matched:
-
-\begin{verbatim}
-  rule R: 
-      {{ start = self._scanner.pos }}
-      a b c 
-      {{ end = self._scanner.pos }}
-      {{ print 'Text is', self._scanner.input[start:end] }}
-\end{verbatim}
-
-\mysubsection{Pre- and Post-Parser Code}
-
-Sometimes the parser code needs to rely on helper variables,
-functions, and classes.  A Yapps grammar can optionally be surrounded
-by double percent signs, to separate the grammar from Python code.
-
-\begin{verbatim}
-... Python code ...
-%%
-... Yapps grammar ...
-%%
-... Python code ...
-\end{verbatim}
-
-The second \verb|%%| can be omitted if there is no Python code at the
-end, and the first \verb|%%| can be omitted if there is no extra
-Python code at all.  (To have code only at the end, both separators
-are required.)
-
-If the second \verb|%%| is omitted, Yapps will insert testing code
-that allows you to use the generated parser to parse a file.
-
-The extended calculator example in the Yapps examples subdirectory
-includes both pre-parser and post-parser code.
-
-\mysubsection{Representation of Grammars}
-
-For each kind of pattern there is a class derived from Pattern.  Yapps 
-has classes for Terminal, NonTerminal, Sequence, Choice, Option, Plus, 
-Star, and Eval.  Each of these classes has the following interface:
-
-\begin{itemize}
- \item[setup(\emph{gen})] Set accepts-$\epsilon$, and call
-   \emph{gen.changed()} if it changed.  This function can change the
-   flag from false to true but \emph{not} from true to false.
- \item[update(\emph(gen))] Set \first and \follow, and call
-   \emph{gen.changed()} if either changed.  This function can add to
-   the sets but \emph{not} remove from them.
- \item[output(\emph{gen}, \emph{indent})] Generate code for matching
-   this rule, using \emph{indent} as the current indentation level.
-   Writes are performed using \emph{gen.write}.
- \item[used(\emph{vars})] Given a list of variables \emph{vars},
-   return two lists: one containing the variables that are used, and
-   one containing the variables that are assigned.  This function is
-   used for optimizing the resulting code.
-\end{itemize}
-
-Both \emph{setup} and \emph{update} monotonically increase the
-variables they modify.  Since the variables can only increase a finite
-number of times, we can repeatedly call the function until the
-variable stabilized.  The \emph{used} function is not currently
-implemented.
-
-With each pattern in the grammar Yapps associates three pieces of
-information: the \first set, the \follow set, and the
-accepts-$\epsilon$ flag.
-
-The \first set contains the tokens that can appear as we start
-matching the pattern.  The \follow set contains the tokens that can
-appear immediately after we match the pattern.  The accepts-$\epsilon$ 
-flag is true if the pattern can match no tokens.  In this case, \first 
-will contain all the elements in \follow.  The \follow set is not
-needed when accepts-$\epsilon$ is false, and may not be accurate in
-those cases.
-
-Yapps does not compute these sets precisely.  Its approximation can
-miss certain cases, such as this one:
-
-\begin{verbatim}
-  rule C: ( A* | B )
-  rule B: C [A]
-\end{verbatim}
-
-Yapps will calculate {\tt C}'s \follow set to include {\tt A}.
-However, {\tt C} will always match all the {\tt A}'s, so {\tt A} will
-never follow it.  Yapps 2.0 does not properly handle this construct,
-but if it seems important, I may add support for it in a future
-version.
-
-Yapps also cannot handle constructs that depend on the calling
-sequence.  For example:
-
-\begin{verbatim}
-  rule R: U | 'b'
-  rule S:   | 'c'
-  rule T: S 'b'
-  rule U: S 'a'
-\end{verbatim}
-
-The \follow set for {\tt S} includes {\tt a} and {\tt b}.  Since {\tt
-  S} can be empty, the \first set for {\tt S} should include {\tt a},
-{\tt b}, and {\tt c}.  However, when parsing {\tt R}, if the lookahead
-is {\tt b} we should \emph{not} parse {\tt U}.  That's because in {\tt
-  U}, {\tt S} is followed by {\tt a} and not {\tt b}.  Therefore in
-{\tt R}, we should choose rule {\tt U} only if there is an {\tt a} or
-{\tt c}, but not if there is a {\tt b}.  Yapps and many other LL(1)
-systems do not distinguish {\tt S b} and {\tt S a}, making {\tt
-  S}'s \follow set {\tt a, b}, and making {\tt R} always try to match
-{\tt U}.  In this case we can solve the problem by changing {\tt R} to 
-\verb:'b' | U: but it may not always be possible to solve all such
-problems in this way.
-
-\appendix
-
-\mysection{Grammar for Parsers}
-
-This is the grammar for parsers, without any Python code mixed in.
-The complete grammar can be found in \texttt{parsedesc.g} in the Yapps
-distribution.
-
-\begin{verbatim}
-parser ParserDescription:
-    ignore:      "\\s+"
-    ignore:      "#.*?\r?\n"
-    token END:   "$"  # $ means end of string
-    token ATTR:  "<<.+?>>"
-    token STMT:  "{{.+?}}"
-    token ID:    '[a-zA-Z_][a-zA-Z_0-9]*'
-    token STR:   '[rR]?\'([^\\n\'\\\\]|\\\\.)*\'|[rR]?"([^\\n"\\\\]|\\\\.)*"'
-
-    rule Parser: "parser" ID ":"
-                   Options
-                   Tokens
-                   Rules
-                 END 
-
-    rule Options:  ( "option" ":" STR )*
-    rule Tokens:   ( "token" ID ":" STR | "ignore"   ":" STR )*
-    rule Rules:    ( "rule" ID OptParam ":" ClauseA )*
-
-    rule ClauseA:  ClauseB ( '[|]' ClauseB )*
-    rule ClauseB:  ClauseC*
-    rule ClauseC:  ClauseD [ '[+]' | '[*]' ]
-    rule ClauseD:  STR | ID [ATTR] | STMT
-                 | '\\(' ClauseA '\\) | '\\[' ClauseA '\\]'
-\end{verbatim}
-
-\mysection{Upgrading}
-
-Yapps 2.0 is not backwards compatible with Yapps 1.0.  In this section 
-are some tips for upgrading:
-
-\begin{enumerate}
- \item Yapps 1.0 was distributed as a single file.  Yapps 2.0 is
-   instead distributed as two Python files: a \emph{parser generator}
-   (26k) and a \emph{parser runtime} (5k).  You need both files to
-   create parsers, but you need only the runtime (\texttt{yappsrt.py})
-   to use the parsers.
-   
- \item Yapps 1.0 supported Python 1.4 regular expressions from the
-   \texttt{regex} module.  Yapps 2.0 uses Python 1.5 regular
-   expressions from the \texttt{re} module.  \emph{The new syntax for
-     regular expressions is not compatible with the old syntax.}
-   Andrew Kuchling has a \htmladdnormallink{guide to converting
-     regular
-     expressions}{http://www.python.org/doc/howto/regex-to-re/} on his
-   web page.
-   
- \item Yapps 1.0 wants a pattern and then a return value in \verb|->|
-   \verb|<<...>>|.  Yapps 2.0 allows patterns and Python statements to
-   be mixed.  To convert a rule like this:
-
-\begin{verbatim}
-rule R: A B C -> << E1 >>
-      | X Y Z -> << E2 >>
-\end{verbatim}
-   
-   to Yapps 2.0 form, replace the return value specifiers with return
-   statements:
-
-\begin{verbatim}
-rule R: A B C {{ return E1 }}
-      | X Y Z {{ return E2 }}
-\end{verbatim}
-   
- \item Yapps 2.0 does not perform tail recursion elimination.  This
-   means any recursive rules you write will be turned into recursive
-   methods in the parser.  The parser will work, but may be slower.
-   It can be made faster by rewriting recursive rules, using instead
-   the looping operators \verb|*| and \verb|+| provided in Yapps 2.0.
-
-\end{enumerate}
-
-\mysection{Troubleshooting}
-
-\begin{itemize}
- \item A common error is to write a grammar that doesn't have an END
-   token.  End tokens are needed when it is not clear when to stop
-   parsing.  For example, when parsing the expression {\tt 3+5}, it is 
-   not clear after reading {\tt 3} whether to treat it as a complete
-   expression or whether the parser should continue reading.
-   Therefore the grammar for numeric expressions should include an end 
-   token.  Another example is the grammar for Lisp expressions.  In
-   Lisp, it is always clear when you should stop parsing, so you do
-   \emph{not} need an end token.  In fact, it may be more useful not
-   to have an end token, so that you can read in several Lisp expressions.
- \item If there is a chance of ambiguity, make sure to put the choices 
-   in the order you want them checked.  Usually the most specific
-   choice should be first.  Empty sequences should usually be last.
- \item The context sensitive scanner is not appropriate for all
-   grammars.  You might try using the insensitive scanner with the
-   {\tt context-insensitive-scanner} option in the grammar.
- \item If performance turns out to be a problem, try writing a custom
-   scanner.  The Yapps scanner is rather slow (but flexible and easy
-   to understand).
-\end{itemize}
-
-\mysection{History}
-
-Yapps 1 had several limitations that bothered me while writing
-parsers:
-
-\begin{enumerate}
- \item It was not possible to insert statements into the generated
-   parser.  A common workaround was to write an auxilliary function
-   that executed those statements, and to call that function as part
-   of the return value calculation.  For example, several of my
-   parsers had an ``append(x,y)'' function that existed solely to call 
-   ``x.append(y)''.
- \item The way in which grammars were specified was rather
-   restrictive: a rule was a choice of clauses.  Each clause was a
-   sequence of tokens and rule names, followed by a return value.
- \item Optional matching had to be put into a separate rule because
-   choices were only made at the beginning of a rule.
- \item Repetition had to be specified in terms of recursion.  Not only 
-   was this awkward (sometimes requiring additional rules), I had to
-   add a tail recursion optimization to Yapps to transform the
-   recursion back into a loop.
-\end{enumerate}
-
-Yapps 2 addresses each of these limitations.
-
-\begin{enumerate}
- \item Statements can occur anywhere within a rule.  (However, only
-   one-line statements are allowed; multiline blocks marked by
-   indentation are not.)
- \item Grammars can be specified using any mix of sequences, choices,
-   tokens, and rule names.  To allow for complex structures,
-   parentheses can be used for grouping.
- \item Given choices and parenthesization, optional matching can be
-   expressed as a choice between some pattern and nothing.  In
-   addition, Yapps 2 has the convenience syntax \verb|[A B ...]| for
-   matching \verb|A B ...| optionally.
- \item Repetition operators \verb|*| for zero or more and \verb|+| for 
-   one or more make it easy to specify repeating patterns.
-\end{enumerate}
-
-It is my hope that Yapps 2 will be flexible enough to meet my needs
-for another year, yet simple enough that I do not hesitate to use it.
-
-\mysection{Future Extensions}
-\label{sec:future}
-
-I am still investigating the possibility of LL(2) and higher
-lookahead.  However, it looks like the resulting parsers will be
-somewhat ugly.  
-
-It would be nice to control choices with user-defined predicates.
-
-The most likely future extension is backtracking.  A grammar pattern
-like \verb|(VAR ':=' expr)? {{ return Assign(VAR,expr) }} : expr {{ return expr }}|
-would turn into code that attempted to match \verb|VAR ':=' expr|.  If 
-it succeeded, it would run \verb|{{ return ... }}|.  If it failed, it
-would match \verb|expr {{ return expr }}|.  Backtracking may make it
-less necessary to write LL(2) grammars.
-
-\mysection{References}
-
-\begin{enumerate}
- \item The \htmladdnormallink{Python-Parser
-     SIG}{http://www.python.org/sigs/parser-sig/} is the first place
-   to look for a list of parser systems for Python.
-    
-  \item ANTLR/PCCTS, by Terrence Parr, is available at
-  \htmladdnormallink{The ANTLR Home Page}{http://www.antlr.org/}.
-  
-  \item PyLR, by Scott Cotton, is at \htmladdnormallink{his Starship
-    page}{http://starship.skyport.net/crew/scott/PyLR.html}.
-  
-  \item John Aycock's \htmladdnormallink{Compiling Little Languages
-      Framework}{http://www.csr.UVic.CA/~aycock/python/}.
-
-  \item PyBison, by Scott Hassan, can be found at
-  \htmladdnormallink{his Python Projects
-    page}{http://coho.stanford.edu/\~{}hassan/Python/}.
-  
-  \item mcf.pars, by Mike C. Fletcher, is available at
-  \htmladdnormallink{his web
-    page}{http://www.golden.net/\~{}mcfletch/programming/}.
-  
-  \item kwParsing, by Aaron Watters, is available at
-  \htmladdnormallink{his Starship
-    page}{http://starship.skyport.net/crew/aaron_watters/kwParsing/}.
-\end{enumerate}
-
-\end{document}
diff --git a/util/newconfig/yappsrt.py b/util/newconfig/yappsrt.py
deleted file mode 100644
index 2ce2480..0000000
--- a/util/newconfig/yappsrt.py
+++ /dev/null
@@ -1,172 +0,0 @@
-# Yapps 2.0 Runtime
-#
-# This module is needed to run generated parsers.
-
-from string import *
-import exceptions
-import re
-
-class SyntaxError(Exception):
-    """When we run into an unexpected token, this is the exception to use"""
-    def __init__(self, pos=-1, msg="Bad Token"):
-	self.pos = pos
-	self.msg = msg
-    def __repr__(self):
-	if self.pos < 0: return "#<syntax-error>"
-	else: return "SyntaxError[@ char " + `self.pos` + ": " + self.msg + "]"
-
-class NoMoreTokens(Exception):
-    """Another exception object, for when we run out of tokens"""
-    pass
-
-class Scanner:
-    def __init__(self, patterns, ignore, input):
-	"""Patterns is [(terminal,regex)...]
-        Ignore is [terminal,...];
-	Input is a string"""
-	self.tokens = []
-	self.restrictions = []
-	self.input = input
-	self.pos = 0
-	self.ignore = ignore
-	# The stored patterns are a pair (compiled regex,source
-	# regex).  If the patterns variable passed in to the
-	# constructor is None, we assume that the class already has a
-	# proper .patterns list constructed
-        if patterns is not None:
-            self.patterns = []
-            for k,r in patterns:
-                self.patterns.append( (k, re.compile(r)) )
-	
-    def token(self, i, restrict=0):
-	"""Get the i'th token, and if i is one past the end, then scan 
-	for another token; restrict is a list of tokens that
-	are allowed, or 0 for any token."""
-	if i == len(self.tokens): self.scan(restrict)
-	if i < len(self.tokens):
-	    # Make sure the restriction is more restricted
-	    if restrict and self.restrictions[i]:
-		for r in restrict:
-		    if r not in self.restrictions[i]:
-			raise "Unimplemented: restriction set changed"
-	    return self.tokens[i]
-	raise NoMoreTokens()
-    
-    def __repr__(self):
-	"""Print the last 10 tokens that have been scanned in"""
-	output = ''
-	for t in self.tokens[-10:]:
-	    output = '%s\n  (@%s)  %s  =  %s' % (output,t[0],t[2],`t[3]`)
-	return output
-    
-    def scan(self, restrict):
-	"""Should scan another token and add it to the list, self.tokens,
-	and add the restriction to self.restrictions"""
-	# Keep looking for a token, ignoring any in self.ignore
-	while 1:
-	    # Search the patterns for the longest match, with earlier
-	    # tokens in the list having preference
-	    best_match = -1
-	    best_pat = '(error)'
-	    for p, regexp in self.patterns:
-		# First check to see if we're ignoring this token
-		if restrict and p not in restrict and p not in self.ignore: 
-		    continue
-		m = regexp.match(self.input, self.pos)
-		if m and len(m.group(0)) > best_match:
-		    # We got a match that's better than the previous one
-		    best_pat = p
-		    best_match = len(m.group(0))
-		    
-	    # If we didn't find anything, raise an error
-	    if best_pat == '(error)' and best_match < 0:
-		msg = "Bad Token"
-		if restrict:
-		    msg = "Trying to find one of "+join(restrict,", ")
-		raise SyntaxError(self.pos, msg)
-
-	    # If we found something that isn't to be ignored, return it
-	    if best_pat not in self.ignore:
-		# Create a token with this data
-		token = (self.pos, self.pos+best_match, best_pat,
-			 self.input[self.pos:self.pos+best_match])
-		self.pos = self.pos + best_match
-		# Only add this token if it's not in the list
-		# (to prevent looping)
-		if not self.tokens or token != self.tokens[-1]:
-		    self.tokens.append(token)
-		    self.restrictions.append(restrict)
-		return
-	    else:
-		# This token should be ignored ..
-		self.pos = self.pos + best_match
-
-class Parser:
-    def __init__(self, scanner):
-        self._scanner = scanner
-        self._pos = 0
-        
-    def _peek(self, *types):
-        """Returns the token type for lookahead; if there are any args
-        then the list of args is the set of token types to allow"""
-        tok = self._scanner.token(self._pos, types)
-        return tok[2]
-        
-    def _scan(self, type):
-        """Returns the matched text, and moves to the next token"""
-        tok = self._scanner.token(self._pos, [type])
-        if tok[2] != type:
-            raise SyntaxError(tok[0], 'Trying to find '+type)
-        self._pos = 1+self._pos
-        return tok[3]
-
-
-
-def print_error(input, err, scanner):
-    """This is a really dumb long function to print error messages nicely."""
-    p = err.pos
-    # Figure out the line number
-    line = count(input[:p], '\n')
-    print err.msg+" on line "+`line+1`+":"
-    # Now try printing part of the line
-    text = input[max(p-80,0):p+80]
-    p = p - max(p-80,0)
-
-    # Strip to the left
-    i = rfind(text[:p],'\n')
-    j = rfind(text[:p],'\r')
-    if i < 0 or (j < i and j >= 0): i = j
-    if i >= 0 and i < p: 
-	p = p - i - 1
-	text = text[i+1:]
-
-    # Strip to the right
-    i = find(text,'\n',p)
-    j = find(text,'\r',p)
-    if i < 0 or (j < i and j >= 0): i = j
-    if i >= 0: 
-	text = text[:i]
-
-    # Now shorten the text
-    while len(text) > 70 and p > 60:
-	# Cut off 10 chars
-	text = "..." + text[10:]
-	p = p - 7
-
-    # Now print the string, along with an indicator
-    print '> ',text
-    print '> ',' '*p + '^'
-    print 'List of nearby tokens:', scanner
-
-def wrap_error_reporter(parser, rule):
-    try: return getattr(parser, rule)()
-    except SyntaxError, s:
-        input = parser._scanner.input
-        try:
-            print_error(input, s, parser._scanner)
-        except ImportError:
-            print 'Syntax Error',s.msg,'on line',1+count(input[:s.pos], '\n')
-    except NoMoreTokens:
-        print 'Could not complete parsing; stopped around here:'
-        print parser._scanner
-
diff --git a/util/x86emu/Config.lb b/util/x86emu/Config.lb
deleted file mode 100644
index 85d21e7..0000000
--- a/util/x86emu/Config.lb
+++ /dev/null
@@ -1,17 +0,0 @@
-uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
-uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-
-if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-  dir yabel
-  dir x86emu
-else
-  if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-    object x86.o
-    object x86_interrupts.o
-    object x86_asm.S
-  else
-    object biosemu.o
-    dir x86emu
-  end
-end
-
diff --git a/util/x86emu/x86emu/Config.lb b/util/x86emu/x86emu/Config.lb
deleted file mode 100644
index f5ca6d7..0000000
--- a/util/x86emu/x86emu/Config.lb
+++ /dev/null
@@ -1,9 +0,0 @@
-makedefine CPPFLAGS += -I$(TOP)/util/x86emu/include
-
-object debug.o
-object decode.o
-object fpu.o
-object ops.o
-object ops2.o
-object prim_ops.o
-object sys.o
diff --git a/util/x86emu/yabel/Config.lb b/util/x86emu/yabel/Config.lb
deleted file mode 100644
index 523c794..0000000
--- a/util/x86emu/yabel/Config.lb
+++ /dev/null
@@ -1,9 +0,0 @@
-object biosemu.o
-object debug.o
-object device.o
-object interrupt.o
-object io.o
-object mem.o
-object pmm.o
-#object vbe.o
-dir compat
diff --git a/util/x86emu/yabel/compat/Config.lb b/util/x86emu/yabel/compat/Config.lb
deleted file mode 100644
index 919526d..0000000
--- a/util/x86emu/yabel/compat/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object functions.o