Upstream-Status: Unknown Signed-off-by: Khem Raj From 26adb06ce515aadfec08ce13109b4b98287f677b Mon Sep 17 00:00:00 2001 From: Nebu Philips Date: Fri, 30 Jul 2010 15:10:03 -0700 Subject: [PATCH] Add support for Netlogic XLP Using the mipsisa64r2nlm target, add support for XLP from Netlogic. Also, update vendor name to NLM wherever applicable. --- bfd/aoutx.h | 1 + bfd/archures.c | 1 + bfd/bfd-in2.h | 1 + bfd/config.bfd | 5 +++++ bfd/cpu-mips.c | 6 ++++-- bfd/elfxx-mips.c | 8 ++++++++ binutils/readelf.c | 1 + config.sub | 6 ++++++ gas/config/tc-mips.c | 7 ++++++- gas/configure | 3 +++ gas/configure.tgt | 2 +- gas/doc/c-mips.texi | 3 ++- include/elf/mips.h | 1 + include/opcode/mips.h | 6 +++++- ld/configure.tgt | 2 ++ opcodes/mips-dis.c | 6 ++++++ opcodes/mips-opc.c | 31 ++++++++++++++++++++----------- 17 files changed, 73 insertions(+), 17 deletions(-) Index: binutils-2.24/bfd/aoutx.h =================================================================== --- binutils-2.24.orig/bfd/aoutx.h 2013-12-15 13:07:57.180399300 -0800 +++ binutils-2.24/bfd/aoutx.h 2013-12-15 13:08:03.397065919 -0800 @@ -798,6 +798,7 @@ case bfd_mach_mipsisa64r2: case bfd_mach_mips_sb1: case bfd_mach_mips_xlr: + case bfd_mach_mips_xlp: /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */ arch_flags = M_MIPS2; break; Index: binutils-2.24/bfd/archures.c =================================================================== --- binutils-2.24.orig/bfd/archures.c 2013-12-15 13:07:57.180399300 -0800 +++ binutils-2.24/bfd/archures.c 2013-12-15 13:08:03.397065919 -0800 @@ -178,6 +178,7 @@ .#define bfd_mach_mips_octeonp 6601 .#define bfd_mach_mips_octeon2 6502 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *} +.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP' *} .#define bfd_mach_mipsisa32 32 .#define bfd_mach_mipsisa32r2 33 .#define bfd_mach_mipsisa64 64 Index: binutils-2.24/bfd/bfd-in2.h =================================================================== --- binutils-2.24.orig/bfd/bfd-in2.h 2013-12-15 13:07:57.180399300 -0800 +++ binutils-2.24/bfd/bfd-in2.h 2013-12-15 13:08:03.400399254 -0800 @@ -1933,6 +1933,7 @@ #define bfd_mach_mips_octeonp 6601 #define bfd_mach_mips_octeon2 6502 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */ +#define bfd_mach_mips_xlp 887680 /* decimal 'XLP' */ #define bfd_mach_mipsisa32 32 #define bfd_mach_mipsisa32r2 33 #define bfd_mach_mipsisa64 64 Index: binutils-2.24/bfd/config.bfd =================================================================== --- binutils-2.24.orig/bfd/config.bfd 2013-12-15 13:08:03.047065922 -0800 +++ binutils-2.24/bfd/config.bfd 2013-12-15 13:08:03.400399254 -0800 @@ -1032,6 +1032,11 @@ targ_defvec=bfd_elf32_littlemips_vec targ_selvecs="bfd_elf32_bigmips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec" ;; + mipsisa64*-*-elf*) + targ_defvec=bfd_elf32_tradbigmips_vec + targ_selvecs="bfd_elf32_tradlittlemips_vec bfd_elf64_tradbigmips_vec bfd_elf64_tradlittlemips_vec" + want64=true + ;; mips*-*-elf* | mips*-*-rtems* | mips*-*-vxworks | mips*-*-windiss) targ_defvec=bfd_elf32_bigmips_vec targ_selvecs="bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec" Index: binutils-2.24/bfd/cpu-mips.c =================================================================== --- binutils-2.24.orig/bfd/cpu-mips.c 2013-12-15 13:07:57.180399300 -0800 +++ binutils-2.24/bfd/cpu-mips.c 2013-12-15 13:08:03.400399254 -0800 @@ -99,7 +99,8 @@ I_mipsocteonp, I_mipsocteon2, I_xlr, - I_micromips + I_micromips, + I_xlp }; #define NN(index) (&arch_info_struct[(index) + 1]) @@ -143,7 +144,8 @@ N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)), N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)), N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)), - N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0) + N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)), + N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0) }; /* The default architecture is mips:3000, but with a machine number of Index: binutils-2.24/bfd/elfxx-mips.c =================================================================== --- binutils-2.24.orig/bfd/elfxx-mips.c 2013-12-15 13:07:57.180399300 -0800 +++ binutils-2.24/bfd/elfxx-mips.c 2013-12-15 13:08:03.400399254 -0800 @@ -6404,6 +6404,9 @@ case E_MIPS_MACH_XLR: return bfd_mach_mips_xlr; + case E_MIPS_MACH_XLP: + return bfd_mach_mips_xlp; + default: switch (flags & EF_MIPS_ARCH) { @@ -11622,6 +11625,10 @@ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2; break; + case bfd_mach_mips_xlp: + val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP; + break; + case bfd_mach_mipsisa32: val = E_MIPS_ARCH_32; break; @@ -14202,6 +14209,7 @@ { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp }, { bfd_mach_mips_octeonp, bfd_mach_mips_octeon }, { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 }, + { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 }, /* MIPS64 extensions. */ { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, Index: binutils-2.24/binutils/readelf.c =================================================================== --- binutils-2.24.orig/binutils/readelf.c 2013-12-15 13:07:57.180399300 -0800 +++ binutils-2.24/binutils/readelf.c 2013-12-15 13:08:03.403732587 -0800 @@ -2602,6 +2602,7 @@ case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break; case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break; case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; + case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break; case 0: /* We simply ignore the field in this case to avoid confusion: MIPS ELF does not specify EF_MIPS_MACH, it is a GNU Index: binutils-2.24/gas/config/tc-mips.c =================================================================== --- binutils-2.24.orig/gas/config/tc-mips.c 2013-12-15 13:07:57.180399300 -0800 +++ binutils-2.24/gas/config/tc-mips.c 2013-12-15 13:17:19.943728439 -0800 @@ -486,6 +486,7 @@ || mips_opts.arch == CPU_RM7000 \ || mips_opts.arch == CPU_VR5500 \ || mips_opts.micromips \ + || mips_opts.arch == CPU_XLP \ ) /* Whether the processor uses hardware interlocks to protect reads @@ -515,6 +516,7 @@ && mips_opts.isa != ISA_MIPS3) \ || mips_opts.arch == CPU_R4300 \ || mips_opts.micromips \ + || mips_opts.arch == CPU_XLP \ ) /* Whether the processor uses hardware interlocks to protect reads @@ -17794,7 +17796,7 @@ /* Broadcom XLP. XLP is mostly like XLR, with the prominent exception that it is MIPS64R2 rather than MIPS64. */ - { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, + { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP }, /* End marker */ { NULL, 0, 0, 0, 0 } Index: binutils-2.24/gas/configure =================================================================== --- binutils-2.24.orig/gas/configure 2013-12-15 13:08:01.127065936 -0800 +++ binutils-2.24/gas/configure 2013-12-15 13:08:03.407065920 -0800 @@ -12697,6 +12697,9 @@ mipsisa64r2 | mipsisa64r2el) mips_cpu=mips64r2 ;; + mipsisa64r2nlm | mipsisa64r2nlmel) + mips_cpu=xlp + ;; mipstx39 | mipstx39el) mips_cpu=r3900 ;; Index: binutils-2.24/gas/configure.tgt =================================================================== --- binutils-2.24.orig/gas/configure.tgt 2013-12-15 13:08:00.783732605 -0800 +++ binutils-2.24/gas/configure.tgt 2013-12-15 13:08:03.407065920 -0800 @@ -325,7 +325,7 @@ fmt=elf em=freebsd ;; mips-*-sysv4*MP* | mips-*-gnu*) fmt=elf em=tmips ;; mips*-sde-elf* | mips*-mti-elf*) fmt=elf em=tmips ;; - mips-*-elf* | mips-*-rtems*) fmt=elf ;; + mips-*-elf* | mips-*-rtems*) fmt=elf em=tmips ;; mips-*-netbsd*) fmt=elf em=tmips ;; mips-*-openbsd*) fmt=elf em=tmips ;; Index: binutils-2.24/include/elf/mips.h =================================================================== --- binutils-2.24.orig/include/elf/mips.h 2013-12-15 13:07:57.180399300 -0800 +++ binutils-2.24/include/elf/mips.h 2013-12-15 13:08:03.407065920 -0800 @@ -274,6 +274,7 @@ #define E_MIPS_MACH_SB1 0x008a0000 #define E_MIPS_MACH_OCTEON 0x008b0000 #define E_MIPS_MACH_XLR 0x008c0000 +#define E_MIPS_MACH_XLP 0x008e0000 #define E_MIPS_MACH_OCTEON2 0x008d0000 #define E_MIPS_MACH_5400 0x00910000 #define E_MIPS_MACH_5900 0x00920000 Index: binutils-2.24/include/opcode/mips.h =================================================================== --- binutils-2.24.orig/include/opcode/mips.h 2013-12-15 13:07:57.180399300 -0800 +++ binutils-2.24/include/opcode/mips.h 2013-12-15 13:40:11.130384844 -0800 @@ -1092,8 +1092,10 @@ #define INSN_LOONGSON_2F 0x80000000 /* Loongson 3A. */ #define INSN_LOONGSON_3A 0x00000400 -/* RMI Xlr instruction */ -#define INSN_XLR 0x00000020 +/* Netlogic Xlr instruction */ +#define INSN_XLR 0x00000020 +/* Netlogic XlP instruction */ +#define INSN_XLP 0x00000040 /* DSP ASE */ #define ASE_DSP 0x00000001 @@ -1172,6 +1174,7 @@ #define CPU_OCTEONP 6601 #define CPU_OCTEON2 6502 #define CPU_XLR 887682 /* decimal 'XLR' */ +#define CPU_XLP 887680 /* decimal 'XLP' */ /* Return true if the given CPU is included in INSN_* mask MASK. */ @@ -1239,6 +1242,9 @@ case CPU_XLR: return (mask & INSN_XLR) != 0; + case CPU_XLP: + return (mask & INSN_XLP) != 0; + default: return FALSE; } Index: binutils-2.24/ld/configure.tgt =================================================================== --- binutils-2.24.orig/ld/configure.tgt 2013-12-15 13:08:03.047065922 -0800 +++ binutils-2.24/ld/configure.tgt 2013-12-15 13:08:03.407065920 -0800 @@ -457,6 +457,8 @@ mips*-sde-elf* | mips*-mti-elf*) targ_emul=elf32btsmip targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; +mipsisa64*-*-elf*) targ_emul=elf32btsmip + targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip" ;; mips64*el-ps2-elf*) targ_emul=elf32lr5900n32 targ_extra_emuls="elf32lr5900" targ_extra_libpath=$targ_extra_emuls ;; Index: binutils-2.24/opcodes/mips-dis.c =================================================================== --- binutils-2.24.orig/opcodes/mips-dis.c 2013-12-15 13:07:57.180399300 -0800 +++ binutils-2.24/opcodes/mips-dis.c 2013-12-15 13:39:50.243718329 -0800 @@ -554,13 +554,11 @@ mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), mips_hwr_names_numeric }, - /* XLP is mostly like XLR, with the prominent exception it is being - MIPS64R2. */ - { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR, - ISA_MIPS64R2 | INSN_XLR, 0, - mips_cp0_names_xlr, - mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), - mips_hwr_names_numeric }, + { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP, + ISA_MIPS64R2 | INSN_XLP, 0, + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_hwr_names_mips3264r2 }, /* This entry, mips16, is here only for ISA/processor selection; do not print its name. */ Index: binutils-2.24/opcodes/mips-opc.c =================================================================== --- binutils-2.24.orig/opcodes/mips-opc.c 2013-12-15 13:07:57.180399300 -0800 +++ binutils-2.24/opcodes/mips-opc.c 2013-12-15 13:27:30.573724118 -0800 @@ -262,7 +262,8 @@ #define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2) #define IOCTP (INSN_OCTEONP | INSN_OCTEON2) #define IOCT2 INSN_OCTEON2 -#define XLR INSN_XLR +#define XLR INSN_XLR +#define XLP INSN_XLP #define IVIRT ASE_VIRT #define IVIRT64 ASE_VIRT64 @@ -881,6 +882,7 @@ {"cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 }, {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 }, +{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 }, {"ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 }, {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 }, @@ -913,10 +915,11 @@ {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, -{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 }, +{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR|XLP, 0, 0 }, {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 }, {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, 0 }, {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, 0 }, +{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 }, /* dctr and dctw are used on the r5000. */ {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, @@ -980,6 +983,7 @@ {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LCD, 0, I64, 0, 0 }, {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LCD, 0, 0, IVIRT64, 0 }, {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LCD, 0, 0, IVIRT64, 0 }, +{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_1, 0, XLP, 0, 0 }, {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, I3, 0, EE }, @@ -994,6 +998,8 @@ /* dmtc2 is at the bottom of the table. */ /* dmfc3 is at the bottom of the table. */ /* dmtc3 is at the bottom of the table. */ +{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_1, 0, XLP, 0, 0 }, +{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 }, {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32 }, {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, M32 }, @@ -1134,9 +1140,9 @@ /* The macro has to be first to handle o32 correctly. */ {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3, 0, I3, 0, 0 }, -{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, -{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, -{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, +{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, +{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, +{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, @@ -1288,7 +1294,7 @@ {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, -{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR, 0, 0 }, +{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR|XLP, 0, 0 }, {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, @@ -1332,10 +1338,13 @@ /* move is at the top of the table. */ {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, +{"msgsnds", "d,t", 0x4a000001, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 }, {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 }, {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 }, -{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 }, -{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 }, +{"msglds", "d,t", 0x4a000002, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 }, +{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP, 0, 0 }, +{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP, 0, 0 }, +{"msgsync", "", 0x4a000004, 0xffffffff,0, 0, XLP, 0, 0 }, {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, 0 }, {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, @@ -1381,7 +1390,7 @@ {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, -{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR, 0, 0 }, +{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 }, {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, @@ -1802,9 +1811,9 @@ {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, 0}, {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, -{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, -{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, +{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, +{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, +{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2 }, {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },