diff options
Diffstat (limited to 'meta-aspeed/recipes-bsp/u-boot/files/patch-2013.07/0001-u-boot-openbmc.patch')
-rw-r--r-- | meta-aspeed/recipes-bsp/u-boot/files/patch-2013.07/0001-u-boot-openbmc.patch | 1580 |
1 files changed, 1580 insertions, 0 deletions
diff --git a/meta-aspeed/recipes-bsp/u-boot/files/patch-2013.07/0001-u-boot-openbmc.patch b/meta-aspeed/recipes-bsp/u-boot/files/patch-2013.07/0001-u-boot-openbmc.patch new file mode 100644 index 0000000..e38ae5a --- /dev/null +++ b/meta-aspeed/recipes-bsp/u-boot/files/patch-2013.07/0001-u-boot-openbmc.patch @@ -0,0 +1,1580 @@ +diff --git a/arch/arm/cpu/arm926ejs/aspeed/IO.c b/arch/arm/cpu/arm926ejs/aspeed/IO.c +index 86e9918..b06fdba 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/IO.c ++++ b/arch/arm/cpu/arm926ejs/aspeed/IO.c +@@ -31,7 +31,7 @@ static const char ThisFile[] = "IO.c"; + #include <post.h>
+ #include <malloc.h>
+ #include <net.h>
+- #include <COMMINF.H>
++ #include "COMMINF.H"
+ #endif
+ #ifdef SLT_DOS
+ #include <stdlib.h>
+@@ -353,4 +353,3 @@ ULONG ReadSOC_DD(ULONG addr) + #endif
+ return 0;
+ }
+-
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c b/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c +index 498d4fd..fdabd45 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c ++++ b/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c +@@ -13,9 +13,9 @@ static const char ThisFile[] = "LAN9303.c"; +
+ #include "SWFUNC.H" + #ifdef SLT_UBOOT
+- #include <COMMINF.H>
+- #include <MAC.H>
+- #include <IO.H>
++ #include "COMMINF.H" ++ #include "MAC.H" ++ #include "IO.H"
+ #endif
+
+ #ifdef SLT_DOS
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/MAC.c b/arch/arm/cpu/arm926ejs/aspeed/MAC.c +index 829da92..b4182f5 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/MAC.c ++++ b/arch/arm/cpu/arm926ejs/aspeed/MAC.c +@@ -16,7 +16,7 @@ static const char ThisFile[] = "MAC.c"; + #ifdef SLT_UBOOT
+ #include <common.h>
+ #include <command.h>
+- #include <COMMINF.H>
++ #include "COMMINF.H"
+ #include "STDUBOOT.H"
+ #endif
+ #ifdef SLT_DOS
+@@ -2081,5 +2081,3 @@ char TestingLoop (ULONG loop_checknum) { +
+ return(0);
+ } // End char TestingLoop (ULONG loop_checknum)
+-
+-
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/Makefile b/arch/arm/cpu/arm926ejs/aspeed/Makefile +index 378745e..4c4e239 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/Makefile ++++ b/arch/arm/cpu/arm926ejs/aspeed/Makefile +@@ -16,7 +16,7 @@ + + include $(TOPDIR)/config.mk + +-LIB = $(obj)lib$(SOC).a ++LIB = $(obj)lib$(SOC).o + + COBJS = timer.o + COBJS += reset.o +@@ -41,7 +41,7 @@ START := $(addprefix $(obj),$(START)) + all: $(obj).depend $(LIB) + + $(LIB): $(OBJS) +- $(AR) $(ARFLAGS) $@ $(OBJS) ++ $(call cmd_link_o_target, $(OBJS)) + + ######################################################################### + +diff --git a/arch/arm/cpu/arm926ejs/aspeed/NCSI.c b/arch/arm/cpu/arm926ejs/aspeed/NCSI.c +index 7de06c3..7e86fb6 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/NCSI.c ++++ b/arch/arm/cpu/arm926ejs/aspeed/NCSI.c +@@ -16,9 +16,9 @@ static const char ThisFile[] = "NCSI.c"; + #ifdef SLT_UBOOT + #include <common.h> + #include <command.h> +- #include <COMMINF.H> +- #include <NCSI.H> +- #include <IO.H> ++ #include "COMMINF.H" ++ #include "NCSI.H" ++ #include "IO.H" + #endif + #ifdef SLT_DOS + #include <stdio.h> +diff --git a/arch/arm/cpu/arm926ejs/aspeed/PHY.c b/arch/arm/cpu/arm926ejs/aspeed/PHY.c +index 6afed9d..db73a70 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/PHY.c ++++ b/arch/arm/cpu/arm926ejs/aspeed/PHY.c +@@ -16,7 +16,7 @@ static const char ThisFile[] = "PHY.c"; + #ifdef SLT_UBOOT
+ #include <common.h>
+ #include <command.h>
+- #include <COMMINF.H>
++ #include "COMMINF.H"
+ #include "STDUBOOT.H"
+ #endif
+ #ifdef SLT_DOS
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c +index 95958b0..2414d57 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c ++++ b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c +@@ -13,11 +13,11 @@ static const char ThisFile[] = "PLLTEST.c"; + + #include "SWFUNC.H" + +-#include <COMMINF.H> +-#include <STDUBOOT.H> +-#include <TYPEDEF.H> +-#include <IO.H> +-#include <PLLTESTU.H> ++#include "COMMINF.H" ++#include "STDUBOOT.H" ++#include "TYPEDEF.H" ++#include "IO.H" ++#include "PLLTESTU.H" + + /* + * static +@@ -407,5 +407,3 @@ int pll_function(int argc, char *argv[]) + return (ERR_FATAL); + } + } +- +- +diff --git a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H +index 7fbf590..4e0adf6 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H ++++ b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H +@@ -13,6 +13,5 @@ + + unsigned long int strtoul(char *string, char **endPtr, int base); + int atoi( char s[] ); +-int rand(void); + + #endif // End STDUBOOT_H +diff --git a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c +index 90e2997..4b1f439 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c ++++ b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c +@@ -19,11 +19,11 @@ int isspace ( char c ) + { + if ( ( c == ' ' ) || ( c == 9 ) || ( c == 13 ) ) + return 1; +- ++ + return 0; + } + +-/* ++/* + * strtoul.c -- + * + * Source code for the "strtoul" library procedure. +@@ -111,7 +111,7 @@ strtoul(char *string, char **endPtr, int base) + * If no base was provided, pick one from the leading characters + * of the string. + */ +- ++ + if (base == 0) + { + if (*p == '0') { +@@ -219,17 +219,6 @@ int atoi( char s[] ) + ans = ( 10 * ans ) + ( s[i] - '0' ); + + return ans; +-} +- +-// ----------------------------------------------------------------------------- +-/* rand:return pseudo-random integer on 0...32767 */ +-int rand(void) +-{ +- static unsigned long int next = 1; +- +- next = next * 1103515245 + 12345; +- +- return (unsigned int) ( next / 65536 ) % 32768; + } + + #endif // End SLT_UBOOT +diff --git a/arch/arm/cpu/arm926ejs/aspeed/STRESS.c b/arch/arm/cpu/arm926ejs/aspeed/STRESS.c +index dffd64f..e86685e 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/STRESS.c ++++ b/arch/arm/cpu/arm926ejs/aspeed/STRESS.c +@@ -12,8 +12,8 @@ + static const char ThisFile[] = "STRESS.c";
+
+ #include "SWFUNC.H"
+-#include <COMMINF.H>
+-#include <IO.H>
++#include "COMMINF.H"
++#include "IO.H"
+
+ #define TIMEOUT_DRAM 5000000
+
+@@ -142,4 +142,3 @@ int dram_stress_function(int argc, char *argv[]) +
+ return( ret );
+ }
+-
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c b/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c +index 72936c0..24ec0c5 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c ++++ b/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c +@@ -13,9 +13,9 @@ static const char ThisFile[] = "PLLTEST.c"; + + #include "SWFUNC.H" + +-#include <COMMINF.H> +-#include <TYPEDEF.H> +-#include <IO.H> ++#include "COMMINF.H" ++#include "TYPEDEF.H" ++#include "IO.H" + + #define ASTCHIP_2400 0 + #define ASTCHIP_2300 1 +diff --git a/arch/arm/cpu/arm926ejs/aspeed/mactest.c b/arch/arm/cpu/arm926ejs/aspeed/mactest.c +index 95bd560..62a696d 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/mactest.c ++++ b/arch/arm/cpu/arm926ejs/aspeed/mactest.c +@@ -19,9 +19,9 @@ static const char ThisFile[] = "MACTEST.c"; + #include <post.h> + #include <malloc.h> + #include <net.h> +- #include <COMMINF.H> +- #include <STDUBOOT.H> +- #include <IO.H> ++ #include "COMMINF.H" ++ #include "STDUBOOT.H" ++ #include "IO.H" + #else + #include <stdlib.h> + #include <string.h> +@@ -1212,4 +1212,3 @@ Find_Err_IOMargin:; + return(Finish_Check(0)); + + } +- +diff --git a/arch/arm/cpu/arm926ejs/aspeed/reset.c b/arch/arm/cpu/arm926ejs/aspeed/reset.c +index e0a57f9..ce8dba1 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/reset.c ++++ b/arch/arm/cpu/arm926ejs/aspeed/reset.c +@@ -17,7 +17,7 @@ void reset_cpu(ulong addr) + { + __raw_writel(0x10 , AST_WDT_BASE+0x04); + __raw_writel(0x4755, AST_WDT_BASE+0x08); +- __raw_writel(0x3, AST_WDT_BASE+0x0c); ++ __raw_writel(0x23, AST_WDT_BASE+0x0c); /* reset the full chip */ + + while (1) + /*nothing*/; +diff --git a/arch/arm/cpu/arm926ejs/aspeed/timer.c b/arch/arm/cpu/arm926ejs/aspeed/timer.c +index 4bba5c5..add4c0e 100644 +--- a/arch/arm/cpu/arm926ejs/aspeed/timer.c ++++ b/arch/arm/cpu/arm926ejs/aspeed/timer.c +@@ -16,12 +16,17 @@ + */ + + #include <common.h> +-#include <arm926ejs.h> ++ ++#if CONFIG_ASPEED_TIMER_CLK < CONFIG_SYS_HZ ++#error "CONFIG_ASPEED_TIMER_CLK must be as large as CONFIG_SYS_HZ" ++#endif + + #define TIMER_LOAD_VAL 0xffffffff ++#define CLK_PER_HZ (CONFIG_ASPEED_TIMER_CLK / CONFIG_SYS_HZ) + + /* macro to read the 32 bit timer */ +-#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+0)) ++#define READ_CLK (*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0)) ++#define READ_TIMER (READ_CLK / CLK_PER_HZ) + + static ulong timestamp; + static ulong lastdec; +@@ -57,27 +62,25 @@ void set_timer (ulong t) + } + + /* delay x useconds AND perserve advance timstamp value */ +-void udelay (unsigned long usec) ++void __udelay (unsigned long usec) + { +- ulong tmo, tmp; +- +- if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ +- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ +- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ +- tmo /= 1000; /* finish normalize. */ +- }else{ /* else small number, don't kill it prior to HZ multiply */ +- tmo = usec * CONFIG_SYS_HZ; +- tmo /= (1000*1000); +- } +- +- tmp = get_timer (0); /* get current timestamp */ +- if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ +- reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ +- else +- tmo += tmp; /* else, set advancing stamp wake up time */ +- +- while (get_timer_masked () < tmo)/* loop till event */ +- /*NOP*/; ++ ulong last = READ_CLK; ++ ulong clks; ++ ulong elapsed = 0; ++ ++ /* translate usec to clocks */ ++ clks = (usec / 1000) * CLK_PER_HZ; ++ clks += (usec % 1000) * CLK_PER_HZ / 1000; ++ ++ while (clks > elapsed) { ++ ulong now = READ_CLK; ++ if (now <= last) { ++ elapsed += last - now; ++ } else { ++ elapsed += TIMER_LOAD_VAL - (now - last); ++ } ++ last = now; ++ } + } + + void reset_timer_masked (void) +@@ -100,7 +103,7 @@ ulong get_timer_masked (void) + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and cause problems. + */ +- timestamp += lastdec + TIMER_LOAD_VAL - now; ++ timestamp += lastdec + (TIMER_LOAD_VAL / CLK_PER_HZ) - now; + } + lastdec = now; + +@@ -110,25 +113,7 @@ ulong get_timer_masked (void) + /* waits specified delay value and resets timestamp */ + void udelay_masked (unsigned long usec) + { +- ulong tmo; +- ulong endtime; +- signed long diff; +- +- if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ +- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ +- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ +- tmo /= 1000; /* finish normalize. */ +- } else { /* else small number, don't kill it prior to HZ multiply */ +- tmo = usec * CONFIG_SYS_HZ; +- tmo /= (1000*1000); +- } +- +- endtime = get_timer_masked () + tmo; +- +- do { +- ulong now = get_timer_masked (); +- diff = endtime - now; +- } while (diff >= 0); ++ __udelay(usec); + } + + /* +@@ -146,8 +131,5 @@ unsigned long long get_ticks(void) + */ + ulong get_tbclk (void) + { +- ulong tbclk; +- +- tbclk = CONFIG_SYS_HZ; +- return tbclk; ++ return CONFIG_SYS_HZ; + } +diff --git a/board/aspeed/ast2400/Makefile b/board/aspeed/ast2400/Makefile +index 1970ea1..fb77fc9 100644 +--- a/board/aspeed/ast2400/Makefile ++++ b/board/aspeed/ast2400/Makefile +@@ -11,7 +11,7 @@ + + include $(TOPDIR)/config.mk + +-LIB = $(obj)lib$(BOARD).a ++LIB = $(obj)lib$(BOARD).o + + COBJS := ast2400.o flash.o flash_spi.o pci.o crc32.o slt.o regtest.o vfun.o vhace.o crt.o videotest.o mactest.o hactest.o mictest.o + +@@ -28,17 +28,13 @@ OBJS := $(addprefix $(obj),$(COBJS)) + SOBJS := $(addprefix $(obj),$(SOBJS)) + + $(LIB): $(obj).depend $(OBJS) $(SOBJS) +- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +-clean: +- rm -f $(SOBJS) $(OBJS) +- +-distclean: clean +- rm -f $(LIB) core *.bak $(obj).depend ++######################################################################### + + # defines $(obj).depend target + include $(SRCTREE)/rules.mk + +-sinclude .depend ++sinclude $(obj).depend + + ######################################################################### +diff --git a/board/aspeed/ast2400/ast2400.c b/board/aspeed/ast2400/ast2400.c +index 65bccbe..55ed6b7 100644 +--- a/board/aspeed/ast2400/ast2400.c ++++ b/board/aspeed/ast2400/ast2400.c +@@ -10,6 +10,7 @@ + */ + + #include <common.h> ++#include <asm/io.h> + #include <command.h> + #include <pci.h> + +@@ -105,8 +106,8 @@ int dram_init (void) + { + DECLARE_GLOBAL_DATA_PTR; + +- gd->bd->bi_dram[0].start = PHYS_SDRAM_1; +- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ /* dram_init must store complete ramsize in gd->ram_size */ ++ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + + return 0; + } +@@ -190,6 +191,22 @@ int ast1070_calibration() + return 0; + } + ++static void watchdog_init() ++{ ++#ifdef CONFIG_ASPEED_ENABLE_WATCHDOG ++#define AST_WDT_BASE 0x1e785000 ++#define AST_WDT_CLK (1*1000*1000) /* 1M clock source */ ++ u32 reload = AST_WDT_CLK * CONFIG_ASPEED_WATCHDOG_TIMEOUT; ++ /* set the reload value */ ++ __raw_writel(reload, AST_WDT_BASE + 0x04); ++ /* magic word to reload */ ++ __raw_writel(0x4755, AST_WDT_BASE + 0x08); ++ /* start the watchdog with 1M clk src and reset whole chip */ ++ __raw_writel(0x33, AST_WDT_BASE + 0x0c); ++ printf("Watchdog: %us\n", CONFIG_ASPEED_WATCHDOG_TIMEOUT); ++#endif ++} ++ + int misc_init_r(void) + { + unsigned int reg, reg1, revision, chip_id, lpc_plus; +@@ -290,6 +307,8 @@ int misc_init_r(void) + if (getenv ("eeprom") == NULL) { + setenv ("eeprom", "y"); + } ++ ++ watchdog_init(); + } + + #ifdef CONFIG_PCI +@@ -302,3 +321,15 @@ void pci_init_board(void) + aspeed_init_pci(&hose); + } + #endif ++ ++int board_eth_init(bd_t *bis) ++{ ++ int ret = -1; ++#if defined(CONFIG_ASPEEDNIC) ++ ret = aspeednic_initialize(bis); ++#else ++ printf("No ETH, "); ++#endif ++ ++ return ret; ++} +diff --git a/board/aspeed/ast2400/config.mk b/board/aspeed/ast2400/config.mk +index 24ca09b..eddc3bf 100755 +--- a/board/aspeed/ast2400/config.mk ++++ b/board/aspeed/ast2400/config.mk +@@ -9,10 +9,5 @@ + # MA 02111-1307 USA + # + +-# ROM version +-#TEXT_BASE = 0xBFC00000 +- +-# RAM version +-TEXT_BASE = 0x40500000 +-#TEXT_BASE = 0x00000000 +-#TEXT_BASE = 0x00400000 ++# SPI flash is mapped to 0x00000000 initially ++CONFIG_SYS_TEXT_BASE = 0x00000000 +diff --git a/board/aspeed/ast2400/flash_spi.c b/board/aspeed/ast2400/flash_spi.c +index ad89254..339e531 100755 +--- a/board/aspeed/ast2400/flash_spi.c ++++ b/board/aspeed/ast2400/flash_spi.c +@@ -23,7 +23,7 @@ + */ + + /* The DEBUG define must be before common to enable debugging */ +-/* #define DEBUG */ ++/* #define DEBUG */ + + #include <common.h> + #include <asm/processor.h> +@@ -68,6 +68,7 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */ + /* Support Flash ID */ + #define STM25P64 0x172020 + #define STM25P128 0x182020 ++#define N25Q128 0x18ba20 + #define N25Q256 0x19ba20 + #define N25Q512 0x20ba20 + #define S25FL064A 0x160201 +@@ -581,7 +582,7 @@ static ulong flash_get_size (ulong base, int banknum) + ulID = ((ulong)ch[0]) | ((ulong)ch[1] << 8) | ((ulong)ch[2] << 16) ; + info->flash_id = ulID; + +- //printf("SPI Flash ID: %x \n", ulID); ++ printf("SPI Flash ID: %x \n", ulID); + + /* init default */ + info->iomode = IOMODEx1; +@@ -617,6 +618,19 @@ static ulong flash_get_size (ulong base, int banknum) + ReadClk = 50; + break; + ++ case N25Q128: ++ info->sector_count = 256; ++ info->size = 0x1000000; ++ erase_region_size = 0x10000; ++ info->readcmd = 0x0b; ++ info->dualport = 0; ++ info->dummybyte = 1; ++ info->buffersize = 256; ++ WriteClk = 50; ++ EraseClk = 20; ++ ReadClk = 50; ++ break; ++ + case N25Q256: + info->sector_count = 256; + info->size = 0x1000000; +@@ -1051,8 +1065,7 @@ AST2300 A0 SPI can't run faster than 50Mhz + } /* JDEC */ + } + +- debug ("erase_region_count = %d erase_region_size = %d\n", +- erase_region_count, erase_region_size); ++ debug ("erase_region_size = %d\n", erase_region_size); + + sector = base; + for (j = 0; j < info->sector_count; j++) { +diff --git a/board/aspeed/ast2400/platform.S b/board/aspeed/ast2400/platform.S +index 27e8f26..dd94da0 100644 +--- a/board/aspeed/ast2400/platform.S ++++ b/board/aspeed/ast2400/platform.S +@@ -334,7 +334,11 @@ set_MPLL: + str r1, [r0] + + /* Debug - UART console message */ +- ldr r0, =0x1e78400c ++ ldr r0, =0x1e6e2080 ++ ldr r1, =0xFFFF0000 @ enable UART3 and UART4 ++ str r1, [r0] ++ ++ ldr r0, =CONFIG_ASPEED_COM_LCR + mov r1, #0x83 + str r1, [r0] + +@@ -342,28 +346,38 @@ set_MPLL: + ldr r2, [r0] + mov r2, r2, lsr #12 + tst r2, #0x01 +- ldr r0, =0x1e784000 ++ ldr r0, =CONFIG_ASPEED_COM ++#if CONFIG_BAUDRATE == 115200 + moveq r1, #0x0D @ Baudrate 115200 + movne r1, #0x01 @ Baudrate 115200, div13 +-#if defined(CONFIG_DRAM_UART_38400) ++#endif ++#if CONFIG_BAUDRATE == 57600 ++ moveq r1, #0x1A @ Baudrate 57600 ++ movne r1, #0x02 @ Baudrate 57600, div13 ++#endif ++#if CONFIG_BAUDRATE == 38400 + moveq r1, #0x27 @ Baudrate 38400 + movne r1, #0x03 @ Baudrate 38400 , div13 + #endif ++#if CONFIG_BAUDRATE == 9600 ++ moveq r1, #0x9c @ Baudrate 9600 ++ movne r1, #0x0C @ Baudrate 9600 , div13 ++#endif + str r1, [r0] + +- ldr r0, =0x1e784004 ++ ldr r0, =CONFIG_ASPEED_COM_IER + mov r1, #0x00 + str r1, [r0] + +- ldr r0, =0x1e78400c ++ ldr r0, =CONFIG_ASPEED_COM_LCR + mov r1, #0x03 + str r1, [r0] + +- ldr r0, =0x1e784008 ++ ldr r0, =CONFIG_ASPEED_COM_IIR + mov r1, #0x07 + str r1, [r0] + +- ldr r0, =0x1e784000 ++ ldr r0, =CONFIG_ASPEED_COM + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' +@@ -575,7 +589,7 @@ delay_2: + ******************************************************************************/ + ddr3_init: + /* Debug - UART console message */ +- ldr r0, =0x1e784000 ++ ldr r0, =CONFIG_ASPEED_COM + mov r1, #0x33 @ '3' + str r1, [r0] + mov r1, #0x0D @ '\r' +@@ -764,7 +778,7 @@ delay3_4: + ******************************************************************************/ + ddr2_init: + /* Debug - UART console message */ +- ldr r0, =0x1e784000 ++ ldr r0, =CONFIG_ASPEED_COM + mov r1, #0x32 @ '2' + str r1, [r0] + mov r1, #0x0D @ '\r' +@@ -1416,7 +1430,7 @@ init_sram_start3: + *****************************************************************************/ + CBR0_START: + /* Debug - UART console message */ +- ldr r0, =0x1e784000 ++ ldr r0, =CONFIG_ASPEED_COM + mov r1, #0x43 @ 'C' + str r1, [r0] + mov r1, #0x42 @ 'B' +@@ -1454,7 +1468,7 @@ cbr0_next_dqidly: + bgt CBR0_END + + /* Debug - UART console message */ +- ldr r0, =0x1e784000 ++ ldr r0, =CONFIG_ASPEED_COM + and r1, r8, #0x07 + add r1, r1, #0x30 @ '0-7' + str r1, [r0] +@@ -1776,7 +1790,7 @@ delay_5: + *****************************************************************************/ + CBR1_START: + /* Debug - UART console message */ +- ldr r0, =0x1e784000 ++ ldr r0, =CONFIG_ASPEED_COM + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' +@@ -2057,7 +2071,7 @@ cbr1_set_result_end: + + CBR3_START: + /* Debug - UART console message */ +- ldr r0, =0x1e784000 ++ ldr r0, =CONFIG_ASPEED_COM + mov r1, #0x33 @ '3' + str r1, [r0] + /* Debug - UART console message */ +@@ -2276,7 +2290,7 @@ CBR3_END: + *****************************************************************************/ + CBR4_START: + /* Debug - UART console message */ +- ldr r0, =0x1e784000 ++ ldr r0, =CONFIG_ASPEED_COM + mov r1, #0x34 @ '4' + str r1, [r0] + /* Debug - UART console message */ +@@ -2556,7 +2570,7 @@ set_scratch: + str r1, [r0] + + /* Debug - UART console message */ +- ldr r0, =0x1e784000 ++ ldr r0, =CONFIG_ASPEED_COM + mov r1, #0x44 @ 'D' + str r1, [r0] + mov r1, #0x6F @ 'o' +@@ -2724,11 +2738,13 @@ ECC_Init_Flag: + orr r1, r1, #0x08 + str r1, [r0] + ++#ifndef CONFIG_ASPEED_ENABLE_JTAG + ldr r0, =0x1e6e2004 + ldr r1, [r0] + ldr r2, =0xFFBFFFFF @ Enable JTAG Master, solve ARM stucked by JTAG issue + and r1, r1, r2 + str r1, [r0] ++#endif + + ldr r0, =0x1e6e2048 @ Set MAC interface delay timing + ldr r1, =0x2255 +diff --git a/board/aspeed/ast2400/u-boot.lds b/board/aspeed/ast2400/u-boot.lds +deleted file mode 100755 +index ff0fe22..0000000 +--- a/board/aspeed/ast2400/u-boot.lds ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* +- * (C) Copyright 2004 +- * Wolfgang Denk, DENX Software Engineering, <wg@denx.de> +- * +- * See file CREDITS for list of people who contributed to this +- * project. +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- */ +- +-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +-/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +-OUTPUT_ARCH(arm) +-ENTRY(_start) +-SECTIONS +-{ +- . = 0x00000000; +- +- . = ALIGN(4); +- .text : +- { +- cpu/arm926ejs/start.o (.text) +- *(.text) +- } +- +- . = ALIGN(4); +- .rodata : { *(.rodata) } +- +- . = ALIGN(4); +- .data : { *(.data) } +- +- . = ALIGN(4); +- .got : { *(.got) } +- +- __u_boot_cmd_start = .; +- .u_boot_cmd : { *(.u_boot_cmd) } +- __u_boot_cmd_end = .; +- +- . = ALIGN(4); +- __bss_start = .; +- .bss : { *(.bss) } +- _end = .; +-} +diff --git a/boards.cfg b/boards.cfg +index 674896b..ce6bff1 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -72,7 +72,7 @@ mini2440 arm arm920t mini2440 friendl + VCMA9 arm arm920t vcma9 mpl s3c24x0 + smdk2410 arm arm920t - samsung s3c24x0 + omap1510inn arm arm925t - ti +-ast2400 arm arm926ejs ast2400 aspeed aspeed ++wedge arm arm926ejs ast2400 aspeed aspeed + integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap:CM926EJ_S + integratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp:CM924EJ_S + aspenite arm arm926ejs - Marvell armada100 +diff --git a/common/cmd_slt.c b/common/cmd_slt.c +index 9763692..6296416 100644 +--- a/common/cmd_slt.c ++++ b/common/cmd_slt.c +@@ -9,6 +9,7 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + ++#include <common.h> + #include <command.h> + + extern int pll_function(int argc, char *argv[]); +diff --git a/common/env_common.c b/common/env_common.c +index 906b41f..f5af537 100644 +--- a/common/env_common.c ++++ b/common/env_common.c +@@ -203,6 +203,9 @@ void env_relocate(void) + #else + bootstage_error(BOOTSTAGE_ID_NET_CHECKSUM); + set_default_env("!bad CRC"); ++#ifdef CONFIG_ASPEED_WRITE_DEFAULT_ENV ++ saveenv(); ++#endif + #endif + } else { + env_relocate_spec(); +diff --git a/common/image.c b/common/image.c +index f5ad097..2fc071b 100644 +--- a/common/image.c ++++ b/common/image.c +@@ -902,6 +902,11 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, + rd_data = image_get_data(rd_hdr); + rd_len = image_get_data_size(rd_hdr); + rd_load = image_get_load(rd_hdr); ++#ifdef CONFIG_ASPEED ++ /* Need to copy the initrd into RAM */ ++ memmove_wd((void *)rd_load, (void *)rd_data, rd_len, CHUNKSZ); ++ rd_data = rd_load; ++#endif + break; + #if defined(CONFIG_FIT) + case IMAGE_FORMAT_FIT: +diff --git a/drivers/net/aspeednic.c b/drivers/net/aspeednic.c +index 6b1ce05..d75ef67 100644 +--- a/drivers/net/aspeednic.c ++++ b/drivers/net/aspeednic.c +@@ -16,6 +16,7 @@ + #include <malloc.h> + #include <net.h> + #include <pci.h> ++#include <linux/mii.h> + + + /* +@@ -53,7 +54,6 @@ + #define MAC1_MDC (1 << 30) + #define MAC1_PHY_LINK (1 << 0) + #define MAC2_MDC_MDIO (1 << 2) +-#define MAC1_PHY_LINK (1 << 0) + #define MAC2_PHY_LINK (1 << 1) + #else + #define MAC2_MDC_MDIO (1 << 20) +@@ -69,6 +69,9 @@ unsigned int aspeednic_iobase[CONFIG_ASPEED_MAC_NUMBER] = { + 0x1E660000, 0x1E680000}; + #endif + ++/* PHY address */ ++static u8 g_phy_addr = 0; ++ + #undef DEBUG_SROM + #undef DEBUG_SROM2 + +@@ -249,6 +252,7 @@ struct de4x5_desc { + #define PHYID_RTL8201EL 0x001cc810 + #define PHYID_RTL8211 0x001cc910 + #define PHYID_BCM54612E 0x03625E6A ++#define PHYID_BCM54616S 0x03625D12 + + //NCSI define & structure + //NC-SI Command Packet +@@ -410,6 +414,12 @@ static void aspeednic_halt(struct eth_device* dev); + static void set_mac_address (struct eth_device* dev, bd_t* bis); + static void phy_write_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_Address, u16 PHY_Data); + static u16 phy_read_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_Address); ++#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) ++static int faraday_mdio_read(const char *devname, uint8_t addr, uint8_t reg, ++ uint16_t *value); ++static int faraday_mdio_write(const char *devname, uint8_t addr, uint8_t reg, ++ uint16_t value); ++#endif + static void set_mac_control_register(struct eth_device* dev); + + #if defined(CONFIG_E500) +@@ -456,7 +466,7 @@ void NCSI_Struct_Initialize(void) + + int aspeednic_initialize(bd_t *bis) + { +- int card_number = 0; ++ int card_number = CONFIG_ASPEED_MAC_CONFIG - 1; + unsigned int iobase, SCURegister; + struct eth_device* dev; + +@@ -538,7 +548,7 @@ int aspeednic_initialize(bd_t *bis) + + dev->iobase = iobase; + +- if (CONFIG_MAC1_PHY_SETTING >= 1) { ++ if (CONFIG_ASPEED_MAC_PHY_SETTING >= 1) { + //NCSI Struct Initialize + NCSI_Struct_Initialize(); + } +@@ -556,20 +566,22 @@ int aspeednic_initialize(bd_t *bis) + dev->recv = aspeednic_recv; + + /* Ensure we're not sleeping. */ +- if (CONFIG_MAC1_PHY_SETTING >= 1) { ++ if (CONFIG_ASPEED_MAC_PHY_SETTING >= 1) { + udelay(2000000); //2.0 sec + } + else { + udelay(10 * 1000); + } + +- + dev->init(dev, bis); + + eth_register(dev); + ++#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) ++ miiphy_register(dev->name, faraday_mdio_read, faraday_mdio_write); ++#endif + +- return card_number; ++ return 1; + } + + void Calculate_Checksum(unsigned char *buffer_base, int Length) +@@ -1114,11 +1126,37 @@ void Set_Link (struct eth_device* dev) + Retry = 0; + } + ++static void aspeednic_probe_phy(struct eth_device *dev) ++{ ++ u8 phy_addr; ++ u16 phy_id; ++ ++ /* assume it as 0 */ ++ g_phy_addr = 0; ++ ++ /* Check if the PHY is up to snuff..., max phy addr is 0x1f */ ++ for (phy_addr = 0; phy_addr <= 0x1f; phy_addr++) { ++ phy_id = phy_read_register(dev, MII_PHYSID1, phy_addr); ++ /* ++ * When it is unable to found PHY, ++ * the interface usually return 0xffff or 0x0000 ++ */ ++ if (phy_id != 0xffff && phy_id != 0x0) { ++ g_phy_addr = phy_addr; ++ break; ++ } ++ } ++ printf("%s: PHY at 0x%02x\n", dev->name, phy_addr); ++} ++ + static int aspeednic_init(struct eth_device* dev, bd_t* bis) + { + unsigned long i, Package_Found = 0, Channel_Found = 0, Re_Send = 0, Link_Status; + + RESET_DE4X5(dev); ++ ++ aspeednic_probe_phy(dev); ++ + set_mac_address (dev, bis); + set_mac_control_register (dev); + +@@ -1149,7 +1187,7 @@ static int aspeednic_init(struct eth_device* dev, bd_t* bis) + tx_new = 0; + rx_new = 0; + +- if (CONFIG_MAC1_PHY_SETTING >= 1) { ++ if (CONFIG_ASPEED_MAC_PHY_SETTING >= 1) { + //NCSI Start + //DeSelect Package/ Select Package + for (i = 0; i < 4; i++) { +@@ -1313,58 +1351,23 @@ static void aspeednic_halt(struct eth_device* dev) + + static void set_mac_address (struct eth_device* dev, bd_t* bis) + { +- unsigned char mac_address[6]; // 6 bytes mac address +- unsigned char ethaddress[20]; // string for setenv function +- char *s; +- int i, env; // env variable 0: eeprom, 1: environment parameters +- +- s = getenv ("eeprom"); +- env = (s && (*s == 'y')) ? 0 : 1; +- +- if (env == 0) { +- env = 1; +- eeprom_init (); +- eeprom_read (0xA0, 0, mac_address, 6); +- +- for (i = 0; i < 6; i++) { +- if (mac_address[i] != 0xFF) { +- env = 0; //Suppose not all 0xFF is valid +- } +- } ++ if (!eth_getenv_enetaddr_by_index("eth", 0, dev->enetaddr)) { ++ eth_random_enetaddr(dev->enetaddr); + } + +- if (env == 0) { // EEPROM +- sprintf (ethaddress, "%02X:%02X:%02X:%02X:%02X:%02X", mac_address[0], mac_address[1], mac_address[2], mac_address[3], mac_address[4], mac_address[5]); +- setenv ("ethaddr", ethaddress); +- OUTL(dev, ((mac_address[2] << 24) | (mac_address[3] << 16) | (mac_address[4] << 8) | mac_address[5]), MAC_LADR_REG); +- OUTL(dev, ((mac_address[0] << 8) | mac_address[1]), MAC_MADR_REG); +- if (CONFIG_MAC1_PHY_SETTING >= 1) { +- for (i = 0; i < 6; i++) { +- NCSI_Request.SA[i] = mac_address[i]; +- } +- } +- } +- else { // Environment Parameters +- OUTL(dev, ((bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) | (bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5]), MAC_LADR_REG); +- OUTL(dev, ((bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1]), MAC_MADR_REG); +- if (CONFIG_MAC1_PHY_SETTING >= 1) { +- for (i = 0; i < 6; i++) { +- NCSI_Request.SA[i] = bis->bi_enetaddr[i]; +- } +- } ++ OUTL(dev, ((dev->enetaddr[2] << 24) | (dev->enetaddr[3] << 16) ++ | (dev->enetaddr[4] << 8) | dev->enetaddr[5]), MAC_LADR_REG); ++ OUTL(dev, ((dev->enetaddr[0] << 8) | dev->enetaddr[1]), MAC_MADR_REG); ++ if (CONFIG_ASPEED_MAC_PHY_SETTING >= 1) { ++ memcpy(NCSI_Request.SA, dev->enetaddr, 6); + } +- + } + +- + static u16 phy_read_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_Address) + { + u32 Data, Status = 0, Loop_Count = 0, PHY_Ready = 1; + u16 Return_Data; + +-#ifdef REALTEK_PHY_SUPPORT +- PHY_Address = 0x01; +-#endif + //20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34 + OUTL(dev, (PHY_Register << 21) + (PHY_Address << 16) + MIIRD + MDC_CYCTHR, PHYCR_REG); + do { +@@ -1378,7 +1381,6 @@ static u16 phy_read_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_Ad + } while (Status == MIIRD); + + if (PHY_Ready == 0) { +- printf ("PHY NOT REDAY "); + return 0; + } + Data = INL (dev, PHYDATA_REG); +@@ -1392,9 +1394,6 @@ static void phy_write_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_ + { + u32 Status = 0, Loop_Count = 0, PHY_Ready = 1; + +-#ifdef REALTEK_PHY_SUPPORT +- PHY_Address = 0x01; +-#endif + //20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34 + OUTL(dev, PHY_Data, PHYDATA_REG); + OUTL(dev, (PHY_Register << 21) + (PHY_Address << 16) + MIIWR + MDC_CYCTHR, PHYCR_REG); +@@ -1407,31 +1406,66 @@ static void phy_write_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_ + break; + } + } while (Status == MIIWR); +- if (PHY_Ready == 0) { +- printf ("PHY NOT REDAY "); ++} ++ ++#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) ++ ++static int faraday_mdio_read( ++ const char *devname, uint8_t addr, uint8_t reg, uint16_t *value) ++{ ++ int ret = 0; ++ struct eth_device *dev; ++ ++ dev = eth_get_dev_by_name(devname); ++ if (dev == NULL) { ++ printf("%s: no such device\n", devname); ++ ret = -1; ++ } else { ++ *value = phy_read_register(dev, reg, addr); ++ } ++ ++ return ret; ++} ++ ++static int faraday_mdio_write( ++ const char *devname, uint8_t addr, uint8_t reg, uint16_t value) ++{ ++ int ret = 0; ++ struct eth_device *dev; ++ ++ dev = eth_get_dev_by_name(devname); ++ if (dev == NULL) { ++ printf("%s: no such device\n", devname); ++ ret = -1; ++ } else { ++ phy_write_register(dev, reg, addr, value); + } ++ ++ return ret; + } + ++#endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */ ++ + static void set_mac_control_register (struct eth_device* dev) + { + unsigned long MAC_CR_Register = 0; +- unsigned long Loop_Count = 0, PHY_Ready = 1, Chip_ID; ++ unsigned int Loop_Count = 0, PHY_Ready = 1, Chip_ID; + u16 PHY_Status, PHY_Speed, PHY_Duplex, Resolved_Status = 0, Advertise, Link_Partner; + +- if (CONFIG_MAC1_PHY_SETTING >= 1) { ++ if (CONFIG_ASPEED_MAC_PHY_SETTING >= 1) { + MAC_CR_Register = SPEED_100M_MODE_bit | RX_BROADPKT_bit | FULLDUP_bit | RXMAC_EN_bit | RXDMA_EN_bit | TXMAC_EN_bit | TXDMA_EN_bit | CRC_APD_bit; + } + else { + MAC_CR_Register = SPEED_100M_MODE_bit | FULLDUP_bit | RXMAC_EN_bit | RXDMA_EN_bit | TXMAC_EN_bit | TXDMA_EN_bit | CRC_APD_bit; + } + +- if (CONFIG_MAC1_PHY_SETTING != 2) { +- Chip_ID = ((phy_read_register (dev, 0x02, 0)) << 16); +- Chip_ID |= (phy_read_register (dev, 0x03, 0) & 0xffff); ++ if (CONFIG_ASPEED_MAC_PHY_SETTING != 2) { ++ Chip_ID = ((phy_read_register (dev, 0x02, g_phy_addr)) << 16); ++ Chip_ID |= (phy_read_register (dev, 0x03, g_phy_addr) & 0xffff); + if (((Chip_ID & PHYID_VENDOR_MASK) == PHYID_VENDOR_BROADCOM) || + ((Chip_ID & PHYID_VENDOR_MODEL_MASK) == PHYID_RTL8201EL)) { +- Advertise = phy_read_register (dev, 0x04, 0); +- Link_Partner = phy_read_register (dev, 0x05, 0); ++ Advertise = phy_read_register (dev, 0x04, g_phy_addr); ++ Link_Partner = phy_read_register (dev, 0x05, g_phy_addr); + Advertise = (Advertise & PHY_SPEED_DUPLEX_MASK); + Link_Partner = (Link_Partner & PHY_SPEED_DUPLEX_MASK); + if ((Advertise & Link_Partner) & PHY_100M_DUPLEX) { +@@ -1456,7 +1490,8 @@ static void set_mac_control_register (struct eth_device* dev) + //Max waiting time = (20 + 2)ms * 250(PHY_LOOP) = 5.5s + do { + udelay (20000); +- Resolved_Status = (phy_read_register (dev, 0x11, 0) & RESOLVED_BIT); ++ Resolved_Status = (phy_read_register (dev, 0x11, g_phy_addr) ++ & RESOLVED_BIT); + Loop_Count++; + if (Loop_Count >= PHY_LOOP) { + PHY_Ready = 0; +@@ -1466,7 +1501,7 @@ static void set_mac_control_register (struct eth_device* dev) + } while (Resolved_Status != RESOLVED_BIT); + + if (PHY_Ready == 1) { +- PHY_Status = phy_read_register (dev, 0x11, 0); ++ PHY_Status = phy_read_register (dev, 0x11, g_phy_addr); + PHY_Speed = (PHY_Status & PHY_SPEED_MASK) >> 14; + PHY_Duplex = (PHY_Status & PHY_DUPLEX_MASK) >> 13; + +@@ -1485,40 +1520,54 @@ static void set_mac_control_register (struct eth_device* dev) + } + //LED Control + // if (Chip_ID == 0x1C) { +-// PHY_Status = phy_read_register (dev, 0x18, 0); +-// phy_write_register (dev, 0x18, 0, (PHY_Status | 0x09)); ++// PHY_Status = phy_read_register (dev, 0x18, g_phy_addr); ++// phy_write_register (dev, 0x18, g_phy_addr, (PHY_Status | 0x09)); + // } + //LED Control D[0], D[6] + // if (Chip_ID == 0x141) { +-// PHY_Status = phy_read_register (dev, 0x18, 0); +-// phy_write_register (dev, 0x18, 0, ((PHY_Status & ~(0x41)) | 0x01)); ++// PHY_Status = phy_read_register (dev, 0x18, g_phy_addr); ++// phy_write_register (dev, 0x18, g_phy_addr, ((PHY_Status & ~(0x41)) | 0x01)); + // } + } +- else if (Chip_ID == PHYID_BCM54612E ) { +- phy_write_register ( dev, 0x1C, 1, 0x8C00 ); // Disable GTXCLK Clock Delay Enable +- phy_write_register ( dev, 0x18, 1, 0xF0E7 ); // Disable RGMII RXD to RXC Skew +- +- Advertise = phy_read_register (dev, 0x04, 1); +- Link_Partner = phy_read_register (dev, 0x05, 1); +- Advertise = (Advertise & PHY_SPEED_DUPLEX_MASK); +- Link_Partner = (Link_Partner & PHY_SPEED_DUPLEX_MASK); +- if ((Advertise & Link_Partner) & PHY_100M_DUPLEX) { +- MAC_CR_Register |= SPEED_100M_MODE_bit; +- MAC_CR_Register |= FULLDUP_bit; ++ else if (Chip_ID == PHYID_BCM54612E || Chip_ID == PHYID_BCM54616S) { ++ // Disable GTXCLK Clock Delay Enable ++ phy_write_register( dev, 0x1C, g_phy_addr, 0x8C00); ++ // Disable RGMII RXD to RXC Skew ++ phy_write_register( dev, 0x18, g_phy_addr, 0xF0E7); ++ // First Switch shadow register selector ++ phy_write_register(dev, 0x1C, g_phy_addr, 0x2000); ++ PHY_Status = phy_read_register(dev, 0x1C, g_phy_addr); ++ PHY_Duplex = (PHY_Status & 0x0080); ++ switch (PHY_Status & 0x0018) { ++ case 0x0000: ++ PHY_Speed = SPEED_1000M; ++ break; ++ case 0x0008: ++ PHY_Speed = SPEED_100M; ++ break; ++ case 0x0010: ++ PHY_Speed = SPEED_10M; ++ break; ++ default: ++ PHY_Speed = SPEED_100M; ++ break; + } +- else if ((Advertise & Link_Partner) & PHY_100M_HALF) { +- MAC_CR_Register |= SPEED_100M_MODE_bit; +- MAC_CR_Register &= ~FULLDUP_bit; ++ if (PHY_Speed == SPEED_1000M) { ++ MAC_CR_Register |= GMAC_MODE_bit; ++ } else { ++ MAC_CR_Register &= ~GMAC_MODE_bit; ++ if (PHY_Speed == SPEED_100M) { ++ MAC_CR_Register |= SPEED_100M_MODE_bit; ++ } else { ++ MAC_CR_Register &= ~SPEED_100M_MODE_bit; ++ } + } +- else if ((Advertise & Link_Partner) & PHY_10M_DUPLEX) { +- MAC_CR_Register &= ~SPEED_100M_MODE_bit; ++ if (PHY_Duplex) { + MAC_CR_Register |= FULLDUP_bit; +- } +- else if ((Advertise & Link_Partner) & PHY_10M_HALF) { +- MAC_CR_Register &= ~SPEED_100M_MODE_bit; ++ } else { + MAC_CR_Register &= ~FULLDUP_bit; + } +- }else { ++ } else { + printf("Unknow Chip_ID %x\n",Chip_ID); + } + } +diff --git a/include/configs/wedge.h b/include/configs/wedge.h +new file mode 100644 +index 0000000..6bb7639 +--- /dev/null ++++ b/include/configs/wedge.h +@@ -0,0 +1,350 @@ ++/* ++ * Copyright 2004-present Facebook. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/* Uncommit the following line to enable JTAG in u-boot */ ++//#define CONFIG_ASPEED_ENABLE_JTAG ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */ ++#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */ ++//#define CONFIG_FPGA_ASPEED 1 ++#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */ ++#define CONFIG_ASPEED 1 ++#define CONFIG_AST2400 1 ++//#define CONFIG_AST1070 1 ++//#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/ ++#define CONFIG_FLASH_SPI ++//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */ ++#undef CONFIG_2SPIFLASH ++#undef CONFIG_ASPEED_SLT ++#define CONFIG_FLASH_AST2300 ++//#define CONFIG_FLASH_AST2300_DMA ++//#define CONFIG_FLASH_SPIx2_Dummy ++//#define CONFIG_FLASH_SPIx4_Dummy ++#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */ ++ ++//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ ++#define CONFIG_MISC_INIT_R ++ ++/* ++ * DRAM Config ++ * ++ * 1. DRAM Size // ++ * CONFIG_DRAM_512MBIT // 512M bit ++ * CONFIG_DRAM_1GBIT // 1G bit (default) ++ * CONFIG_DRAM_2GBIT // 2G bit ++ * CONFIG_DRAM_4GBIT // 4G bit ++ * 2. DRAM Speed // ++ * CONFIG_DRAM_336 // 336MHz (DDR-667) ++ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default) ++ * 3. VGA Mode ++ * CONFIG_CRT_DISPLAY // define to disable VGA function ++ * 4. ECC Function enable ++ * CONFIG_DRAM_ECC // define to enable ECC function ++ * 5. UART Debug Message ++ * CONFIG_DRAM_UART_OUT // enable output message at UART5 ++ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200 ++ */ ++ ++//1. DRAM Size ++//#define CONFIG_DRAM_512MBIT ++#define CONFIG_DRAM_1GBIT ++//#define CONFIG_DRAM_2GBIT ++//#define CONFIG_DRAM_4GBIT ++//2. DRAM Speed ++//#define CONFIG_DRAM_336 ++#define CONFIG_DRAM_408 ++//3. VGA Mode ++//#define CONFIG_CRT_DISPLAY ++//4. ECC Function enable ++//#define CONFIG_DRAM_ECC ++//5. UART Debug Message ++#define CONFIG_DRAM_UART_OUT ++//#define CONFIG_DRAM_UART_38400 ++ ++ ++ ++/* ++ * Environment Config ++ */ ++#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_INITRD_TAG 1 ++#define CONFIG_BOOTARGS "debug console=ttyS2,9600n8 root=/dev/ram rw" ++#define CONFIG_UPDATE "tftp 40800000 ast2400.scr; so 40800000'" ++ ++#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ ++#define CONFIG_AUTOBOOT_KEYED ++#define CONFIG_AUTOBOOT_PROMPT \ ++ "autoboot in %d seconds (stop with 'Delete' key)...\n", bootdelay ++#define CONFIG_AUTOBOOT_STOP_STR "\x1b\x5b\x33\x7e" /* 'Delete', ESC[3~ */ ++#define CONFIG_ZERO_BOOTDELAY_CHECK ++ ++#ifdef CONFIG_FLASH_AST2300 ++#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000" ++#else ++#ifdef CONFIG_SYS_FLASH_CFI ++#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000" ++#else ++#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000" ++#endif ++#endif ++#define CONFIG_BOOTFILE "all.bin" ++#define CONFIG_ENV_OVERWRITE ++ ++/* ++ * Command line configuration. ++ */ ++#include <config_cmd_default.h> ++ ++#define CONFIG_CMD_DFL ++#define CONFIG_CMD_ENV ++#define CONFIG_CMD_FLASH ++#define CONFIG_CMD_MII ++#define CONFIG_CMD_NET ++#define CONFIG_CMD_PING ++#define CONFIG_CMD_I2C ++#define CONFIG_CMD_EEPROM ++#define CONFIG_CMD_NETTEST ++#define CONFIG_CMD_SLT ++ ++/* ++ * CPU Setting ++ */ ++#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */ ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024) ++#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++ ++/* ++ * Stack sizes, The stack sizes are set up in start.S using the settings below ++ */ ++#define CONFIG_STACKSIZE (128*1024) /* regular stack */ ++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ ++ ++/* ++ * Memory Configuration ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ ++#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */ ++#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ ++ ++#define CONFIG_SYS_SDRAM_BASE 0x40000000 ++ ++/* ++ * FLASH Configuration ++ */ ++#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */ ++ ++#ifdef CONFIG_FLASH_AST2300 ++#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */ ++#else ++#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */ ++#endif ++ ++#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 ++#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 } ++ ++#define CONFIG_SYS_MAX_FLASH_BANKS 1 ++#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */ ++ ++#define CONFIG_ENV_IS_IN_FLASH 1 ++#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */ ++#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ ++ ++#define CONFIG_SYS_FLASH_CFI_AMD_RESET ++#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE ++ ++#else /* SPI Flash */ ++ ++#ifdef CONFIG_FLASH_AST2300 ++#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */ ++#else ++#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */ ++#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */ ++#define PHYS_FLASH_2_BASE 0x10000000 ++#endif ++ ++#ifdef CONFIG_2SPIFLASH ++#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE ++#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } ++#define CONFIG_SYS_MAX_FLASH_BANKS 2 ++#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */ ++ ++#define CONFIG_ENV_IS_IN_FLASH 1 ++#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */ ++#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */ ++#else ++#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 ++#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 } ++#define CONFIG_SYS_MAX_FLASH_BANKS 1 ++#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */ ++ ++#define CONFIG_ENV_IS_IN_FLASH 1 ++#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */ ++#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ ++#define CONFIG_ASPEED_WRITE_DEFAULT_ENV ++#endif ++ ++#endif ++ ++#define __LITTLE_ENDIAN 1 ++ ++#define CONFIG_MONITOR_BASE TEXT_BASE ++#define CONFIG_MONITOR_LEN (192 << 10) ++ ++/* timeout values are in ticks */ ++#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ ++#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CONFIG_SYS_LONGHELP /* undef to save memory */ ++ ++#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */ ++#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ ++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ ++#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ ++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */ ++#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */ ++ ++#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */ ++ ++#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */ ++#define CONFIG_SYS_HZ 1000 ++#define CONFIG_ASPEED_TIMER_CLK (1*1000*1000) /* use external clk (1M) */ ++ ++/* ++ * Serial Configuration ++ */ ++#define CONFIG_SYS_NS16550 ++#define CONFIG_SYS_NS16550_SERIAL ++#define CONFIG_SYS_NS16550_MEM32 ++#define CONFIG_SYS_NS16550_REG_SIZE -4 ++#define CONFIG_SYS_NS16550_CLK 24000000 ++#define CONFIG_SYS_NS16550_COM1 0x1e783000 ++#define CONFIG_SYS_NS16550_COM2 0x1e784000 ++#define CONFIG_SYS_NS16550_COM3 0x1e78e000 ++#define CONFIG_SYS_LOADS_BAUD_CHANGE ++#define CONFIG_CONS_INDEX 3 ++#define CONFIG_BAUDRATE 9600 ++#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++#define CONFIG_ASPEED_COM 0x1e78e000 // COM3 ++#define CONFIG_ASPEED_COM_IER (CONFIG_ASPEED_COM + 0x4) ++#define CONFIG_ASPEED_COM_IIR (CONFIG_ASPEED_COM + 0x8) ++#define CONFIG_ASPEED_COM_LCR (CONFIG_ASPEED_COM + 0xc) ++ ++/* ++ * USB device configuration ++ */ ++/* ++#define CONFIG_USB_DEVICE 1 ++#define CONFIG_USB_TTY 1 ++ ++#define CONFIG_USBD_VENDORID 0x1234 ++#define CONFIG_USBD_PRODUCTID 0x5678 ++#define CONFIG_USBD_MANUFACTURER "Siemens" ++#define CONFIG_USBD_PRODUCT_NAME "SX1" ++*/ ++ ++/* ++ * I2C configuration ++ */ ++#define CONFIG_HARD_I2C ++#define CONFIG_SYS_I2C_SPEED 100000 ++#define CONFIG_SYS_I2C_SLAVE 1 ++#define CONFIG_DRIVER_ASPEED_I2C ++ ++/* ++* EEPROM configuration ++*/ ++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 ++#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0 ++ ++#define __BYTE_ORDER __LITTLE_ENDIAN ++#define __LITTLE_ENDIAN_BITFIELD ++ ++/* ++ * NIC configuration ++ */ ++#define CONFIG_ASPEEDNIC ++#define CONFIG_NET_MULTI ++#define CONFIG_MAC1_PHY_LINK_INTERRUPT ++#define CONFIG_MAC2_ENABLE ++#define CONFIG_MAC2_PHY_LINK_INTERRUPT ++/* ++*------------------------------------------------------------------------------- ++* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration. ++* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to ++* inform kernel driver. ++* The meanings of the 2 bits are: ++* 00(0): Dedicated PHY ++* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA ++* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly ++* 11: Reserved ++* ++* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot ++* 0: Dedicated PHY ++* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA ++* 2: ASPEED's MAC is connected to NC-SI PHY chip directly ++* 3: Reserved ++*------------------------------------------------------------------------------- ++*/ ++#define CONFIG_MAC1_PHY_SETTING 0 ++#define CONFIG_MAC2_PHY_SETTING 0 ++#define CONFIG_ASPEED_MAC_NUMBER 2 ++#define CONFIG_ASPEED_MAC_CONFIG 2 // config MAC2 ++#define _PHY_SETTING_CONCAT(mac) CONFIG_MAC##mac##_PHY_SETTING ++#define _GET_MAC_PHY_SETTING(mac) _PHY_SETTING_CONCAT(mac) ++#define CONFIG_ASPEED_MAC_PHY_SETTING \ ++ _GET_MAC_PHY_SETTING(CONFIG_ASPEED_MAC_CONFIG) ++#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255 ++#define CONFIG_RANDOM_MACADDR ++//#define CONFIG_GATEWAYIP 192.168.0.1 ++//#define CONFIG_NETMASK 255.255.255.0 ++//#define CONFIG_IPADDR 192.168.0.45 ++//#define CONFIG_SERVERIP 192.168.0.81 ++ ++/* ++ * SLT ++ */ ++/* ++#define CONFIG_SLT ++#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST) ++*/ ++ ++#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) ++ ++#define CONFIG_ASPEED_ENABLE_WATCHDOG ++#define CONFIG_ASPEED_WATCHDOG_TIMEOUT (5*60) // 5m ++ ++#endif /* __CONFIG_H */ |