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authorTian Fang <tfang@fb.com>2015-03-09 22:53:57 -0700
committerTian Fang <tfang@fb.com>2015-03-09 22:53:57 -0700
commit2a51b7c1c2165ddb188c511e192b75f0aa0fbead (patch)
treebb42aeac00a8b986c325cd70d5cca6c13bc0c23a
downloadast2050-yocto-openbmc-2a51b7c1c2165ddb188c511e192b75f0aa0fbead.zip
ast2050-yocto-openbmc-2a51b7c1c2165ddb188c511e192b75f0aa0fbead.tar.gz
Initial open source release of OpenBMC
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diff --git a/.gitignore b/.gitignore
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diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
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+++ b/CONTRIBUTING.md
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+CONTRIBUTING.md
+
+# Contributing to OpenBMC
+We want to make contributing to this project as easy and transparent as
+possible.
+
+## Our Development Process
+We develop on a private branch internally at Facebook. We regularly update
+this github project with the changes from the internal repo. External pull
+requests are cherry-picked into our repo and then pushed back out.
+
+## Pull Requests
+We actively welcome your pull requests.
+1. Fork the repo and create your branch from `master`.
+2. If you've added code that should be tested, add tests
+3. If you've changed APIs, update the documentation.
+4. Ensure the test suite passes.
+5. Make sure your code lints.
+6. If you haven't already, complete the Contributor License Agreement ("CLA").
+
+## Contributor License Agreement ("CLA")
+In order to accept your pull request, we need you to submit a CLA. You only need
+to do this once to work on any of Facebook's open source projects.
+
+Complete your CLA here: <https://code.facebook.com/cla>
+
+## Issues
+We use GitHub issues to track public bugs. Please ensure your description is
+clear and has sufficient instructions to be able to reproduce the issue.
+
+Facebook has a [bounty program](https://www.facebook.com/whitehat/) for the safe
+disclosure of security bugs. In those cases, please go through the process
+outlined on that page and do not file a public issue.
+
+## Coding Style
+* 2 spaces for indentation rather than tabs
+* 80 character line length
diff --git a/README.md b/README.md
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+# OpenBMC
+
+OpenBMC is an open software framework to build a complete Linux image for a Board Management Controller (BMC).
+
+OpenBMC uses [Yocto](https://www.yoctoproject.org) as the underlying building framework.
+
+## Contents
+
+This repository includes 3 set of layers:
+
+* **OpenBMC Common Layer** - Common packages and recipes can be used in different types of BMC.
+* **BMC System-on-Chip (SoC) Layer** - SoC specific drivers and tools. This layer includes the bootloader (u-boot) and the Linux kernel. Both the bootloader and Linux kernel shall include the hardware drivers specific for the SoC.
+* **Board Specific Layer** - Board specific drivers, configurations, and tools. This layer defines how to configure the image. It also defines what packages to be installed for an OpenBMC image for this board. Any board specific initialization and tools are also included in this layer.
+
+## File structure
+
+Yocto naming pattern is used in this repository. `meta-layer` is used to name a layer. And `recipe-abc` is used to name a recipe.
+
+The recipes for OpenBMC common layer should be in `meta-openbmc/common`.
+
+BMC SoC layer and board specific layer are grouped together based on the vendor/manufacturer name. For example, all Facebook boards specific code should be in `meta-openbmc/meta-facebook`. And `meta-openbmc/meta-aspeed` includes source code for Aspeed SoCs.
+
+## How to build
+
+* Step 0 - Set up the build environment based on the Yocto project [document](http://www.yoctoproject.org/docs/1.6.1/yocto-project-qs/yocto-project-qs.html).
+
+* Step 1 - Clone Yocto repository.
+```
+$ git clone -b daisy https://git.yoctoproject.org/git/poky
+```
+
+* Step 2 - Clone Openembedded and OpenBMC repositories, in the new created `poky` directory,
+```
+$ cd poky
+$ git clone -b daisy https://github.com/openembedded/meta-openembedded.git
+$ git clone git@github.com:facebook/openbmc.git meta-openbmc
+```
+
+* Step 3 - Initialize a build directory. In `poky` directory,
+
+```
+$ export TEMPLATECONF=meta-openbmc/meta-facebook/meta-wedge/conf
+$ source oe-init-build-env
+```
+
+After this step, you will be dropped into a build directory, `poky/build`.
+
+* Step 4 - Start the build within the build directory, `poky/build`.
+
+```
+$ bitbake wedge-image
+```
+
+The build process automatically fetches all necessary packages and build the complete image. The final build results are in `poky/build/tmp/deploy/images/wedge`.
+
+* u-boot.bin - This is the u-boot image for the board.
+* uImage - This the Linux kernel for the board.
+* wedge-image-wedge.cpio.lzma.u-boot - This is the rootfs for the board
+* flash-wedge - This is the complete flash image including u-boot, kernel, and the rootfs.
+
+# How can I contribute
+
+If you have an application that can be used by different BMCs, you can contribute your application to the OpenBMC common layer.
+
+If you are a BMC SoC vendor, you can contribute your SoC specific drivers to the BMC SoC layer.
+
+If you are a board vendor, you can contribute your board specific configurations and tools to the Board specific layer. If the board uses a new BMC SoC that is not part of the BMC SoC layer, the SoC specific driver contribution to the BMC SoC layer is also required.
diff --git a/common/recipes-connectivity/dhcp/dhcp_%.bbappend b/common/recipes-connectivity/dhcp/dhcp_%.bbappend
new file mode 100644
index 0000000..6dc6962
--- /dev/null
+++ b/common/recipes-connectivity/dhcp/dhcp_%.bbappend
@@ -0,0 +1,3 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+SRC_URI += "file://dhclient.conf"
diff --git a/common/recipes-connectivity/dhcp/files/dhclient.conf b/common/recipes-connectivity/dhcp/files/dhclient.conf
new file mode 100644
index 0000000..8dea59b
--- /dev/null
+++ b/common/recipes-connectivity/dhcp/files/dhclient.conf
@@ -0,0 +1,52 @@
+# Configuration file for /sbin/dhclient, which is included in Debian's
+# dhcp3-client package.
+#
+# This is a sample configuration file for dhclient. See dhclient.conf's
+# man page for more information about the syntax of this file
+# and a more comprehensive list of the parameters understood by
+# dhclient.
+#
+# Normally, if the DHCP server provides reasonable information and does
+# not leave anything out (like the domain name, for example), then
+# few changes must be made to this file, if any.
+#
+
+#send host-name "andare.fugue.com";
+#send dhcp-client-identifier 1:0:a0:24:ab:fb:9c;
+#send dhcp-lease-time 3600;
+#supersede domain-name "fugue.com home.vix.com";
+#prepend domain-name-servers 127.0.0.1;
+request subnet-mask, broadcast-address, time-offset, routers,
+ domain-name, domain-name-servers, host-name,
+ netbios-name-servers, netbios-scope;
+#require subnet-mask, domain-name-servers;
+# 25 seconds (default 300s) to get the lease
+timeout 25;
+# if not, retry in 55 seconds (default 5m)
+retry 55;
+#reboot 10;
+#select-timeout 5;
+#initial-interval 2;
+#script "/etc/dhcp3/dhclient-script";
+#media "-link0 -link1 -link2", "link0 link1";
+#reject 192.33.137.209;
+
+#alias {
+# interface "eth0";
+# fixed-address 192.5.5.213;
+# option subnet-mask 255.255.255.255;
+#}
+
+#lease {
+# interface "eth0";
+# fixed-address 192.33.137.200;
+# medium "link0 link1";
+# option host-name "andare.swiftmedia.com";
+# option subnet-mask 255.255.255.0;
+# option broadcast-address 192.33.137.255;
+# option routers 192.33.137.250;
+# option domain-name-servers 127.0.0.1;
+# renew 2 2000/1/12 00:00:01;
+# rebind 2 2000/1/12 00:00:01;
+# expire 2 2000/1/12 00:00:01;
+#}
diff --git a/common/recipes-connectivity/openssh/files/init b/common/recipes-connectivity/openssh/files/init
new file mode 100644
index 0000000..e7484a7
--- /dev/null
+++ b/common/recipes-connectivity/openssh/files/init
@@ -0,0 +1,160 @@
+#! /bin/sh
+set -e
+
+# source function library
+. /etc/init.d/functions
+
+# /etc/init.d/ssh: start and stop the OpenBSD "secure shell" daemon
+
+test -x /usr/sbin/sshd || exit 0
+( /usr/sbin/sshd -\? 2>&1 | grep -q OpenSSH ) 2>/dev/null || exit 0
+
+# /etc/default/ssh may set SYSCONFDIR and SSHD_OPTS
+if test -f /etc/default/ssh; then
+ . /etc/default/ssh
+fi
+
+[ -z "$SYSCONFDIR" ] && SYSCONFDIR=/etc/ssh
+mkdir -p $SYSCONFDIR
+
+HOST_KEY_RSA=$SYSCONFDIR/ssh_host_rsa_key
+HOST_KEY_DSA=$SYSCONFDIR/ssh_host_dsa_key
+HOST_KEY_ECDSA=$SYSCONFDIR/ssh_host_ecdsa_key
+HOST_KEY_ED25519=$SYSCONFDIR/ssh_host_ed25519_key
+
+check_for_no_start() {
+ # forget it if we're trying to start, and /etc/ssh/sshd_not_to_be_run exists
+ if [ -e $SYSCONFDIR/sshd_not_to_be_run ]; then
+ echo "OpenBSD Secure Shell server not in use ($SYSCONFDIR/sshd_not_to_be_run)"
+ exit 0
+ fi
+}
+
+check_privsep_dir() {
+ # Create the PrivSep empty dir if necessary
+ if [ ! -d /var/run/sshd ]; then
+ mkdir /var/run/sshd
+ chmod 0755 /var/run/sshd
+ fi
+}
+
+check_config() {
+ /usr/sbin/sshd -t || exit 1
+}
+
+KEYFILES_DIR="/mnt/data/etc/ssh"
+
+prepare_keyfiles_dir() {
+ if [ ! -d "$KEYFILES_DIR" ]; then
+ # remove it in case someone create a file with the same name
+ rm -rf "$KEYFILES_DIR" > /dev/null 2>&1
+ mkdir -p "$KEYFILES_DIR"
+ fi
+}
+
+get_keyfile() {
+ filename=$(basename $1)
+ if [ -f "$KEYFILES_DIR/$filename" ]; then
+ rm -rf $1 > /dev/null 2>&1
+ ln -s "$KEYFILES_DIR/$filename" $1
+ fi
+}
+
+save_keyfile() {
+ filename=$(basename $1)
+ if [ -d "$KEYFILES_DIR" ]; then
+ mv -f $1 "$KEYFILES_DIR/$filename" > /dev/null 2>&1
+ ln -s "$KEYFILES_DIR/$filename" $1
+ fi
+}
+
+check_keys() {
+ # prepare for the permanent storage
+ prepare_keyfiles_dir
+ # create keys if necessary
+ get_keyfile $HOST_KEY_RSA
+ get_keyfile $HOST_KEY_RSA.pub
+ if [ ! -f $HOST_KEY_RSA ]; then
+ echo " generating ssh RSA key..."
+ ssh-keygen -q -f $HOST_KEY_RSA -N '' -t rsa
+ save_keyfile $HOST_KEY_RSA
+ save_keyfile $HOST_KEY_RSA.pub
+ fi
+
+ get_keyfile $HOST_KEY_ECDSA
+ get_keyfile $HOST_KEY_ECDSA.pub
+ if [ ! -f $HOST_KEY_ECDSA ]; then
+ echo " generating ssh ECDSA key..."
+ ssh-keygen -q -f $HOST_KEY_ECDSA -N '' -t ecdsa
+ save_keyfile $HOST_KEY_ECDSA
+ save_keyfile $HOST_KEY_ECDSA.pub
+ fi
+
+ get_keyfile $HOST_KEY_DSA
+ get_keyfile $HOST_KEY_DSA.pub
+ if [ ! -f $HOST_KEY_DSA ]; then
+ echo " generating ssh DSA key..."
+ ssh-keygen -q -f $HOST_KEY_DSA -N '' -t dsa
+ save_keyfile $HOST_KEY_DSA
+ save_keyfile $HOST_KEY_DSA.pub
+ fi
+
+ get_keyfile $HOST_KEY_ED25519
+ get_keyfile $HOST_KEY_ED25519.pub
+ if [ ! -f $HOST_KEY_ED25519 ]; then
+ echo " generating ssh ED25519 key..."
+ ssh-keygen -q -f $HOST_KEY_ED25519 -N '' -t ed25519
+ save_keyfile $HOST_KEY_ED25519
+ save_keyfile $HOST_KEY_ED25519.pub
+ fi
+}
+
+export PATH="${PATH:+$PATH:}/usr/sbin:/sbin"
+
+case "$1" in
+ start)
+ check_for_no_start
+ echo "Starting OpenBSD Secure Shell server: sshd"
+ check_keys
+ check_privsep_dir
+ start-stop-daemon -S -x /usr/sbin/sshd -- $SSHD_OPTS
+ echo "done."
+ ;;
+ stop)
+ echo -n "Stopping OpenBSD Secure Shell server: sshd"
+ start-stop-daemon -K -x /usr/sbin/sshd
+ echo "."
+ ;;
+
+ reload|force-reload)
+ check_for_no_start
+ check_keys
+ check_config
+ echo -n "Reloading OpenBSD Secure Shell server's configuration"
+ start-stop-daemon -K -s 1 -x /usr/sbin/sshd
+ echo "."
+ ;;
+
+ restart)
+ check_keys
+ check_config
+ echo -n "Restarting OpenBSD Secure Shell server: sshd"
+ start-stop-daemon -K --oknodo -x /usr/sbin/sshd
+ check_for_no_start
+ check_privsep_dir
+ sleep 2
+ start-stop-daemon -S -x /usr/sbin/sshd -- $SSHD_OPTS
+ echo "."
+ ;;
+
+ status)
+ status /usr/sbin/sshd
+ exit $?
+ ;;
+
+ *)
+ echo "Usage: /etc/init.d/ssh {start|stop|status|reload|force-reload|restart}"
+ exit 1
+esac
+
+exit 0
diff --git a/common/recipes-connectivity/openssh/openssh_6.5%.bbappend b/common/recipes-connectivity/openssh/openssh_6.5%.bbappend
new file mode 100644
index 0000000..60b164b
--- /dev/null
+++ b/common/recipes-connectivity/openssh/openssh_6.5%.bbappend
@@ -0,0 +1,3 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+SRC_URI += "file://init"
diff --git a/common/recipes-core/base-files/base-files_%.bbappend b/common/recipes-core/base-files/base-files_%.bbappend
new file mode 100644
index 0000000..340ad2c
--- /dev/null
+++ b/common/recipes-core/base-files/base-files_%.bbappend
@@ -0,0 +1,30 @@
+BASEFILESISSUEINSTALL = "do_install_bmc_issue"
+
+DISTRO_HOSTNAME = "bmc"
+
+do_install_bmc_issue () {
+ if [ "${DISTRO_HOSTNAME}" != "" ]; then
+ echo ${DISTRO_HOSTNAME} > ${D}${sysconfdir}/hostname
+ else
+ echo ${MACHINE} > ${D}${sysconfdir}/hostname
+ fi
+
+ # found out the source dir
+ dir=$(pwd)
+ while [ -n "$dir" -a "$dir" != "/" -a ! -d "$dir/meta-openbmc/.git" ]; do
+ dir=$(dirname $dir)
+ done
+
+ if [ -d "$dir/meta-aspeed/.git" ]; then
+ srcdir="$dir/meta-aspeed"
+ srcdir_git="${srcdir}/.git"
+ version=$(git --git-dir=${srcdir_git} --work-tree=${srcdir} describe --dirty 2> /dev/null)
+ else
+ version=""
+ fi
+
+ echo "Open BMC Release ${version} \\n \\l" > ${D}${sysconfdir}/issue
+ echo >> ${D}${sysconfdir}/issue
+ echo "Open BMC Release ${version} %h" > ${D}${sysconfdir}/issue.net
+ echo >> ${D}${sysconfdir}/issue.net
+}
diff --git a/common/recipes-core/i2c-tools/i2c-tools_3.1.1.bb b/common/recipes-core/i2c-tools/i2c-tools_3.1.1.bb
new file mode 100644
index 0000000..6743e3f
--- /dev/null
+++ b/common/recipes-core/i2c-tools/i2c-tools_3.1.1.bb
@@ -0,0 +1,38 @@
+DESCRIPTION = "i2c tools"
+SECTION = "base"
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = "file://COPYING;md5=751419260aa954499f7abaabaa882bbe"
+
+SRCREV = "6235"
+SRC_URI = "svn://lm-sensors.org/svn/i2c-tools/branches/;protocol=http;module=i2c-tools-3.1 \
+ "
+
+S = "${WORKDIR}/i2c-tools-3.1"
+
+i2ctools = "i2cdetect \
+ i2cdump \
+ i2cget \
+ i2cset \
+ "
+
+eepromtools = "eepromer \
+ eeprom \
+ eeprog \
+ "
+
+do_compile() {
+ make -C eepromer
+ make
+}
+
+do_install() {
+ mkdir -p ${D}/${bindir}
+ for f in ${i2ctools}; do
+ install -m 755 tools/$f ${D}/${bindir}/$f
+ done
+ for f in ${eepromtools}; do
+ install -m 755 eepromer/$f ${D}/${bindir}/$f
+ done
+}
+
+FILES_${PN} = "${bindir}"
diff --git a/common/recipes-core/init-ifupdown/files/init b/common/recipes-core/init-ifupdown/files/init
new file mode 100644
index 0000000..8e15896
--- /dev/null
+++ b/common/recipes-core/init-ifupdown/files/init
@@ -0,0 +1,92 @@
+#!/bin/sh -e
+### BEGIN INIT INFO
+# Provides: networking
+# Required-Start: mountvirtfs $local_fs
+# Required-Stop: $local_fs
+# Should-Start: ifupdown
+# Should-Stop: ifupdown
+# Default-Start: S
+# Default-Stop: 0 6
+# Short-Description: Raise network interfaces.
+### END INIT INFO
+
+PATH="/usr/local/sbin:/usr/local/bin:/sbin:/bin:/usr/sbin:/usr/bin"
+
+[ -x /sbin/ifup ] || exit 0
+
+check_network_file_systems() {
+ [ -e /proc/mounts ] || return 0
+
+ if [ -e /etc/iscsi/iscsi.initramfs ]; then
+ echo "not deconfiguring network interfaces: iSCSI root is mounted."
+ exit 0
+ fi
+
+ exec 9<&0 < /proc/mounts
+ while read DEV MTPT FSTYPE REST; do
+ case $DEV in
+ /dev/nbd*|/dev/nd[a-z]*|/dev/etherd/e*)
+ echo "not deconfiguring network interfaces: network devices still mounted."
+ exit 0
+ ;;
+ esac
+ case $FSTYPE in
+ nfs|nfs4|smbfs|ncp|ncpfs|cifs|coda|ocfs2|gfs|pvfs|pvfs2|fuse.httpfs|fuse.curlftpfs)
+ echo "not deconfiguring network interfaces: network file systems still mounted."
+ exit 0
+ ;;
+ esac
+ done
+ exec 0<&9 9<&-
+}
+
+check_network_swap() {
+ [ -e /proc/swaps ] || return 0
+
+ exec 9<&0 < /proc/swaps
+ while read DEV MTPT FSTYPE REST; do
+ case $DEV in
+ /dev/nbd*|/dev/nd[a-z]*|/dev/etherd/e*)
+ echo "not deconfiguring network interfaces: network swap still mounted."
+ exit 0
+ ;;
+ esac
+ done
+ exec 0<&9 9<&-
+}
+
+case "$1" in
+start)
+ echo -n "Configuring network interfaces... "
+ sysctl -e -p /etc/sysctl.conf >/dev/null 2>&1
+ ifup -a
+ echo "done."
+ ;;
+
+stop)
+ # tfang, disabled them because 'exec < /proc/mounts' hangs
+ # could be kernel issue as regular file is ok
+ #check_network_file_systems
+ #check_network_swap
+
+ echo -n "Deconfiguring network interfaces... "
+ ifdown -a
+ echo "done."
+ ;;
+
+force-reload|restart)
+ echo "Running $0 $1 is deprecated because it may not enable again some interfaces"
+ echo "Reconfiguring network interfaces... "
+ ifdown -a || true
+ ifup -a
+ echo "done."
+ ;;
+
+*)
+ echo "Usage: /etc/init.d/networking {start|stop}"
+ exit 1
+ ;;
+esac
+
+exit 0
+
diff --git a/common/recipes-core/init-ifupdown/files/nfsroot b/common/recipes-core/init-ifupdown/files/nfsroot
new file mode 100644
index 0000000..b667cbb
--- /dev/null
+++ b/common/recipes-core/init-ifupdown/files/nfsroot
@@ -0,0 +1,2 @@
+exit 0
+
diff --git a/common/recipes-core/init-ifupdown/init-ifupdown_%.bbappend b/common/recipes-core/init-ifupdown/init-ifupdown_%.bbappend
new file mode 100644
index 0000000..7d74521
--- /dev/null
+++ b/common/recipes-core/init-ifupdown/init-ifupdown_%.bbappend
@@ -0,0 +1,2 @@
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
diff --git a/common/recipes-core/packagegroups/packagegroup-core-tools-debug.bbappend b/common/recipes-core/packagegroups/packagegroup-core-tools-debug.bbappend
new file mode 100644
index 0000000..65f85de
--- /dev/null
+++ b/common/recipes-core/packagegroups/packagegroup-core-tools-debug.bbappend
@@ -0,0 +1,6 @@
+# eglibc-mtrace is a Perl script analyzing the mtrace output data.
+# It is small but depends on perl, which increases image size by 1.35M.
+# Remove it explicitly. When we need to use it, we can always copy the
+# mtrace results out and run mtrace utility outside of BMC.
+MTRACE = ""
+MTRACE_libc-glibc = ""
diff --git a/common/recipes-core/udev/files/init b/common/recipes-core/udev/files/init
new file mode 100644
index 0000000..a428665
--- /dev/null
+++ b/common/recipes-core/udev/files/init
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+echo "UDEV: no devtmpfs support. Skip udev"
+
+exit 0
diff --git a/common/recipes-core/udev/udev_%.bbappend b/common/recipes-core/udev/udev_%.bbappend
new file mode 100644
index 0000000..7d74521
--- /dev/null
+++ b/common/recipes-core/udev/udev_%.bbappend
@@ -0,0 +1,2 @@
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
diff --git a/common/recipes-core/watchdog-ctrl/watchdog-ctrl/watchdog_ctrl.sh b/common/recipes-core/watchdog-ctrl/watchdog-ctrl/watchdog_ctrl.sh
new file mode 100755
index 0000000..9c4f2cc
--- /dev/null
+++ b/common/recipes-core/watchdog-ctrl/watchdog-ctrl/watchdog_ctrl.sh
@@ -0,0 +1,44 @@
+#!/bin/sh
+#
+# Copyright 2004-present Facebook. All Rights Reserved.
+#
+# This program file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program in a file named COPYING; if not, write to the
+# Free Software Foundation, Inc.,
+# 51 Franklin Street, Fifth Floor,
+# Boston, MA 02110-1301 USA
+#
+usage() {
+ echo "Usage: $0 <on | off>" >&2
+}
+
+set -e
+
+if [ "$#" -ne 1 ]; then
+ usage
+ exit 1
+fi
+
+case "$1" in
+"on")
+ echo "Enabling watchdog. Note: this does not start the watchdog!"
+ echo "x" > /dev/watchdog
+ ;;
+"off")
+ echo "Disabling watchdog."
+ echo "X" > /dev/watchdog
+ ;;
+*)
+ usage
+ exit 1
+ ;;
+esac
diff --git a/common/recipes-core/watchdog-ctrl/watchdog-ctrl_0.1.bb b/common/recipes-core/watchdog-ctrl/watchdog-ctrl_0.1.bb
new file mode 100644
index 0000000..00cf0f9
--- /dev/null
+++ b/common/recipes-core/watchdog-ctrl/watchdog-ctrl_0.1.bb
@@ -0,0 +1,33 @@
+# Copyright 2014-present Facebook. All Rights Reserved.
+SUMMARY = "Watchdog control utilities."
+DESCRIPTION = "The utilities to control system watchdog."
+SECTION = "base"
+PR = "r1"
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = "file://watchdog_ctrl.sh;beginline=5;endline=18;md5=0b1ee7d6f844d472fa306b2fee2167e0"
+
+SRC_URI = "file://watchdog_ctrl.sh \
+ "
+
+S = "${WORKDIR}"
+
+binfiles = "watchdog_ctrl.sh"
+
+pkgdir = "watchdog_ctrl"
+
+do_install() {
+ dst="${D}/usr/local/fbpackages/${pkgdir}"
+ bin="${D}/usr/local/bin"
+ install -d $dst
+ install -d $bin
+ for f in ${binfiles}; do
+ install -m 755 $f ${dst}/${f}
+ ln -s ../fbpackages/${pkgdir}/${f} ${bin}/${f}
+ done
+}
+
+FBPACKAGEDIR = "${prefix}/local/fbpackages"
+
+FILES_${PN} = "${FBPACKAGEDIR}/watchdog_ctrl ${prefix}/local/bin ${sysconfdir} "
+INHIBIT_PACKAGE_DEBUG_SPLIT = "1"
+INHIBIT_PACKAGE_STRIP = "1"
diff --git a/common/recipes-rest/bottle/bottle_0.12.7.bb b/common/recipes-rest/bottle/bottle_0.12.7.bb
new file mode 100644
index 0000000..25bd547
--- /dev/null
+++ b/common/recipes-rest/bottle/bottle_0.12.7.bb
@@ -0,0 +1,19 @@
+DESCRIPTION = "Bottle Web Framework"
+SECTION = "base"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://bottle.py;beginline=1;endline=14;md5=15d806194a048a43e3a7f1d4c7574fe6"
+
+SRC_URI = "https://pypi.python.org/packages/source/b/bottle/${PN}-${PV}.tar.gz"
+SRC_URI[md5sum] = "ed0b83c9dbbdbde784e7c652d61c59f4"
+SRC_URI[sha256sum] = "e3ea2191f06ca51af45bf6ca41ed2d1b2d809ceda0876466879fe205be7b2073"
+
+S = "${WORKDIR}/${PN}-${PV}"
+
+dst="/usr/lib/python2.7"
+
+do_install() {
+ mkdir -p ${D}/${dst}
+ install -m 755 bottle.py ${D}/${dst}
+}
+
+FILES_${PN} = "${dst}"
diff --git a/conf/layer.conf b/conf/layer.conf
new file mode 100644
index 0000000..3084e34
--- /dev/null
+++ b/conf/layer.conf
@@ -0,0 +1,10 @@
+# We have a conf and classes directory, add to BBPATH
+BBPATH .= ":${LAYERDIR}"
+
+# We have common/recipes-* directories, add to BBFILES
+BBFILES += "${LAYERDIR}/common/recipes-*/*/*.bb \
+ ${LAYERDIR}/common/recipes-*/*/*.bbappend"
+
+BBFILE_COLLECTIONS += "openbmc"
+BBFILE_PATTERN_openbmc = "^${LAYERDIR}/"
+BBFILE_PRIORITY_openbmc = "6"
diff --git a/meta-aspeed/classes/aspeed_uboot_image.bbclass b/meta-aspeed/classes/aspeed_uboot_image.bbclass
new file mode 100644
index 0000000..b22b0b8
--- /dev/null
+++ b/meta-aspeed/classes/aspeed_uboot_image.bbclass
@@ -0,0 +1,63 @@
+inherit image_types_uboot
+
+# oe_mkimage() was defined in image_types_uboot. Howver, it does not consider
+# the image load address and entry point. Override it here.
+
+oe_mkimage () {
+ mkimage -A ${UBOOT_ARCH} -O linux -T ramdisk -C $2 -n ${IMAGE_NAME} \
+ -a ${UBOOT_IMAGE_LOADADDRESS} -e ${UBOOT_IMAGE_ENTRYPOINT} \
+ -d ${DEPLOY_DIR_IMAGE}/$1 ${DEPLOY_DIR_IMAGE}/$1.u-boot
+}
+
+UBOOT_IMAGE_ENTRYPOINT ?= "0x42000000"
+UBOOT_IMAGE_LOADADDRESS ?= "${UBOOT_IMAGE_ENTRYPOINT}"
+
+# 24M
+IMAGE_ROOTFS_SIZE = "24576"
+# and don't put overhead behind my back
+IMAGE_OVERHEAD_FACTOR = "1"
+
+IMAGE_PREPROCESS_COMMAND += " generate_data_mount_dir ; "
+IMAGE_POSTPROCESS_COMMAND += " flash_image_generate ; "
+
+FLASH_IMAGE_NAME ?= "flash-${MACHINE}-${DATETIME}"
+FLASH_IMAGE_LINK ?= "flash-${MACHINE}"
+# 16M
+FLASH_SIZE ?= "16384"
+FLASH_UBOOT_OFFSET ?= "0"
+# 512k
+FLASH_KERNEL_OFFSET ?= "512"
+# 3M
+FLASH_ROOTFS_OFFSET ?= "3072"
+
+flash_image_generate() {
+ kernelfile="${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}"
+ ubootfile="${DEPLOY_DIR_IMAGE}/u-boot.${UBOOT_SUFFIX}"
+ # rootfs has to match the type defined in IMAGE_FSTYPES"
+ rootfs="${DEPLOY_DIR_IMAGE}/${IMAGE_LINK_NAME}.cpio.lzma.u-boot"
+ if [ ! -f $kernelfile ]; then
+ echo "Kernel file ${kernelfile} does not exist"
+ return 1
+ fi
+ if [ ! -f $ubootfile ]; then
+ echo "U-boot file ${ubootfile} does not exist"
+ return 1
+ fi
+ if [ ! -f $rootfs ]; then
+ echo "Rootfs file ${rootfs} does not exist"
+ return 1
+ fi
+ dst="${DEPLOY_DIR_IMAGE}/${FLASH_IMAGE_NAME}"
+ rm -rf $dst
+ dd if=/dev/zero of=${dst} bs=1k count=${FLASH_SIZE}
+ dd if=${ubootfile} of=${dst} bs=1k seek=${FLASH_UBOOT_OFFSET}
+ dd if=${kernelfile} of=${dst} bs=1k seek=${FLASH_KERNEL_OFFSET}
+ dd if=${rootfs} of=${dst} bs=1k seek=${FLASH_ROOTFS_OFFSET}
+ dstlink="${DEPLOY_DIR_IMAGE}/${FLASH_IMAGE_LINK}"
+ rm -rf $dstlink
+ ln -sf ${FLASH_IMAGE_NAME} $dstlink
+}
+
+generate_data_mount_dir() {
+ mkdir -p "${IMAGE_ROOTFS}/mnt/data"
+}
diff --git a/meta-aspeed/conf/layer.conf b/meta-aspeed/conf/layer.conf
new file mode 100644
index 0000000..2418d8e
--- /dev/null
+++ b/meta-aspeed/conf/layer.conf
@@ -0,0 +1,10 @@
+# We have a conf and classes directory, add to BBPATH
+BBPATH .= ":${LAYERDIR}"
+
+# We have recipes-* directories, add to BBFILES
+BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
+ ${LAYERDIR}/recipes-*/*/*.bbappend"
+
+BBFILE_COLLECTIONS += "aspeed"
+BBFILE_PATTERN_aspeed = "^${LAYERDIR}/"
+BBFILE_PRIORITY_aspeed = "7"
diff --git a/meta-aspeed/conf/machine/include/ast1250.inc b/meta-aspeed/conf/machine/include/ast1250.inc
new file mode 100644
index 0000000..099fdb0
--- /dev/null
+++ b/meta-aspeed/conf/machine/include/ast1250.inc
@@ -0,0 +1,28 @@
+#@TYPE: Machine
+#@NAME: aspeed ast1250
+#@DESCRIPTION: Machine configuration for aspeed ast1250 SoC
+
+# Ship all kernel modules by default
+MACHINE_EXTRA_RRECOMMENDS = "kernel-modules"
+
+# Allow for MMC booting (required by the NAND-less Beagleboard XM)
+EXTRA_IMAGEDEPENDS += "u-boot"
+
+# Uncomment the following line to enable the hard floating point abi. Note that
+# this breaks some binary libraries and 3D (neither of which ship with
+# meta-yocto). For maximum compatibility, leave this disabled.
+DEFAULTTUNE ?= "arm926ejs"
+require conf/machine/include/tune-arm926ejs.inc
+
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-aspeed"
+PREFERRED_VERSION_linux-aspeed ?= "2.6.28%"
+
+KERNEL_IMAGETYPE ?= "uImage"
+KERNEL_EXTRA_ARGS ?= "UIMAGE_LOADADDR=0x40008000"
+
+UBOOT_SUFFIX ?= "bin"
+UBOOT_ENTRYPOINT ?= "0x40008000"
+UBOOT_LOADADDRESS ?= "0x40008000"
+UBOOT_MACHINE ?= "ast1250_config"
+
+MACHINE_FEATURES = "usbgadget usbhost vfat ext2 serial"
diff --git a/meta-aspeed/conf/machine/include/ast2400.inc b/meta-aspeed/conf/machine/include/ast2400.inc
new file mode 100644
index 0000000..4ea982b
--- /dev/null
+++ b/meta-aspeed/conf/machine/include/ast2400.inc
@@ -0,0 +1,7 @@
+#@TYPE: Machine
+#@NAME: aspeed ast2400
+#@DESCRIPTION: Machine configuration for aspeed ast2400 SoC
+
+UBOOT_MACHINE ?= "ast2400_config"
+
+require conf/machine/include/ast1250.inc \ No newline at end of file
diff --git a/meta-aspeed/recipes-bsp/u-boot/files/fw_env.config b/meta-aspeed/recipes-bsp/u-boot/files/fw_env.config
new file mode 100644
index 0000000..9cb3ad2
--- /dev/null
+++ b/meta-aspeed/recipes-bsp/u-boot/files/fw_env.config
@@ -0,0 +1,22 @@
+# Configuration file for fw_(printenv/setenv) utility.
+# Up to two entries are valid, in this case the redundant
+# environment sector is assumed present.
+# Notice, that the "Number of sectors" is ignored on NOR and SPI-dataflash.
+# Futhermore, if the Flash sector size is ommitted, this value is assumed to
+# be the same as the Environment size, which is valid for NOR and SPI-dataflash
+
+# NOR example
+# MTD device name Device offset Env. size Flash sector size Number of sectors
+/dev/mtd1 0x0000 0x20000 0x20000
+#/dev/mtd2 0x0000 0x4000 0x4000
+
+# MTD SPI-dataflash example
+# MTD device name Device offset Env. size Flash sector size Number of sectors
+#/dev/mtd5 0x4200 0x4200
+#/dev/mtd6 0x4200 0x4200
+
+# NAND example
+#/dev/mtd0 0x4000 0x4000 0x20000 2
+
+# Block device example
+#/dev/mmcblk0 0xc0000 0x20000
diff --git a/meta-aspeed/recipes-bsp/u-boot/files/patch-2013.07/0000-u-boot-aspeed-064.patch b/meta-aspeed/recipes-bsp/u-boot/files/patch-2013.07/0000-u-boot-aspeed-064.patch
new file mode 100644
index 0000000..8ebfb96
--- /dev/null
+++ b/meta-aspeed/recipes-bsp/u-boot/files/patch-2013.07/0000-u-boot-aspeed-064.patch
@@ -0,0 +1,44658 @@
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/COMMINF.H b/arch/arm/cpu/arm926ejs/aspeed/COMMINF.H
+new file mode 100644
+index 0000000..44b7540
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/COMMINF.H
+@@ -0,0 +1,641 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef COMMINF_H
++#define COMMINF_H
++
++#include "SWFUNC.H"
++
++#if defined(LinuxAP)
++#endif
++#ifdef SLT_UBOOT
++#endif
++#ifdef SLT_DOS
++ #include <stdio.h>
++ #include <time.h>
++ #include <dos.h> // For delay()
++#endif
++
++#include "TYPEDEF.H"
++#include "LIB.H"
++
++//---------------------------------------------------------
++// Print Message
++//---------------------------------------------------------
++// for function
++#define FP_LOG 0
++#define FP_IO 1
++#define STD_OUT 2
++
++#ifdef SLT_UBOOT
++ #define PRINT printf
++ #define OUT_OBJ
++ #define FILE_VAR
++
++ #define GET_OBJ( i ) \
++ do { \
++ if ( i != STD_OUT ) \
++ return; \
++ } while ( 0 );
++
++#else
++ #define PRINT fprintf
++ #define OUT_OBJ fp,
++ #define FILE_VAR FILE *fp;
++
++ #define GET_OBJ( i ) \
++ switch( i ) { \
++ case FP_LOG: \
++ fp = fp_log; \
++ break; \
++ case FP_IO: \
++ fp = fp_io; \
++ break; \
++ case STD_OUT: \
++ fp = stdout; \
++ break; \
++ default : break; \
++ }
++#endif
++
++//---------------------------------------------------------
++// Function
++//---------------------------------------------------------
++#ifdef SLT_UBOOT
++ #define DELAY( x ) udelay( x * 1000 ) // For Uboot, the unit of udelay() is us.
++ #define GET_CAHR getc
++#endif
++#ifdef SLT_DOS
++ #define DELAY( x ) delay( x ) // For DOS, the unit of delay() is ms.
++ #define GET_CAHR getchar
++#endif
++
++//---------------------------------------------------------
++// Default argument
++//---------------------------------------------------------
++#define DEF_USER_DEF_PACKET_VAL 0x66666666 //0xff00ff00, 0xf0f0f0f0, 0xcccccccc, 0x55aa55aa, 0x5a5a5a5a, 0x66666666
++#define DEF_IOTIMINGBUND 5 //0/1/3/5/7
++#define DEF_PHY_ADR 0
++#define DEF_TESTMODE 0 //[0]0: no burst mode, 1: 0xff, 2: 0x55, 3: random, 4: ARP, 5: ARP, 6: IO timing, 7: IO timing+IO Strength
++#define DEF_LOOP_MAX 1
++#define DEF_MAC_LOOP_BACK 0 //GCtrl bit6
++#define DEF_SKIP_CHECK_PHY 0 //GCtrl bit4
++#define DEF_INIT_PHY 1 //GCtrl bit3
++
++#define SET_1GBPS 0 // 1G bps
++#define SET_100MBPS 1 // 100M bps
++#define SET_10MBPS 2 // 10M bps
++#define SET_1G_100M_10MBPS 3 // 1G and 100M and 10M bps
++#define DEF_SPEED SET_1G_100M_10MBPS
++#define DEF_ARPNUMCNT 0
++
++//---------------------------------------------------------
++// MAC information
++//---------------------------------------------------------
++#if ( AST1010_IOMAP == 1 )
++ // AST1010 only has a MAC
++ #define MAC_BASE1 AST_MAC1_BASE
++ #define MAC_BASE2 AST_MAC1_BASE
++ #define MAC_BASE3 AST_MAC1_BASE
++ #define MAC_BASE4 AST_MAC1_BASE
++#endif
++
++#if ( AST1010_IOMAP == 2 )
++ // AST1010 only has a MAC
++ #define MAC_BASE1 0x0830000
++ #define MAC_BASE2 0x0830000
++ #define MAC_BASE3 0x0830000
++ #define MAC_BASE4 0x0830000
++#endif
++
++#ifndef AST1010_IOMAP
++ #define MAC_BASE1 0x1e660000
++ #define MAC_BASE2 0x1e680000
++ #define MAC_BASE3 0x1e670000
++ #define MAC_BASE4 0x1e690000
++#endif
++
++#define MDC_Thres 0x3f
++#define MAC_PHYWr 0x08000000
++#define MAC_PHYRd 0x04000000
++
++#define MAC_PHYWr_New 0x00009400
++#define MAC_PHYRd_New 0x00009800
++#define MAC_PHYBusy_New 0x00008000
++
++//#define MAC_30h 0x00001010
++//#define MAC_34h 0x00000000
++//#define MAC_38h 0x00d22f00 //default 0x22f00
++//#define MAC_38h 0x00022f00 //default 0x22f00
++
++#define MAC_40h 0x40000000
++
++#ifdef Enable_BufMerge
++ #define MAC_48h 0x007702F1 //default 0xf1
++#else
++ #ifdef AST1010_IOMAP
++ #define MAC_48h 0x000002F1 //default 0xf1
++ #else
++ #define MAC_48h 0x000001F1 //default 0xf1
++ #endif
++#endif
++
++//---------------------------------------------------------
++// Data information
++//---------------------------------------------------------
++#ifdef SelectSimpleBoundary
++ #define ZeroCopy_OFFSET 0
++#else
++ #define ZeroCopy_OFFSET ( (BurstEnable) ? 0 : 2 )
++#endif
++
++// --------------------------------- DRAM_MapAdr = TDES_BASE1
++// | TX descriptor ring #1 |
++// ------------------------- DRAM_MapAdr + 0x040000 = RDES_BASE1
++// | RX descriptor ring #1 |
++// ------------------------- DRAM_MapAdr + 0x080000 = TDES_BASE2
++// | TX descriptor ring #2 |
++// ------------------------- DRAM_MapAdr + 0x0C0000 = RDES_BASE2
++// | RX descriptor ring #2 |
++// --------------------------------- DRAM_MapAdr + 0x100000 = DMA_BASE -------------------------
++// | #1 | \ | #1 Tx |
++// DMA buffer | | DMA_BufSize | LOOP = 0 |
++// ( Tx/Rx ) ------------------------- / --------------------------------------------------
++// | #2 | | #2 Rx | #2 Tx |
++// | | | LOOP = 0 | LOOP = 1 |
++// ------------------------- --------------------------------------------------
++// | #3 | | #3 Rx |
++// | | | LOOP = 1 |
++// ------------------------- -------------------------
++// | #4 | ..........
++// | |
++// -------------------------
++// | #5 |
++// | |
++// -------------------------
++// | #6 |
++// | |
++// -------------------------
++// .
++// .
++// -------------------------
++// | #n, n = DMA_BufNum |
++// | |
++// ---------------------------------
++
++#if ( AST1010_IOMAP == 1 )
++ #define DRAM_MapAdr ( CONFIG_DRAM_SWAP_BASE + 0x00200000 ) // We use 0xA00000 to 0xEFFFFF
++ #define CPU_BUS_ADDR_SDRAM_OFFSET 0x01000000 // In ReMapping function, MAC engine need Bus address
++ // But Coldfire need CPU address, so need to do offset
++#endif
++
++#if ( AST1010_IOMAP == 2 )
++ #define DRAM_MapAdr 0x0A00000 // We use 0xA00000 to 0xEFFFFF
++ #define CPU_BUS_ADDR_SDRAM_OFFSET 0
++#endif
++
++#ifndef AST1010_IOMAP
++ #ifdef AST3200_IOMAP
++ #define DRAM_MapAdr 0x80000000
++ #else
++ #define DRAM_MapAdr 0x44000000
++ #endif
++
++ #define CPU_BUS_ADDR_SDRAM_OFFSET 0
++#endif
++
++ #define TDES_BASE1 ( 0x00000000 + DRAM_MapAdr )
++ #define RDES_BASE1 ( 0x00040000 + DRAM_MapAdr )
++ #define TDES_BASE2 ( 0x00080000 + DRAM_MapAdr )
++ #define RDES_BASE2 ( 0x000C0000 + DRAM_MapAdr )
++
++ #define TDES_IniVal ( 0xb0000000 + FRAME_LEN_Cur )
++ #define RDES_IniVal ( 0x00000fff )
++ #define EOR_IniVal ( 0x40008000 )
++ #define HWOwnTx(dat) ( (dat) & 0x80000000 )
++ #define HWOwnRx(dat) ( !((dat) & 0x80000000) )
++ #define HWEOR(dat) ( dat & 0x40000000 )
++
++//---------------------------------------------------------
++// Error Flag Bits
++//---------------------------------------------------------
++#define Err_MACMode ( 1 << 0 ) // MAC interface mode mismatch
++#define Err_PHY_Type ( 1 << 1 ) // Unidentifiable PHY
++#define Err_MALLOC_FrmSize ( 1 << 2 ) // Malloc fail at frame size buffer
++#define Err_MALLOC_LastWP ( 1 << 3 ) // Malloc fail at last WP buffer
++#define Err_Check_Buf_Data ( 1 << 4 ) // Received data mismatch
++#define Err_Check_Des ( 1 << 5 ) // Descriptor error
++#define Err_NCSI_LinkFail ( 1 << 6 ) // NCSI packet retry number over flows
++#define Err_NCSI_Check_TxOwnTimeOut ( 1 << 7 ) // Time out of checking Tx owner bit in NCSI packet
++#define Err_NCSI_Check_RxOwnTimeOut ( 1 << 8 ) // Time out of checking Rx owner bit in NCSI packet
++#define Err_NCSI_Check_ARPOwnTimeOut ( 1 << 9 ) // Time out of checking ARP owner bit in NCSI packet
++#define Err_NCSI_No_PHY ( 1 << 10 ) // Can not find NCSI PHY
++#define Err_NCSI_Channel_Num ( 1 << 11 ) // NCSI Channel Number Mismatch
++#define Err_NCSI_Package_Num ( 1 << 12 ) // NCSI Package Number Mismatch
++#define Err_PHY_TimeOut ( 1 << 13 ) // Time out of read/write/reset PHY register
++#define Err_RXBUF_UNAVA ( 1 << 14 ) // MAC00h[2]:Receiving buffer unavailable
++#define Err_RPKT_LOST ( 1 << 15 ) // MAC00h[3]:Received packet lost due to RX FIFO full
++#define Err_NPTXBUF_UNAVA ( 1 << 16 ) // MAC00h[6]:Normal priority transmit buffer unavailable
++#define Err_TPKT_LOST ( 1 << 17 ) // MAC00h[7]:Packets transmitted to Ethernet lost
++#define Err_DMABufNum ( 1 << 18 ) // DMA Buffer is not enough
++#define Err_IOMargin ( 1 << 19 ) // IO timing margin is not enough
++#define Err_IOMarginOUF ( 1 << 20 ) // IO timing testing out of boundary
++#define Err_MHCLK_Ratio ( 1 << 21 ) // Error setting of MAC AHB bus clock (SCU08[18:16])
++
++#define Check_Des_TxOwnTimeOut ( 1 << 0 ) // Time out of checking Tx owner bit
++#define Check_Des_RxOwnTimeOut ( 1 << 1 ) // Time out of checking Rx owner bit
++#define Check_Des_RxErr ( 1 << 2 ) // Input signal RxErr
++#define Check_Des_OddNibble ( 1 << 3 ) // Nibble bit happen
++#define Check_Des_CRC ( 1 << 4 ) // CRC error of frame
++#define Check_Des_RxFIFOFull ( 1 << 5 ) // Rx FIFO full
++#define Check_Des_FrameLen ( 1 << 6 ) // Frame length mismatch
++
++#define NCSI_LinkFail_Get_Version_ID ( 1 << 0 ) // Time out when Get Version ID
++#define NCSI_LinkFail_Get_Capabilities ( 1 << 1 ) // Time out when Get Capabilities
++#define NCSI_LinkFail_Select_Active_Package ( 1 << 2 ) // Time out when Select Active Package
++#define NCSI_LinkFail_Enable_Set_MAC_Address ( 1 << 3 ) // Time out when Enable Set MAC Address
++#define NCSI_LinkFail_Enable_Broadcast_Filter ( 1 << 4 ) // Time out when Enable Broadcast Filter
++#define NCSI_LinkFail_Enable_Network_TX ( 1 << 5 ) // Time out when Enable Network TX
++#define NCSI_LinkFail_Enable_Channel ( 1 << 6 ) // Time out when Enable Channel
++#define NCSI_LinkFail_Disable_Network_TX ( 1 << 7 ) // Time out when Disable Network TX
++#define NCSI_LinkFail_Disable_Channel ( 1 << 8 ) // Time out when Disable Channel
++
++//---------------------------------------------------------
++// SCU information
++//---------------------------------------------------------
++#if ( AST1010_IOMAP == 1 )
++ #define SCU_BASE AST_SCU_BASE
++#endif
++#if ( AST1010_IOMAP == 2 )
++ #define SCU_BASE 0x0841000
++#endif
++
++#ifndef AST1010_IOMAP
++ #define SCU_BASE 0x1e6e2000
++#endif
++
++#define SCU_48h_AST1010 0x00000200
++#define SCU_48h_AST2300 0x00222255
++
++//#ifdef SLT_DOS
++// #define SCU_80h 0x00000000
++// #define SCU_88h 0x00000000
++// #define SCU_90h 0x00000000
++// #define SCU_74h 0x00000000
++//#else
++// #define SCU_80h 0x0000000f //AST2300[3:0]MAC1~4 PHYLINK
++// #define SCU_88h 0xc0000000 //AST2300[31]MAC1 MDIO, [30]MAC1 MDC
++// #define SCU_90h 0x00000004 //AST2300[2 ]MAC2 MDC/MDIO
++// #define SCU_74h 0x06300000 //AST3000[20]MAC2 MDC/MDIO, [21]MAC2 MII, [25]MAC1 PHYLINK, [26]MAC2 PHYLINK
++//#endif
++
++//---------------------------------------------------------
++// DMA Buffer information
++//---------------------------------------------------------
++#ifdef FPGA
++ #define DRAM_KByteSize ( 56 * 1024 )
++#else
++ #ifdef AST1010_IOMAP
++ #define DRAM_KByteSize ( 3 * 1024 ) // DATA buffer only use 0xB00000 to 0xE00000
++ #else
++ #define DRAM_KByteSize ( 18 * 1024 )
++ #endif
++#endif
++
++#define DMA_BASE ( 0x00100000 + DRAM_MapAdr )
++
++#ifdef Enable_Jumbo
++ #define DMA_PakSize ( 10 * 1024 )
++#else
++ #define DMA_PakSize ( 2 * 1024 ) // The size of one LAN packet
++#endif
++
++#ifdef SelectSimpleBoundary
++ #define DMA_BufSize ( ( ( ( ( DES_NUMBER + 15 ) * DMA_PakSize ) >> 2 ) << 2 ) ) //vary by DES_NUMBER
++#else
++ #define DMA_BufSize (4 + ( ( ( ( DES_NUMBER + 15 ) * DMA_PakSize ) >> 2 ) << 2 ) ) //vary by DES_NUMBER
++#endif
++
++#define DMA_BufNum ( ( DRAM_KByteSize * 1024 ) / ( DMA_BufSize ) ) //vary by DES_NUMBER
++#define GET_DMA_BASE_SETUP ( DMA_BASE )
++#define GET_DMA_BASE(x) ( DMA_BASE + ( ( ( ( x ) % DMA_BufNum ) + 1 ) * DMA_BufSize ) )//vary by DES_NUMBER
++
++#define SEED_START 8
++#define DATA_SEED(seed) ( ( seed ) | (( seed + 1 ) << 16 ) )
++#define DATA_IncVal 0x00020001
++//#define DATA_IncVal 0x01000001 //fail
++//#define DATA_IncVal 0x10000001 //fail
++//#define DATA_IncVal 0x10000000 //fail
++//#define DATA_IncVal 0x80000000 //fail
++//#define DATA_IncVal 0x00000001 //ok
++//#define DATA_IncVal 0x01000100 //ok
++//#define DATA_IncVal 0x01010000 //ok
++//#define DATA_IncVal 0x01010101 //ok
++//#define DATA_IncVal 0x00000101 //ok
++//#define DATA_IncVal 0x00001111 //fail
++//#define DATA_IncVal 0x00000011 //fail
++//#define DATA_IncVal 0x10100101 //fail
++//#define DATA_IncVal 0xfeff0201
++//#define DATA_IncVal 0x00010001
++#define PktByteSize ( ( ( ( ZeroCopy_OFFSET + FRAME_LEN_Cur - 1 ) >> 2 ) + 1) << 2 )
++
++//---------------------------------------------------------
++// Delay (ms)
++//---------------------------------------------------------
++//#define Delay_DesGap 1000 //off
++//#define Delay_DesGap 700 //off
++
++//#define Delay_ChkRxOwn 10
++//#define Delay_ChkTxOwn 10
++#define Delay_CntMax 100000000
++//#define Delay_CntMax 1000
++//#define Delay_CntMax 8465
++//#define Delay_CntMaxIncVal 50000
++#define Delay_CntMaxIncVal 47500
++
++#define Delay_PHYRst 100
++#define Delay_PHYRd 5
++
++#define Delay_SCU 11
++#define Delay_MACRst 1
++#define Delay_MACDump 100
++
++//#define Delay_DES 1
++
++//---------------------------------------------------------
++// Time Out
++//---------------------------------------------------------
++#define TIME_OUT_Des 10000
++#define TIME_OUT_PHY_RW 10000
++#define TIME_OUT_PHY_Rst 10000
++
++//#define TIME_OUT_NCSI 300000
++#define TIME_OUT_NCSI 30000
++
++
++
++//---------------------------------------------------------
++// Chip memory MAP
++//---------------------------------------------------------
++#define LITTLE_ENDIAN_ADDRESS 0
++#define BIG_ENDIAN_ADDRESS 1
++
++typedef struct {
++ ULONG StartAddr;
++ ULONG EndAddr;
++} LittleEndian_Area;
++
++#if ( AST1010_IOMAP == 1 )
++ static const LittleEndian_Area LittleEndianArea[] = {
++ { AST_IO_BASE, (AST_IO_BASE + 0x000FFFFF) },
++ { 0xFFFFFFFF, 0xFFFFFFFF } // End
++ };
++#else
++ static const LittleEndian_Area LittleEndianArea[] = {
++ { 0xFFFFFFFF, 0xFFFFFFFF } // End
++ };
++#endif
++
++// ========================================================
++// For ncsi.c
++
++#define DEF_PACKAGE2NUM 1 // Default value
++#define DEF_CHANNEL2NUM 2 // Default value
++
++typedef struct {
++ unsigned char Package_ID;
++ unsigned char Channel_ID;
++ unsigned long Capabilities_Flags;
++ unsigned long Broadcast_Packet_Filter_Capabilities;
++ unsigned long Multicast_Packet_Filter_Capabilities;
++ unsigned long Buffering_Capabilities;
++ unsigned long AEN_Control_Support;
++ unsigned long PCI_DID_VID;
++ unsigned long ManufacturerID;
++} NCSI_Capability;
++
++#undef GLOBAL
++#ifdef NCSI_C
++#define GLOBAL
++#else
++#define GLOBAL extern
++#endif
++
++GLOBAL NCSI_Capability NCSI_Cap_SLT;
++GLOBAL BYTE number_chl;
++
++GLOBAL char phy_ncsi (void);
++
++// ========================================================
++// For mactest
++
++#undef GLOBAL
++#ifdef MACTEST_C
++#define GLOBAL
++#else
++#define GLOBAL extern
++#endif
++
++GLOBAL ULONG NCSI_DiSChannel;
++
++//
++#ifdef SLT_UBOOT
++#else
++// SLT_DOS
++GLOBAL FILE *fp_log;
++GLOBAL FILE *fp_io;
++#endif
++
++GLOBAL CHAR dlymap[16][16];
++GLOBAL CHAR PrintNCSIEn;
++GLOBAL ULONG ARPNumCnt;
++GLOBAL CHAR FileNameMain[256];
++GLOBAL CHAR FileName[256];
++GLOBAL CHAR ASTChipName[256];
++GLOBAL CHAR LOOP_Str[256];
++GLOBAL BYTE IOTimingBund;
++GLOBAL BYTE ChannelTolNum;
++GLOBAL BYTE PackageTolNum;
++GLOBAL ULONG IOdly_out_reg;
++GLOBAL BYTE IOdly_out_reg_idx;
++GLOBAL ULONG Dat_ULONG;
++GLOBAL ULONG IOdly_incval;
++GLOBAL ULONG IOdly_in_reg;
++GLOBAL BYTE IOdly_in_reg_idx;
++GLOBAL ULONG *wp_lst;
++GLOBAL ULONG *FRAME_LEN;
++GLOBAL ULONG DES_NUMBER;
++GLOBAL ULONG DES_NUMBER_Org;
++GLOBAL int LOOP_MAX;
++GLOBAL ULONG LOOP_CheckNum;
++GLOBAL int Loop;
++GLOBAL ULONG CheckBuf_MBSize;
++GLOBAL ULONG Err_Flag;
++GLOBAL ULONG SCU_f0h_old;
++#ifdef AST1010_IOMAP
++ GLOBAL ULONG SCU_11Ch_old;
++#endif
++GLOBAL ULONG SCU_04h;
++GLOBAL ULONG SCU_90h_old;
++GLOBAL ULONG SCU_7ch_old;
++GLOBAL ULONG MAC_50h;
++GLOBAL ULONG SCU_ach_old;
++GLOBAL ULONG SCU_70h_old;
++GLOBAL ULONG MAC_50h_Speed;
++GLOBAL ULONG SCU_48h_old;
++GLOBAL ULONG SCU_48h_mix;
++GLOBAL ULONG MAC_08h_old;
++GLOBAL ULONG MAC_0ch_old;
++GLOBAL ULONG MAC_40h_old;
++GLOBAL ULONG SCU_08h_old;
++GLOBAL ULONG MAC_PHYBASE;
++GLOBAL ULONG LOOP_MAX_arg;
++GLOBAL BYTE GRun_Mode;
++GLOBAL ULONG GSpeed_idx;
++GLOBAL CHAR GSpeed_sel[3];
++GLOBAL CHAR PHY_ADR;
++GLOBAL CHAR PHY_ADR_arg;
++GLOBAL CHAR PHYName[256];
++GLOBAL ULONG PHY_ID3;
++GLOBAL ULONG PHY_ID2;
++GLOBAL BYTE number_pak;
++GLOBAL BYTE TestMode;
++GLOBAL ULONG IOStr_i;
++GLOBAL BYTE IOTimingBund_arg;
++GLOBAL BYTE GSpeed;
++GLOBAL BYTE GCtrl;
++GLOBAL ULONG UserDVal;
++GLOBAL ULONG H_MAC_BASE;
++GLOBAL ULONG H_TDES_BASE;
++GLOBAL ULONG H_RDES_BASE;
++GLOBAL CHAR Loop_rl[3];
++GLOBAL CHAR IOTiming;
++GLOBAL CHAR LOOP_INFINI;
++GLOBAL CHAR SelectMAC;
++GLOBAL CHAR Enable_SkipChkPHY;
++GLOBAL CHAR Enable_MAC34;
++GLOBAL CHAR IOStrength;
++GLOBAL CHAR DataDelay;
++GLOBAL CHAR SA[6];
++GLOBAL CHAR RxDataEnable;
++GLOBAL CHAR IEEETesting;
++GLOBAL CHAR BurstEnable;
++GLOBAL CHAR MAC_Mode;
++GLOBAL CHAR Enable_MACLoopback;
++GLOBAL CHAR Enable_InitPHY;
++GLOBAL CHAR MAC1_1GEn;
++GLOBAL CHAR MAC2_RMII;
++GLOBAL CHAR Enable_RMII;
++GLOBAL CHAR MAC2_1GEn;
++GLOBAL CHAR TxDataEnable;
++GLOBAL CHAR AST2300_NewMDIO;
++GLOBAL CHAR ASTChipType;
++GLOBAL CHAR Err_Flag_PrintEn;
++GLOBAL CHAR AST2400;
++GLOBAL CHAR AST2300;
++GLOBAL CHAR AST1100;//Different in phy & dram initiation & dram size & RMII
++GLOBAL CHAR AST3200;
++GLOBAL CHAR AST1010;
++GLOBAL SCHAR IOdly_i_min;
++GLOBAL SCHAR IOdly_j_min;
++GLOBAL SCHAR IOdly_i_max;
++GLOBAL SCHAR IOdly_j_max;
++GLOBAL BYTE IOdly_i;
++GLOBAL BYTE IOdly_j;
++GLOBAL BYTE IOdly_in;
++GLOBAL BYTE IOdly_out;
++GLOBAL SCHAR IOdly_in_str;
++GLOBAL BYTE IOdly_in_end;
++GLOBAL BYTE IOdly_out_end;
++GLOBAL BYTE IOdly_out_shf;
++GLOBAL BYTE IOdly_in_shf;
++GLOBAL SCHAR IOdly_out_str;
++GLOBAL BYTE valary[16];
++
++#define MODE_DEDICATED 0x01
++#define MODE_NSCI 0x02
++GLOBAL CHAR ModeSwitch;
++
++#ifdef SLT_UBOOT
++#else
++ GLOBAL time_t timestart;
++#endif
++
++#ifdef SPI_BUS
++ GLOBAL ULONG mmiobase;
++#else
++ // ( USE_P2A | USE_LPC )
++ GLOBAL UCHAR *mmiobase;
++ GLOBAL ULONG ulPCIBaseAddress;
++ GLOBAL ULONG ulMMIOBaseAddress;
++#endif
++
++
++// ========================================================
++// For mac.c
++#undef GLOBAL
++#ifdef MAC_C
++#define GLOBAL
++#else
++#define GLOBAL extern
++#endif
++
++GLOBAL ULONG ARP_data[16];
++GLOBAL ULONG NCSI_LinkFail_Val;
++static const char version_name[] = VER_NAME;
++
++GLOBAL void Debug_delay (void);
++GLOBAL void read_scu (void);
++GLOBAL void Setting_scu (void);
++GLOBAL void PrintMode (void);
++GLOBAL void PrintPakNUm (void);
++GLOBAL void PrintChlNUm (void);
++GLOBAL void PrintTest (void);
++GLOBAL void PrintIOTimingBund (void);
++GLOBAL void PrintSpeed (void);
++GLOBAL void PrintCtrl (void);
++GLOBAL void PrintLoop (void);
++GLOBAL void PrintPHYAdr (void);
++GLOBAL void Finish_Close (void);
++GLOBAL void Calculate_LOOP_CheckNum (void);
++GLOBAL char Finish_Check (int value);
++GLOBAL void init_scu1 (void);
++GLOBAL void init_scu_macrst (void);
++GLOBAL void setup_arp (void);
++GLOBAL void TestingSetup (void);
++GLOBAL void init_scu2 (void);
++GLOBAL void init_scu3 (void);
++GLOBAL void init_mac (ULONG base, ULONG tdexbase, ULONG rdexbase);
++GLOBAL char TestingLoop (ULONG loop_checknum);
++GLOBAL void PrintIO_Line_LOG (void);
++GLOBAL void init_phy (int loop_phy);
++GLOBAL void recov_phy (int loop_phy);
++GLOBAL int FindErr (int value);
++GLOBAL int FindErr_Des (int value);
++GLOBAL void PrintIO_Header (BYTE option);
++GLOBAL void Print_Header (BYTE option);
++GLOBAL void PrintIO_LineS (BYTE option);
++GLOBAL void PrintIO_Line (BYTE option);
++GLOBAL void FPri_ErrFlag (BYTE option);
++
++#ifdef SUPPORT_PHY_LAN9303
++// ========================================================
++// For LAN9303.c
++#undef GLOBAL
++#ifdef LAN9303_C
++#define GLOBAL
++#else
++#define GLOBAL extern
++#endif
++
++GLOBAL void LAN9303(int num, int phy_adr, int speed, int int_loopback);
++#endif // SUPPORT_PHY_LAN9303
++#endif // End COMMINF_H
++
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/DEF_SPI.H b/arch/arm/cpu/arm926ejs/aspeed/DEF_SPI.H
+new file mode 100644
+index 0000000..02353e7
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/DEF_SPI.H
+@@ -0,0 +1,35 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef DEF_SPI_H
++#define DEF_SPI_H
++
++#include "TYPEDEF.H"
++#include "SWFUNC.H"
++
++typedef struct _DEVICE_PCI_INFO
++{
++ USHORT usVendorID;
++ USHORT usDeviceID;
++ ULONG ulPCIConfigurationBaseAddress;
++ ULONG ulPhysicalBaseAddress;
++ ULONG ulMMIOBaseAddress;
++ USHORT usRelocateIO;
++} DEVICE_PCI_INFO;
++
++//VIDEO Engine Info
++typedef struct _VIDEO_ENGINE_INFO {
++ USHORT iEngVersion;
++ DEVICE_PCI_INFO VGAPCIInfo;
++} VIDEO_ENGINE_INFO;
++
++BOOLEAN GetDevicePCIInfo (VIDEO_ENGINE_INFO *VideoEngineInfo);
++
++#endif // DEF_SPI_H
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/DRAM_SPI.c b/arch/arm/cpu/arm926ejs/aspeed/DRAM_SPI.c
+new file mode 100644
+index 0000000..fe2b5cf
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/DRAM_SPI.c
+@@ -0,0 +1,78 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define DRAM_SPI_C
++static const char ThisFile[] = "DRAM_SPI.c";
++
++#include "SWFUNC.H"
++
++#ifdef SPI_BUS
++#include <stdio.h>
++#include "DEF_SPI.H"
++#include "LIB_SPI.H"
++
++VOID Set_MMIO_Base(ULONG PCI_BASE, ULONG addr)
++{
++ static ULONG MMIO_BASE = -1;
++
++ if(MMIO_BASE != (addr & 0xffff0000)){
++ if(MMIO_BASE == -1){
++ *(ULONG *)(PCI_BASE + 0xF000) = 1;
++ }
++ *(ULONG *)(PCI_BASE + 0xF004) = addr;
++ MMIO_BASE = addr & 0xffff0000;
++ }
++}
++
++VOID MOutbm(ULONG PCI_BASE, ULONG Offset, BYTE Data)
++{
++ Set_MMIO_Base(PCI_BASE, Offset);
++ *(BYTE *)(PCI_BASE + 0x10000 + (Offset & 0xffff)) = Data;
++}
++
++VOID MOutwm(ULONG PCI_BASE, ULONG Offset, USHORT Data)
++{
++ Set_MMIO_Base(PCI_BASE, Offset);
++ *(USHORT *)(PCI_BASE + 0x10000 + (Offset & 0xffff)) = Data;
++}
++
++VOID MOutdwm(ULONG PCI_BASE, ULONG Offset, ULONG Data)
++{
++ Set_MMIO_Base(PCI_BASE, Offset);
++ *(ULONG *)(PCI_BASE + 0x10000 + (Offset & 0xffff)) = Data;
++}
++
++BYTE MInbm(ULONG PCI_BASE, ULONG Offset)
++{
++ BYTE jData;
++
++ Set_MMIO_Base(PCI_BASE, Offset);
++ jData = *(BYTE *)(PCI_BASE + 0x10000 + (Offset & 0xffff));
++ return(jData);
++}
++
++USHORT MInwm(ULONG PCI_BASE, ULONG Offset)
++{
++ USHORT usData;
++
++ Set_MMIO_Base(PCI_BASE, Offset);
++ usData = *(USHORT *)(PCI_BASE + 0x10000 + (Offset & 0xffff));
++ return(usData);
++}
++
++ULONG MIndwm(ULONG PCI_BASE, ULONG Offset)
++{
++ ULONG ulData;
++
++ Set_MMIO_Base(PCI_BASE, Offset);
++ ulData = *(ULONG *)(PCI_BASE + 0x10000 + (Offset & 0xffff));
++ return(ulData);
++}
++#endif // End SPI_BUS
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/IO.H b/arch/arm/cpu/arm926ejs/aspeed/IO.H
+new file mode 100644
+index 0000000..5fe03f0
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/IO.H
+@@ -0,0 +1,36 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef IO_H
++#define IO_H
++
++#include "SWFUNC.H"
++
++//
++// Macro
++//
++#if defined(LinuxAP)
++ #define delay(val) usleep(val*1000)
++ #define ob(p,d) outb(d,p)
++ #define ib(p) inb(p)
++#else
++ #define ob(p,d) outp(p,d)
++ #define ib(p) inp(p)
++#endif
++
++#ifdef USE_LPC
++void open_aspeed_sio_password(void);
++void enable_aspeed_LDU(BYTE jldu_number);
++int findlpcport(BYTE jldu_number);
++#endif
++
++void WriteSOC_DD(ULONG addr, ULONG data);
++ULONG ReadSOC_DD(ULONG addr);
++#endif
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/IO.c b/arch/arm/cpu/arm926ejs/aspeed/IO.c
+new file mode 100644
+index 0000000..86e9918
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/IO.c
+@@ -0,0 +1,356 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define IO_C
++static const char ThisFile[] = "IO.c";
++
++#include "SWFUNC.H"
++
++#if defined(LinuxAP)
++ #include <stdio.h>
++ #include <string.h>
++ #include <stdlib.h>
++ #include <stdarg.h>
++ #include <unistd.h>
++ #include <string.h>
++ #include <fcntl.h>
++ #include <pthread.h>
++ #include <sys/mman.h>
++ #include <sys/io.h>
++#endif
++#ifdef SLT_UBOOT
++ #include <common.h>
++ #include <command.h>
++ #include <post.h>
++ #include <malloc.h>
++ #include <net.h>
++ #include <COMMINF.H>
++#endif
++#ifdef SLT_DOS
++ #include <stdlib.h>
++ #include <stdio.h>
++ #include <time.h>
++ #include <conio.h>
++ #include <dos.h>
++ #include <mem.h>
++ #include "TYPEDEF.H"
++ #include "LIB.H"
++ #include "COMMINF.H"
++#endif
++
++#include "TYPEDEF.H"
++#include "IO.H"
++#include "LIB_SPI.H"
++
++#ifdef SPI_BUS
++#endif
++#ifdef USE_LPC
++ USHORT usLPCPort;
++#endif
++#ifdef USE_P2A
++#endif
++
++#ifdef USE_LPC
++//------------------------------------------------------------
++// LPC access
++//------------------------------------------------------------
++void open_aspeed_sio_password(void)
++{
++ ob (usLPCPort, 0xaa);
++
++ ob (usLPCPort, 0xa5);
++ ob (usLPCPort, 0xa5);
++}
++
++//------------------------------------------------------------
++void close_aspeed_sio_password(void)
++{
++ ob (usLPCPort, 0xaa);
++}
++
++//------------------------------------------------------------
++void enable_aspeed_LDU(BYTE jldu_number)
++{
++ ob (usLPCPort, 0x07);
++ ob ((usLPCPort + 1), jldu_number);
++ ob (usLPCPort, 0x30);
++ ob ((usLPCPort + 1), 0x01);
++}
++
++//------------------------------------------------------------
++void disable_aspeed_LDU(BYTE jldu_number)
++{
++ ob (usLPCPort, 0x07);
++ ob ((usLPCPort + 1), jldu_number);
++ ob (usLPCPort, 0x30);
++ ob ((usLPCPort + 1), 0x00);
++}
++
++//------------------------------------------------------------
++/*
++ulAddress = AHB address
++jmode = 0: byte mode
++ 1: word mode
++ 2: dword mode
++*/
++static ULONG lpc_read (ULONG ulAddress, BYTE jmode)
++{
++ ULONG uldata = 0;
++ ULONG ultemp = 0;
++ BYTE jtemp;
++
++ //Write Address
++ ob ( usLPCPort, 0xf0);
++ ob ( (usLPCPort + 1 ), ((ulAddress & 0xff000000) >> 24));
++ ob ( usLPCPort, 0xf1);
++ ob ( (usLPCPort + 1) , ((ulAddress & 0x00ff0000) >> 16));
++ ob ( usLPCPort, 0xf2);
++ ob ( (usLPCPort + 1), ((ulAddress & 0x0000ff00) >> 8));
++ ob ( usLPCPort, 0xf3);
++ ob ( (usLPCPort + 1), ulAddress & 0xff);
++
++ //Write Mode
++ ob (usLPCPort, 0xf8);
++ jtemp = ib ((usLPCPort + 1));
++ ob ((usLPCPort + 1), ((jtemp & 0xfc) | jmode));
++
++ //Fire
++ ob (usLPCPort, 0xfe);
++ jtemp = ib ((usLPCPort + 1));
++
++ //Get Data
++ switch ( jmode )
++ {
++ case 0:
++ ob (usLPCPort, 0xf7);
++ ultemp = ib ((usLPCPort + 1));
++ uldata |= (ultemp);
++ break;
++
++ case 1:
++ ob (usLPCPort, 0xf6);
++ ultemp = ib ((usLPCPort + 1));
++ uldata |= (ultemp << 8);
++ ob (usLPCPort, 0xf7);
++ ultemp = ib ((usLPCPort + 1));
++ uldata |= (ultemp << 0);
++ break;
++
++ case 2:
++ ob (usLPCPort, 0xf4);
++ ultemp = ib ((usLPCPort + 1));
++ uldata |= (ultemp << 24);
++ ob (usLPCPort, 0xf5);
++ ultemp = ib ((usLPCPort + 1));
++ uldata |= (ultemp << 16);
++ ob (usLPCPort, 0xf6);
++ ultemp = ib ((usLPCPort + 1));
++ uldata |= (ultemp << 8);
++ ob (usLPCPort, 0xf7);
++ ultemp = ib ((usLPCPort + 1));
++ uldata |= ultemp;
++ break;
++ } // End switch ( jmode )
++
++ return uldata;
++} // End static ULONG lpc_read (ULONG ulAddress, BYTE jmode)
++
++//------------------------------------------------------------
++static void lpc_write (ULONG ulAddress, ULONG uldata, BYTE jmode)
++{
++ BYTE jtemp;
++
++ //Write Address
++ ob ( usLPCPort, 0xf0);
++ ob ((usLPCPort + 1), ((ulAddress & 0xff000000) >> 24));
++ ob ( usLPCPort, 0xf1);
++ ob ((usLPCPort + 1), ((ulAddress & 0x00ff0000) >> 16));
++ ob ( usLPCPort, 0xf2);
++ ob ((usLPCPort + 1), ((ulAddress & 0x0000ff00) >> 8));
++ ob ( usLPCPort, 0xf3);
++ ob ((usLPCPort + 1), ulAddress & 0xff);
++
++ //Write Data
++ switch ( jmode )
++ {
++ case 0:
++ ob ( usLPCPort, 0xf7);
++ ob ((usLPCPort + 1), (uldata & 0xff));
++ break;
++ case 1:
++ ob ( usLPCPort, 0xf6);
++ ob ((usLPCPort + 1), ((uldata & 0xff00) >> 8));
++ ob ( usLPCPort, 0xf7);
++ ob ((usLPCPort + 1), (uldata & 0x00ff));
++ break;
++ case 2:
++ ob ( usLPCPort, 0xf4);
++ ob ((usLPCPort + 1), ((uldata & 0xff000000) >> 24));
++ ob ( usLPCPort, 0xf5);
++ ob ((usLPCPort + 1), ((uldata & 0x00ff0000) >> 16));
++ ob ( usLPCPort, 0xf6);
++ ob ((usLPCPort + 1), ((uldata & 0x0000ff00) >> 8));
++ ob ( usLPCPort, 0xf7);
++ ob ((usLPCPort + 1), uldata & 0xff);
++ break;
++ } // End switch ( jmode )
++
++ //Write Mode
++ ob (usLPCPort, 0xf8);
++ jtemp = ib ((usLPCPort + 1));
++ ob ((usLPCPort + 1), ((jtemp & 0xfc) | jmode));
++
++ //Fire
++ ob (usLPCPort, 0xfe);
++ ob ((usLPCPort + 1), 0xcf);
++
++} // End static void lpc_write (ULONG ulAddress, ULONG uldata, BYTE jmode)
++
++//------------------------------------------------------------
++static USHORT usLPCPortList[] = {0x2e, 0x4e, 0xff};
++int findlpcport(BYTE jldu_number)
++{
++ USHORT *jLPCPortPtr;
++ ULONG ulData;
++
++ jLPCPortPtr = usLPCPortList;
++ while (*(USHORT *)(jLPCPortPtr) != 0xff )
++ {
++ usLPCPort = *(USHORT *)(jLPCPortPtr++);
++
++ open_aspeed_sio_password();
++ enable_aspeed_LDU(0x0d);
++
++ ulData = lpc_read(0x1e6e207c, 2);
++
++ if ( (ulData != 0x00000000) &&
++ (ulData != 0xFFFFFFFF) )
++ {
++ printf("Find LPC IO port at 0x%2x \n", usLPCPort);
++ return 1;
++ }
++
++ disable_aspeed_LDU(0x0d);
++ close_aspeed_sio_password();
++ }
++
++ //printf("[Error] Fail to find proper LPC IO Port \n");
++ return 0;
++}
++#endif // End ifdef USE_LPC
++
++#ifdef USE_P2A
++//------------------------------------------------------------
++// A2P Access
++//------------------------------------------------------------
++void mm_write (ULONG addr, ULONG data, BYTE jmode)
++{
++ *(ULONG *) (mmiobase + 0xF004) = (ULONG) ((addr) & 0xFFFF0000);
++ *(ULONG *) (mmiobase + 0xF000) = (ULONG) 0x00000001;
++
++ switch ( jmode )
++ {
++ case 0:
++ *(BYTE *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) = (BYTE) data;
++ break;
++ case 1:
++ *(USHORT *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) = (USHORT) data;
++ break;
++ case 2:
++ default:
++ *(ULONG *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) = data;
++ break;
++ } //switch
++}
++
++//------------------------------------------------------------
++ULONG mm_read (ULONG addr, BYTE jmode)
++{
++ *(ULONG *) (mmiobase + 0xF004) = (ULONG) ((addr) & 0xFFFF0000);
++ *(ULONG *) (mmiobase + 0xF000) = (ULONG) 0x00000001;
++ switch (jmode)
++ {
++ case 0:
++ return ( *(BYTE *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) );
++ break;
++ case 1:
++ return ( *(USHORT *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) );
++ break;
++ default:
++ case 2:
++ return ( *(ULONG *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) );
++ break;
++ } //switch
++
++ return 0;
++}
++#endif // End ifdef USE_P2A
++
++//------------------------------------------------------------
++// General Access API
++//------------------------------------------------------------
++#ifdef SLT_UBOOT
++BYTE Check_BEorLN ( ULONG chkaddr )
++{
++ BYTE ret = BIG_ENDIAN_ADDRESS;
++ BYTE i = 0;
++
++ do {
++ if ( LittleEndianArea[i].StartAddr == LittleEndianArea[i].EndAddr )
++ break;
++
++ if ( ( LittleEndianArea[i].StartAddr <= chkaddr ) &&
++ ( LittleEndianArea[i].EndAddr >= chkaddr ) ) {
++ ret = LITTLE_ENDIAN_ADDRESS;
++ break;
++ }
++ i++;
++ } while ( 1 );
++
++ return ret;
++}
++#endif
++
++void WriteSOC_DD(ULONG addr, ULONG data)
++{
++#ifdef SLT_UBOOT
++ if ( Check_BEorLN( addr ) == BIG_ENDIAN_ADDRESS )
++ *(volatile unsigned long *)(addr) = cpu_to_le32(data);
++ else
++ *(volatile unsigned long *)(addr) = data;
++#else
++ #ifdef USE_LPC
++ lpc_write(addr, data, 2);
++ #endif
++ #ifdef USE_P2A
++ mm_write(addr, data, 2);
++ #endif
++#endif
++}
++
++//------------------------------------------------------------
++ULONG ReadSOC_DD(ULONG addr)
++{
++#ifdef SLT_UBOOT
++ if ( Check_BEorLN( addr ) == BIG_ENDIAN_ADDRESS )
++ return le32_to_cpu(*(volatile unsigned long *) (addr));
++ else
++ return (*(volatile unsigned long *) (addr));
++#else
++ #ifdef USE_LPC
++ return (lpc_read(addr, 2));
++ #endif
++ #ifdef USE_P2A
++ return (mm_read(addr, 2));
++ #endif
++#endif
++ return 0;
++}
++
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c b/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c
+new file mode 100644
+index 0000000..498d4fd
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c
+@@ -0,0 +1,525 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define LAN9303_C
++static const char ThisFile[] = "LAN9303.c";
++
++#include "SWFUNC.H"
++#ifdef SLT_UBOOT
++ #include <COMMINF.H>
++ #include <MAC.H>
++ #include <IO.H>
++#endif
++
++#ifdef SLT_DOS
++ #include "COMMINF.H"
++ #include <stdlib.h>
++ #include "IO.H"
++#endif
++
++#ifdef SUPPORT_PHY_LAN9303
++//#define LAN9303M
++#define I2C_Debug 0
++#define Print_DWRW 0
++#define Print_PHYRW 0
++#define I2C_TIMEOUT 10000000
++
++ULONG devbase;
++ULONG busnum;
++ULONG byte;
++ULONG data_rd;
++
++//------------------------------------------------------------
++// Basic
++//------------------------------------------------------------
++void actime(ULONG ac1, ULONG ac2, ULONG *fact, ULONG *ckh, ULONG *ckl)
++{
++ static int divcnt;
++
++ ac1 = ac1 * 50 + 1;
++ ac2 = ac2 * 50 + 1;
++
++ divcnt = 0;
++ while (ac1 > 8 || ac2 > 8) {
++ divcnt++;
++ ac1 >>= 1;
++ ac2 >>= 1;
++ }
++
++ if (ac1 < 2 ) ac1 = 2;
++ if (ac2 < 2 ) ac2 = 2;
++ if (ac1 > ac2) ac2 = 1;
++ else ac1 += 1;
++
++#ifdef PRINT_MSG
++ printf("Divcnt = %d, ckdiv = %d, ckh = %d, ckl = %d\n",(1<<divcnt)*(ac1+ac2),divcnt,ac1-1,ac2-1);
++ printf("CKH = %d us, CKL = %d us\n",(1<<divcnt)*ac1/50,(1<<divcnt)*ac2/50);
++#endif
++
++ *fact = divcnt;
++ *ckh = ac1 - 1;
++ *ckl = ac2 - 1;
++}
++
++//------------------------------------------------------------
++ULONG PollStatus()
++{
++ static ULONG status;
++ static ULONG cnt = 0;
++
++ do {
++ status = ReadSOC_DD( devbase + 0x14 ) & 0xff;
++
++ if ( ++cnt > I2C_TIMEOUT ) {
++ printf("\nWait1 Timeout at bus %d!\n", busnum);
++ printf("Status 14 = %08x\n", ReadSOC_DD(devbase + 0x14));
++ exit(0);
++ }
++ } while (status != 0);
++
++ cnt = 0;
++ do {
++ status = ReadSOC_DD( devbase + 0x10 );
++ if ( ++cnt > I2C_TIMEOUT ) {
++ printf("\nWait2 Timeout at bus %d!\n", busnum);
++ printf("Status 14 = %08x\n", ReadSOC_DD(devbase + 0x14));
++ exit(0);
++ }
++ } while (status == 0);
++
++ WriteSOC_DD( devbase + 0x10, status );
++
++ return(status);
++}
++
++
++//------------------------------------------------------------
++ULONG writeb(ULONG start, ULONG data, ULONG stop)
++{
++ WriteSOC_DD( devbase + 0x20, data);
++ WriteSOC_DD( devbase + 0x14, 0x02 | start | (stop << 5) );
++ return(PollStatus());
++}
++
++//------------------------------------------------------------
++ULONG readb(ULONG last, ULONG stop)
++{
++ static ULONG data;
++
++ WriteSOC_DD( devbase + 0x14, 0x08 | (last << 4) | (stop << 5) );
++ data = PollStatus();
++
++ if (data & 0x4) {
++ data = ReadSOC_DD( devbase + 0x20 );
++ return(data >> 8);
++ }
++ else {
++ return(-1);
++ }
++}
++
++//------------------------------------------------------------
++void Initial(ULONG base, ULONG ckh, ULONG ckl)
++{
++ static ULONG ackh;
++ static ULONG ackl;
++ static ULONG divx;
++
++ actime(ckh, ckl, &divx, &ackh, &ackl);
++ WriteSOC_DD(base + 0x00, 0x1);
++ if (ReadSOC_DD(base + 0x00) != 0x1) {
++ printf("Controller initial fail : %x\n",base);
++ exit(0);
++ }
++ WriteSOC_DD(base + 0x04, 0x77700360 | (ackh << 16) | (ackl << 12) | divx);
++ WriteSOC_DD(base + 0x08, 0x0);
++ WriteSOC_DD(base + 0x0c, 0x0);
++ WriteSOC_DD(base + 0x10, 0xffffffff);
++ WriteSOC_DD(base + 0x14, 0x00);
++ WriteSOC_DD(base + 0x1C, 0xff0000);
++ WriteSOC_DD(base + 0x20, 0x00);
++}
++
++//------------------------------------------------------------
++void print_status(ULONG status)
++{
++ if ( status & 0x02 ) printf( "Device NAK\n" );
++ if ( status & 0x08 ) printf( "Arbitration Loss\n" );
++ if ( status & 0x10 ) printf( "STOP\n" );
++ if ( status & 0x20 ) printf( "Abnormal STOP\n" );
++ if ( status & 0x40 ) printf( "SCL Low timeout\n" );
++}
++
++//------------------------------------------------------------
++void readme()
++{
++ printf("\nVersion:%s\n", version_name);
++#ifdef LAN9303M
++ printf("LAN9303M [bus] [vir_PHY_adr] [speed] [func]\n");
++#else
++ printf("LAN9303 [bus] [vir_PHY_adr] [speed] [func]\n" );
++#endif
++ printf("[bus] | 1~14: I2C bus number\n" );
++ printf("[vir_PHY_adr] | 0~1: virtual PHY address\n" );
++ printf("[speed] | 1: 100M\n" );
++ printf(" | 2: 10 M\n" );
++ printf("[func] | 0: external loopback\n" );
++ printf(" | 1: internal loopback\n" );
++}
++
++//------------------------------------------------------------
++void quit()
++{
++ WriteSOC_DD( devbase + 0x14, 0x20 );
++ PollStatus();
++ readme();
++}
++
++//------------------------------------------------------------
++// Double-Word Read/Write
++//------------------------------------------------------------
++ULONG I2C_DWRead(ULONG adr)
++{
++ static ULONG status;
++ int i;
++
++ Initial(devbase, 10, 10);
++
++ if ( Print_DWRW )
++ printf("RAdr %02x: ", adr);
++
++ status = writeb( 1, LAN9303_I2C_ADR, 0 );
++ if ( I2C_Debug )
++ printf("R1W[%02x]%02x ", status, LAN9303_I2C_ADR);
++
++ if ( status != 0x1 ) {
++ print_status(status);
++ quit();
++ exit(0);
++ }
++
++ status = writeb(0, adr, 0);
++ if ( I2C_Debug )
++ printf("R2W[%02x]%02x ", status, adr);
++ if ( !(status & 0x1) ) {
++ print_status(status);
++ quit();
++ exit(0);
++ }
++
++ status = writeb(1, LAN9303_I2C_ADR | 0x1, 0);
++ if ( I2C_Debug )
++ printf("R3W[%02x]%02x ", status, LAN9303_I2C_ADR | 0x1);
++ if ( status != 0x1 ) {
++ print_status(status);
++ quit();
++ exit(0);
++ }
++
++ if ( I2C_Debug )
++ printf("R4");
++
++ data_rd = 0;
++ for (i = 24; i >= 0; i-=8) {
++ if (i == 0) byte = readb(1, 1);
++ else byte = readb(0, 0);
++
++ if ( I2C_Debug )
++ printf("%02x ", byte);
++ data_rd = data_rd | (byte << i);
++ }
++
++ if ( Print_DWRW )
++ printf("%08x\n", data_rd);
++
++ return (data_rd);
++} // End ULONG I2C_DWRead(ULONG adr)
++
++//------------------------------------------------------------
++void I2C_DWWrite(ULONG adr, ULONG dwdata)
++{
++ static ULONG status;
++ int i;
++ ULONG endx;
++
++ Initial(devbase, 10, 10);
++ if (Print_DWRW)
++ printf("WAdr %02x: ", adr);
++
++ status = writeb(1, LAN9303_I2C_ADR, 0);
++ if ( I2C_Debug )
++ printf("W1[%02x]%02x ", status, LAN9303_I2C_ADR);
++ if ( status != 0x1 ) {
++ print_status(status);
++ quit();
++ exit(0);
++ }
++ status = writeb(0, adr, 0);
++ if ( I2C_Debug )
++ printf("W2[%02x]%02x ", status, adr);
++ if ( !(status & 0x1) ) {
++ print_status(status);
++ quit();
++ exit(0);
++ }
++
++ if (I2C_Debug)
++ printf("W3");
++ endx = 0;
++ for (i = 24; i >= 0; i-=8) {
++ if (i == 0)
++ endx = 1;
++ byte = (dwdata >> i) & 0xff;
++ status = writeb(0, byte, endx);
++
++ if (I2C_Debug)
++ printf("[%02x]%02x ", status, byte);
++ if (!(status & 0x1)) {
++ print_status(status);
++ quit();
++ exit(0);
++ }
++ }
++
++ if (Print_DWRW) printf("%08x\n", dwdata);
++} // End void I2C_DWWrite(ULONG adr, ULONG dwdata)
++
++//------------------------------------------------------------
++// PHY Read/Write
++//------------------------------------------------------------
++ULONG LAN9303_PHY_Read(ULONG phy_adr, ULONG reg_adr)
++{
++ static ULONG data_rd;
++
++ I2C_DWWrite(0x2a, ((phy_adr & 0x1f) << 11) | ((reg_adr & 0x1f) << 6));//[0A8h]PMI_ACCESS
++ do {
++ data_rd = I2C_DWRead (0x2a);
++ } while(data_rd & 0x00000001);//[0A8h]PMI_ACCESS
++
++ data_rd = I2C_DWRead (0x29);//[0A4h]PMI_DATA
++ if (Print_PHYRW)
++ printf("PHY:%2d, Reg:%2d, Data:%08x\n", phy_adr, reg_adr, data_rd);
++
++ return(data_rd);
++}
++
++//------------------------------------------------------------
++void LAN9303_PHY_Write(ULONG phy_adr, ULONG reg_adr, ULONG data_wr)
++{
++ static ULONG data_rd;
++
++ I2C_DWWrite(0x29, data_wr);//[0A4h]PMI_DATA
++
++ I2C_DWWrite(0x2a, ((phy_adr & 0x1f) << 11) | ((reg_adr & 0x1f) << 6) | 0x2);//[0A8h]PMI_ACCESS
++ do {
++ data_rd = I2C_DWRead (0x2a);
++ } while(data_rd & 0x00000001);//[0A8h]PMI_ACCESS
++}
++
++//------------------------------------------------------------
++ULONG LAN9303_PHY_Read_WD(ULONG data_ctl)
++{
++ static ULONG data_rd;
++
++ I2C_DWWrite(0x2a, data_ctl);//[0A8h]PMI_ACCESS
++ do {
++ data_rd = I2C_DWRead (0x2a);
++ } while(data_rd & 0x00000001);//[0A8h]PMI_ACCESS
++
++ data_rd = I2C_DWRead (0x29);//[0A4h]PMI_DATA
++ if (Print_PHYRW)
++ printf("WD Data:%08x\n", data_ctl);
++
++ return(data_rd);
++}
++
++//------------------------------------------------------------
++void LAN9303_PHY_Write_WD(ULONG data_ctl, ULONG data_wr)
++{
++ static ULONG data_rd;
++
++ I2C_DWWrite( 0x29, data_wr ); //[0A4h]PMI_DATA
++ I2C_DWWrite( 0x2a, data_ctl ); //[0A8h]PMI_ACCESS
++ do {
++ data_rd = I2C_DWRead (0x2a);
++ } while(data_rd & 0x00000001); //[0A8h]PMI_ACCESS
++}
++
++//------------------------------------------------------------
++// Virtual PHY Read/Write
++//------------------------------------------------------------
++ULONG LAN9303_VirPHY_Read(ULONG reg_adr)
++{
++ static ULONG data_rd;
++
++ data_rd = I2C_DWRead (0x70+reg_adr);//[1C0h]
++ if ( Print_PHYRW )
++ printf("VirPHY Reg:%2d, Data:%08x\n", reg_adr, data_rd);
++
++ return(data_rd);
++}
++
++//------------------------------------------------------------
++void LAN9303_VirPHY_Write(ULONG reg_adr, ULONG data_wr)
++{
++ I2C_DWWrite(0x70+reg_adr, data_wr);//[1C0h]
++}
++
++//------------------------------------------------------------
++void LAN9303_VirPHY_RW(ULONG reg_adr, ULONG data_clr, ULONG data_set)
++{
++ I2C_DWWrite(0x70+reg_adr, (LAN9303_VirPHY_Read(reg_adr) & (~data_clr)) | data_set);//[1C0h]
++}
++
++//------------------------------------------------------------
++// PHY Read/Write
++//------------------------------------------------------------
++ULONG LAN9303_Read(ULONG adr)
++{
++ static ULONG data_rd;
++
++ I2C_DWWrite(0x6c, 0xc00f0000 | adr & 0xffff);//[1B0h]SWITCH_CSR_CMD
++ do {
++ data_rd = I2C_DWRead (0x6c);
++ } while(data_rd & 0x80000000);//[1B0h]SWITCH_CSR_CMD
++
++ return(I2C_DWRead (0x6b));//[1ACh]SWITCH_CSR_DATA
++}
++
++//------------------------------------------------------------
++void LAN9303_Write(ULONG adr, ULONG data)
++{
++ static ULONG data_rd;
++
++ I2C_DWWrite(0x6b, data);//[1ACh]SWITCH_CSR_DATA
++ I2C_DWWrite(0x6c, 0x800f0000 | adr & 0xffff);//[1B0h]SWITCH_CSR_CMD
++
++ do {
++ data_rd = I2C_DWRead (0x6c);
++ } while(data_rd & 0x80000000);//[1B0h]SWITCH_CSR_CMD
++}
++
++//------------------------------------------------------------
++void LAN9303(int num, int phy_adr, int speed, int int_loopback)
++{
++ static ULONG data_rd;
++
++ //------------------------------------------------------------
++ // I2C Initial
++ //------------------------------------------------------------
++ busnum = num;
++ if (busnum <= 7) devbase = 0x1E78A000 + ( busnum * 0x40);
++ else devbase = 0x1E78A300 + ((busnum-8) * 0x40);
++ Initial(devbase, 10, 10);
++
++ //------------------------------------------------------------
++ // LAN9303 Register Setting
++ //------------------------------------------------------------
++ printf("----> Start\n");
++ if (int_loopback == 0) {
++ //Force Speed & external loopback
++ if (speed == 1) { //100M
++ LAN9303_VirPHY_RW( 0, 0xffff, 0x2300 ); //adr clr set //VPHY_BASIC_CTRL
++ LAN9303_VirPHY_RW( 11, 0xffff, 0x2300 ); //adr clr set //P1_MII_BASIC_CONTROL
++ LAN9303_PHY_Write( phy_adr + 1, 0, 0x2300 );
++ LAN9303_PHY_Write( phy_adr + 2, 0, 0x2300 );
++ }
++ else {
++ LAN9303_VirPHY_RW( 0, 0xffff, 0x0100 ); //adr clr set //VPHY_BASIC_CTRL
++ LAN9303_VirPHY_RW( 11, 0xffff, 0x0100 ); //adr clr set //P1_MII_BASIC_CONTROL
++ LAN9303_PHY_Write( phy_adr + 1, 0, 0x0100);
++ LAN9303_PHY_Write( phy_adr + 2, 0, 0x0100);
++ }
++
++ LAN9303_Write( 0x180c, 0x00000001 ); // SWE_VLAN_WR_DATA
++ LAN9303_Write( 0x180b, 0x00000010 ); // SWE_VLAN_CMD
++ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
++
++ LAN9303_Write( 0x180c, 0x00000002 ); // SWE_VLAN_WR_DATA
++ LAN9303_Write( 0x180b, 0x00000011 ); // SWE_VLAN_CMD
++ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
++
++ LAN9303_Write( 0x180c, 0x00000003 ); // SWE_VLAN_WR_DATA
++ LAN9303_Write( 0x180b, 0x00000012 ); // SWE_VLAN_CMD
++ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
++
++#ifdef LAN9303M
++ LAN9303_Write( 0x180c, 0x00022001 ); // SWE_VLAN_WR_DATA
++ LAN9303_Write( 0x180b, 0x00000000 ); // SWE_VLAN_CMD
++ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
++
++ LAN9303_Write( 0x180c, 0x00024002 ); // SWE_VLAN_WR_DATA
++ LAN9303_Write( 0x180b, 0x00000001 ); // SWE_VLAN_CMD
++ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
++
++ LAN9303_Write( 0x180c, 0x0002a003 ); // SWE_VLAN_WR_DATA
++ LAN9303_Write( 0x180b, 0x00000002 ); // SWE_VLAN_CMD
++ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
++#else
++ LAN9303_Write( 0x180c, 0x0002a001 ); // SWE_VLAN_WR_DATA
++ LAN9303_Write( 0x180b, 0x00000000 ); // SWE_VLAN_CMD
++ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
++
++ LAN9303_Write( 0x180c, 0x0000a002 ); // SWE_VLAN_WR_DATA
++ LAN9303_Write( 0x180b, 0x00000001 ); // SWE_VLAN_CMD
++ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
++
++ LAN9303_Write( 0x180c, 0x00022003 ); // SWE_VLAN_WR_DATA
++ LAN9303_Write( 0x180b, 0x00000002 ); // SWE_VLAN_CMD
++ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
++#endif
++ LAN9303_Write( 0x1840, 0x00000007);
++ }
++ else if ( int_loopback == 1 ) {
++ //Force Speed & internal loopback
++ if ( speed == 1 ) {
++ //100M
++ LAN9303_VirPHY_RW( 0, 0xffff, 0x6300 ); // adr clr set //VPHY_BASIC_CTRL
++ LAN9303_VirPHY_RW( 11, 0xffff, 0x6300 ); // adr clr set //P1_MII_BASIC_CONTROL
++ LAN9303_PHY_Write( phy_adr + 1, 0, 0x6300 );
++ LAN9303_PHY_Write( phy_adr + 2, 0, 0x6300 );
++ }
++ else {
++ LAN9303_VirPHY_RW( 0, 0xffff, 0x4100 ); // adr clr set //VPHY_BASIC_CTRL
++ LAN9303_VirPHY_RW( 11, 0xffff, 0x4100 ); // adr clr set //P1_MII_BASIC_CONTROL
++ LAN9303_PHY_Write( phy_adr + 1, 0, 0x4100 );
++ LAN9303_PHY_Write( phy_adr + 2, 0, 0x4100 );
++ }
++ }
++ else {
++ //Force Speed
++ if (speed == 1) {
++ //100M
++ LAN9303_VirPHY_RW( 0, 0xffff, 0x2300 ); // adr clr set //VPHY_BASIC_CTRL
++ LAN9303_VirPHY_RW( 11, 0xffff, 0x2300 ); // adr clr set //P1_MII_BASIC_CONTROL
++ LAN9303_PHY_Write( phy_adr + 1, 0, 0x2300 );
++ LAN9303_PHY_Write( phy_adr + 2, 0, 0x2300 );
++ }
++ else {
++ LAN9303_VirPHY_RW( 0, 0xffff, 0x0100 ); // adr clr set //VPHY_BASIC_CTRL
++ LAN9303_VirPHY_RW( 11, 0xffff, 0x0100 ); // adr clr set //P1_MII_BASIC_CONTROL
++ LAN9303_PHY_Write( phy_adr + 1, 0, 0x0100 );
++ LAN9303_PHY_Write( phy_adr + 2, 0, 0x0100 );
++ }
++#ifdef LAN9303M
++#else
++ if (int_loopback == 3) {
++ //[LAN9303]IEEE measurement
++ data_rd = LAN9303_PHY_Read(phy_adr+1, 27);//PHY_SPECIAL_CONTROL_STAT_IND_x
++ LAN9303_PHY_Write(phy_adr+1, 27, (data_rd & 0x9fff) | 0x8000);//PHY_SPECIAL_CONTROL_STAT_IND_x
++
++ data_rd = LAN9303_PHY_Read(phy_adr+2, 27);//PHY_SPECIAL_CONTROL_STAT_IND_x
++ LAN9303_PHY_Write(phy_adr+2, 27, (data_rd & 0x9fff) | 0x8000);//PHY_SPECIAL_CONTROL_STAT_IND_x
++ }
++#endif
++ } // End if (int_loopback == 0)
++} // End void LAN9303(int num, int phy_adr, int speed, int int_loopback)
++#endif // SUPPORT_PHY_LAN9303
++
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/LIB.H b/arch/arm/cpu/arm926ejs/aspeed/LIB.H
+new file mode 100644
+index 0000000..a7c61dd
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/LIB.H
+@@ -0,0 +1,37 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef LIB_H
++#define LIB_H
++
++#include "TYPEDEF.H"
++
++//
++// Macro
++//
++#define INTFUNC int386
++
++#define OUTDWPORT outpd
++#define INDWPORT inpd
++#define OUTPUT outp
++#define INPUT inp
++
++//
++// PCI
++//
++ULONG ReadPCIReg (ULONG ulPCIConfigAddress, BYTE jOffest, ULONG ulMask);
++ULONG FindPCIDevice (USHORT usVendorID, USHORT usDeviceID, USHORT usBusType);
++VOID WritePCIReg (ULONG ulPCIConfigAddress, BYTE jOffest, ULONG ulMask, ULONG ulData);
++
++//
++// Map Resource
++//
++ULONG MapPhysicalToLinear (ULONG ulBaseAddress, ULONG ulSize);
++#endif
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/LIB.c b/arch/arm/cpu/arm926ejs/aspeed/LIB.c
+new file mode 100644
+index 0000000..f2a0c54
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/LIB.c
+@@ -0,0 +1,184 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define LIB_C
++static const char ThisFile[] = "LIB.c";
++
++#include "SWFUNC.H"
++
++#ifdef SLT_UBOOT
++ #include <common.h>
++ #include <command.h>
++#endif
++#ifdef SLT_DOS
++#include <stdlib.h>
++#include <stdio.h>
++#include <time.h>
++#include <conio.h>
++#include <dos.h>
++#include <mem.h>
++#endif
++
++#include "LIB.H"
++#include "TYPEDEF.H"
++
++#ifdef USE_P2A
++//------------------------------------------------------------
++// PCI
++//------------------------------------------------------------
++ULONG ReadPCIReg (ULONG ulPCIConfigAddress, BYTE jOffest, ULONG ulMask)
++{
++#ifndef Windows
++ OUTDWPORT(0xcf8, ulPCIConfigAddress + jOffest);
++
++ return (((ULONG)INDWPORT(0xcfc)) & ulMask);
++#else
++ WRITE_PORT_ULONG((PULONG)0xcf8, ulPCIConfigAddress + jOffest);
++
++ return (READ_PORT_ULONG((PULONG)0xcfc) & ulMask);
++#endif
++}
++
++//------------------------------------------------------------
++VOID WritePCIReg (ULONG ulPCIConfigAddress, BYTE jOffest, ULONG ulMask, ULONG ulData)
++{
++#ifndef Windows
++ OUTDWPORT(0xcf8, ulPCIConfigAddress + jOffest);
++ OUTDWPORT(0xcfc, (INDWPORT(0xcfc) & ulMask | ulData));
++#else
++ WRITE_PORT_ULONG((PULONG)0xcf8, ulPCIConfigAddress + jOffest);
++ WRITE_PORT_ULONG((PULONG)0xcfc, (READ_PORT_ULONG((PULONG)0xcfc) & ulMask | ulData));
++#endif
++}
++
++//------------------------------------------------------------
++ULONG FindPCIDevice (USHORT usVendorID, USHORT usDeviceID, USHORT usBusType)
++{
++//Return: ulPCIConfigAddress
++//usBusType: ACTIVE/PCI/AGP/PCI-E
++
++ ULONG Base[256];
++ ULONG ebx;
++ USHORT i;
++ USHORT j;
++
++ for (i = 0; i < 256; i++) {
++ Base[i] = 0x80000000 + 0x10000 * i;
++ }
++
++ if (usBusType == PCI)
++ {
++ ebx = 0x80000000;
++ }
++ else if (usBusType == PCIE)
++ {
++ ebx = 0x80020000;
++ }
++ else // AGP and ACTIVE
++ {
++ ebx = 0x80010000;
++ }
++
++ if ( usBusType != ACTIVE ) //AGP, PCI, PCIE
++ {
++ for (i = 0; i < 32; i++)
++ {
++ ebx = ebx + (0x800);
++ if (((USHORT)ReadPCIReg(ebx, 0, 0xffff) == usVendorID) && ((USHORT)(ReadPCIReg(ebx, 0, 0xffff0000) >> 16) == usDeviceID))
++ {
++ return ebx;
++ }
++ }
++ return 0;
++ }
++ else //ACTIVE
++ {
++ for (j = 0; j < 256; j++)
++ {
++ ebx = Base[j];
++ for (i = 0; i < 32; i++)
++ {
++ ebx = ebx + (0x800);
++ if (((USHORT)ReadPCIReg(ebx, 0, 0xffff) == usVendorID) && ((USHORT)(ReadPCIReg(ebx, 0, 0xffff0000) >> 16) == usDeviceID))
++ {
++ return ebx;
++ }
++ }
++ }
++ return 0;
++ }
++} // End ULONG FindPCIDevice (USHORT usVendorID, USHORT usDeviceID, USHORT usBusType)
++#endif
++//------------------------------------------------------------
++// Allocate Resource
++//------------------------------------------------------------
++#ifdef SLT_DOS
++ULONG InitDOS32()
++{
++ union REGS regs ;
++
++ regs.w.ax = 0xee00;
++ INTFUNC(0x31, &regs, &regs) ;
++
++ if(regs.w.ax >= 0x301) // DOS32 version >= 3.01 ?
++ return 1;
++ else
++ return 0;
++}
++
++//------------------------------------------------------------
++USHORT CheckDOS()
++{
++ union REGS regs;
++
++ regs.w.ax = 0xeeff;
++ int386(0x31, &regs, &regs);
++ if (regs.x.eax == 0x504d4457)
++ {
++ return 0;
++ } else {
++ printf("PMODEW Init. fail\n");
++ return 1;
++ }
++}
++
++//------------------------------------------------------------
++ULONG MapPhysicalToLinear (ULONG ulBaseAddress, ULONG ulSize)
++{
++ union REGS regs;
++
++ regs.w.ax = 0x0800; // map physcial memory
++ regs.w.bx = ulBaseAddress >> 16; // bx:cx = physical address
++ regs.w.cx = ulBaseAddress;
++ regs.w.si = ulSize >> 16; // si:di = mapped memory block size
++ regs.w.di = ulSize;
++ INTFUNC(0x31, &regs, &regs); // int386(0x31, &regs, &regs);
++ if (regs.w.cflag == 0)
++ return (ULONG) (regs.w.bx << 16 + regs.w.cx); // Linear Addr = bx:cx
++ else
++ return 0;
++}
++
++//------------------------------------------------------------
++USHORT FreePhysicalMapping(ULONG udwLinAddress)
++{
++ union REGS regs;
++
++ regs.w.ax = 0x0801;
++ regs.w.bx = udwLinAddress >> 16;
++ regs.w.cx = udwLinAddress & 0xFFFF;
++ int386(0x31, &regs, &regs);
++
++ if (regs.x.cflag)
++ return ((USHORT) 0);
++ else return ((USHORT) 1);
++}
++#endif
++
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/LIB_SPI.H b/arch/arm/cpu/arm926ejs/aspeed/LIB_SPI.H
+new file mode 100644
+index 0000000..78c8f1e
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/LIB_SPI.H
+@@ -0,0 +1,23 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef LIB_SPI_H
++#define LIB_SPI_H
++
++#ifdef SPI_BUS
++ // MMIO Functions
++ VOID MOutwm (ULONG, ULONG, USHORT);
++ VOID MOutdwm (ULONG, ULONG, ULONG);
++ ULONG MIndwm (ULONG, ULONG);
++
++ void spim_init(int cs);
++#endif
++
++#endif // LIB_SPI_H
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/MAC.H b/arch/arm/cpu/arm926ejs/aspeed/MAC.H
+new file mode 100644
+index 0000000..6732117
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/MAC.H
+@@ -0,0 +1,157 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef MAC_H
++#define MAC_H
++
++#ifdef SPI_BUS
++ #include <stdio.h>
++ #include <stdlib.h>
++ #include <time.h>
++ #define SPI_CS 1
++#endif
++// ( USE_P2A | USE_LPC )
++
++#if defined(LinuxAP)
++ #include <stdio.h>
++ #include <stdlib.h>
++ #include <string.h>
++ #include <stdarg.h>
++ #include <unistd.h>
++ #include <string.h>
++ #include <fcntl.h>
++ #include <pthread.h>
++ #include <sys/mman.h>
++ #include <sys/io.h>
++#endif
++#ifdef SLT_UBOOT
++ #include <common.h>
++ #include <command.h>
++#endif
++#ifdef SLT_DOS
++ #include <stdio.h>
++ #include <stdlib.h>
++ #include <time.h>
++ #include <conio.h>
++ #include <dos.h>
++ #include <mem.h>
++#endif
++
++#include "NCSI.H"
++#include "IO.H"
++
++// --------------------------------------------------------------
++// Define
++// --------------------------------------------------------------
++
++//#define Force_Enable_MAC34 //[ON][SLT:off] (Force enable mac34)
++//#define Force_Enable_NewMDIO //[off][SLT:off] (Force enable new MDC/MDIO)
++//#define Enable_Fast_SCU //[off]
++//#define Enable_Old_Style //[off]
++#define ENABLE_DASA //[ON]
++//#define Enable_AST2300_Int125MHz //[off]
++//#define ENABLE_ARP_2_WOL //[off]
++//#define Enable_MAC_SWRst //[off]
++
++#define Enable_Runt
++//#define Enable_Jumbo
++//#define Enable_BufMerge
++//#define Disable_VGA
++
++//#define SelectSimpleBoundary //[off] Using in debug
++//#define SelectSimpleData //[off] Using in debug
++//#define SelectSimpleLength 1512 //[off] 60(0x3c) ~ 1514(0x5ea); 1512(0x5e8)
++//#define SelectDesNumber 8 //[off] 1 ~
++//#define SelectSimpleDA //[off] Using in debug
++//#define SelectSimpleDes //[off]
++//#define SelectLengthInc //[off] Using in debug
++
++#define SimpleData_Fix //[ON] Using in debug
++#define SimpleData_FixNum 12
++#define SimpleData_FixVal00 0x00000000 //[0]no SelectSimpleDA: (60: 0412 8908)(1512: e20d e9da)
++#define SimpleData_FixVal01 0xffffffff //[0]no SelectSimpleDA: (60: f48c f14d)(1512: af05 260c)
++#define SimpleData_FixVal02 0x55555555 //[0]no SelectSimpleDA: (60: 5467 5ecb)(1512: d90a 5368)
++#define SimpleData_FixVal03 0xaaaaaaaa //[0]no SelectSimpleDA: (60: a4f9 268e)(1512: 9402 9cbe)
++#define SimpleData_FixVal04 0x5a5a5a5a //[1]no SelectSimpleDA: (60: 7f01 e22d)(1512: 4fd3 8012)
++#define SimpleData_FixVal05 0xc3c3c3c3 //[1]no SelectSimpleDA: (60: 5916 02d5)(1512: 99f1 6127)
++#define SimpleData_FixVal06 0x96969696 //[1]no SelectSimpleDA: (60: 0963 d516)(1512: a2f6 db95)
++#define SimpleData_FixVal07 0xf0f0f0f0 //[1]no SelectSimpleDA: (60: dfea 4dab)(1512: 39dc f576)
++#define SimpleData_FixVal08 0x5555aaaa //[2]no SelectSimpleDA: (60: b61b 5777)(1512: 4652 ddb0)
++#define SimpleData_FixVal09 0xffff0000 //[2]no SelectSimpleDA: (60: 16f0 f8f1)(1512: 305d a8d4)
++#define SimpleData_FixVal10 0x5a5aa5a5 //[2]no SelectSimpleDA: (60: 9d7d eb91)(1512: d08b 0eca)
++#define SimpleData_FixVal11 0xc3c33c3c //[2]no SelectSimpleDA: (60: bb6a 0b69)(1512: 06a9 efff)
++
++#define SelectSimpleDA_Dat0 0x67052301
++#define SelectSimpleDA_Dat1 0xe0cda089
++#define SelectSimpleDA_Dat2 0x98badcfe
++
++#define SelectWOLDA_DatH 0x206a
++#define SelectWOLDA_DatL 0x8a374d9b
++
++#define MOVE_DATA_MB_SEC 800 // MByte per second to move data
++
++//---------------------------------------------------------
++// Frame size
++//---------------------------------------------------------
++#define ENABLE_RAND_SIZE 0
++#define Rand_Sed 0xffccd
++#define FRAME_Rand_Simple 0
++#define MIN_FRAME_RAND_SIZE 60
++#define MAX_FRAME_RAND_SIZE 1514
++
++#define FRAME_SELH_PERD 7
++#ifdef Enable_Jumbo
++// #define FRAME_LENH 9212 //max:9212
++// #define FRAME_LENL 9211 //max:9212
++ #define FRAME_LENH 9212 //max:9212
++ #define FRAME_LENL 9212 //max:9212
++// #define FRAME_LENH 8120
++// #define FRAME_LENL 8119
++// #define FRAME_LENH 7000
++// #define FRAME_LENL 6999
++// #define FRAME_LENH 4095
++// #define FRAME_LENL 4094
++// #define FRAME_LENH 2040
++// #define FRAME_LENL 2039
++#else
++ #ifdef SelectSimpleLength
++// #define FRAME_LENH ( SelectSimpleLength + 1 )
++// #define FRAME_LENL ( SelectSimpleLength )
++ #define FRAME_LENH SelectSimpleLength
++ #define FRAME_LENL SelectSimpleLength
++ #else
++// #define FRAME_LENH 1514 //max:1514
++// #define FRAME_LENL 1513 //max:1514
++ #define FRAME_LENH 1514 //max:1514
++ #define FRAME_LENL 1514 //max:1514
++ #endif
++#endif
++
++const ULONG ARP_org_data[16] = {
++ 0xffffffff,
++ 0x0000ffff, // SA:00 00
++ 0x12345678, // SA:12 34 56 78
++ 0x01000608, // ARP(0x0806)
++ 0x04060008,
++ 0x00000100, // sender MAC Address: 00 00
++ 0x12345678, // sender MAC Address: 12 34 56 78
++ 0xeb00a8c0, // sender IP Address: 192.168.0.235
++ 0x00000000, // target MAC Address: 00 00 00 00
++ 0xa8c00000, // target MAC Address: 00 00, sender IP Address:192.168
++ 0x00000100, // sender IP Address: 0.1
++// 0x0000de00, // sender IP Address: 0.222
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0xc68e2bd5
++};
++
++#endif // MAC_H
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/MAC.c b/arch/arm/cpu/arm926ejs/aspeed/MAC.c
+new file mode 100644
+index 0000000..829da92
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/MAC.c
+@@ -0,0 +1,2085 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define MAC_C
++static const char ThisFile[] = "MAC.c";
++
++#include "SWFUNC.H"
++
++#ifdef SLT_UBOOT
++ #include <common.h>
++ #include <command.h>
++ #include <COMMINF.H>
++ #include "STDUBOOT.H"
++#endif
++#ifdef SLT_DOS
++ #include <stdio.h>
++ #include <stdlib.h>
++ #include <conio.h>
++ #include <string.h>
++ #include "COMMINF.H"
++#endif
++
++#include "MAC.H"
++
++double Avg_frame_len;
++ULONG Check_Des_Val;
++ULONG wp_fir;
++ULONG wp;
++ULONG FRAME_LEN_Cur;
++ULONG gdata;
++ULONG CheckDesFail_DesNum;
++ULONG VGAMode;
++ULONG SCU_1ch_old;
++ULONG SCU_0ch_old;
++ULONG SCU_48h_default;
++ULONG SCU_2ch_old;
++ULONG SCU_80h_old;
++ULONG SCU_74h_old;
++ULONG SCU_a4h_old;
++ULONG SCU_88h_old;
++ULONG WDT_0ch_old;
++ULONG SCU_04h_mix;
++ULONG SCU_04h_old;
++ULONG WDT_2ch_old;
++char SCU_oldvld = 0;
++
++#ifdef SLT_UBOOT
++#else
++ static double timeused;
++#endif
++// -------------------------------------------------------------
++
++void Debug_delay (void) {
++ #ifdef DbgPrn_Enable_Debug_delay
++ GET_CAHR();
++ #endif
++}
++
++
++
++
++void dump_mac_ROreg (void) {
++ DELAY(Delay_MACDump);
++ printf("\n");
++ printf("[MAC-H] ROReg A0h~ACh: %08lx %08lx %08lx %08lx\n", ReadSOC_DD(H_MAC_BASE+0xA0), ReadSOC_DD(H_MAC_BASE+0xA4), ReadSOC_DD(H_MAC_BASE+0xA8), ReadSOC_DD(H_MAC_BASE+0xAC));
++ printf("[MAC-H] ROReg B0h~BCh: %08lx %08lx %08lx %08lx\n", ReadSOC_DD(H_MAC_BASE+0xB0), ReadSOC_DD(H_MAC_BASE+0xB4), ReadSOC_DD(H_MAC_BASE+0xB8), ReadSOC_DD(H_MAC_BASE+0xBC));
++ printf("[MAC-H] ROReg C0h~C8h: %08lx %08lx %08lx \n", ReadSOC_DD(H_MAC_BASE+0xC0), ReadSOC_DD(H_MAC_BASE+0xC4), ReadSOC_DD(H_MAC_BASE+0xC8));
++}
++
++//------------------------------------------------------------
++// SCU
++//------------------------------------------------------------
++void recov_scu (void) {
++ #ifdef DbgPrn_FuncHeader
++ printf ("recov_scu\n");
++ Debug_delay();
++ #endif
++
++ //MAC
++ WriteSOC_DD( H_MAC_BASE + 0x08, MAC_08h_old );
++ WriteSOC_DD( H_MAC_BASE + 0x0c, MAC_0ch_old );
++ WriteSOC_DD( H_MAC_BASE + 0x40, MAC_40h_old );
++
++ //SCU
++ WriteSOC_DD( SCU_BASE + 0x04, SCU_04h_old );
++ WriteSOC_DD( SCU_BASE + 0x08, SCU_08h_old );
++ WriteSOC_DD( SCU_BASE + 0x0c, SCU_0ch_old );
++ WriteSOC_DD( SCU_BASE + 0x1c, SCU_1ch_old );
++ WriteSOC_DD( SCU_BASE + 0x2c, SCU_2ch_old );
++ WriteSOC_DD( SCU_BASE + 0x48, SCU_48h_old );
++// WriteSOC_DD( SCU_BASE + 0x70, SCU_70h_old );
++ WriteSOC_DD( SCU_BASE + 0x74, SCU_74h_old );
++ WriteSOC_DD( SCU_BASE + 0x7c, SCU_7ch_old );
++ WriteSOC_DD( SCU_BASE + 0x80, SCU_80h_old );
++ WriteSOC_DD( SCU_BASE + 0x88, SCU_88h_old );
++ WriteSOC_DD( SCU_BASE + 0x90, SCU_90h_old );
++ WriteSOC_DD( SCU_BASE + 0xa4, SCU_a4h_old );
++ WriteSOC_DD( SCU_BASE + 0xac, SCU_ach_old );
++ #ifdef AST1010_IOMAP
++ WriteSOC_DD( SCU_BASE + 0x11C, SCU_11Ch_old );
++ #endif
++
++ //WDT
++ #ifdef AST1010_IOMAP
++ #else
++ // WriteSOC_DD(0x1e78500c, WDT_0ch_old);
++ // WriteSOC_DD(0x1e78502c, WDT_2ch_old);
++ #endif
++
++ if ( ASTChipType == 3 ) {
++ if ( SCU_f0h_old & 0x01 ) WriteSOC_DD( SCU_BASE + 0xf0, 0xAEED0001 ); //Enable MAC34
++ if ( SCU_f0h_old & 0x02 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x2000DEEA ); //Enable Decode
++ if ( SCU_f0h_old & 0x04 ) WriteSOC_DD( SCU_BASE + 0xf0, 0xA0E0E0D3 ); //Enable I2S
++ if ( SCU_f0h_old & 0x08 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x4D0E0E0A ); //Enable PCI Host
++ if ( SCU_f0h_old & 0x10 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x10ADDEED ); //Enable IR
++ if ( SCU_f0h_old & 0x20 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x66559959 ); //Enabel Buffer Merge
++ if ( SCU_f0h_old & 0x40 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x68961A33 ); //Enable PS2 IO
++ if ( SCU_f0h_old & 0x80 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x68971A33 ); //Enable PS2 IO
++ }
++} // End void recov_scu (void)
++
++void read_scu (void) {
++ #ifdef DbgPrn_FuncHeader
++ printf ("read_scu\n");
++ Debug_delay();
++ #endif
++
++ if (!SCU_oldvld) {
++ //SCU
++ SCU_04h_old = ReadSOC_DD( SCU_BASE + 0x04 );
++ SCU_08h_old = ReadSOC_DD( SCU_BASE + 0x08 );
++ SCU_0ch_old = ReadSOC_DD( SCU_BASE + 0x0c );
++ SCU_1ch_old = ReadSOC_DD( SCU_BASE + 0x1c );
++ SCU_2ch_old = ReadSOC_DD( SCU_BASE + 0x2c );
++ SCU_48h_old = ReadSOC_DD( SCU_BASE + 0x48 );
++ SCU_70h_old = ReadSOC_DD( SCU_BASE + 0x70 );
++ SCU_74h_old = ReadSOC_DD( SCU_BASE + 0x74 );
++ SCU_7ch_old = ReadSOC_DD( SCU_BASE + 0x7c );
++ SCU_80h_old = ReadSOC_DD( SCU_BASE + 0x80 );
++ SCU_88h_old = ReadSOC_DD( SCU_BASE + 0x88 );
++ SCU_90h_old = ReadSOC_DD( SCU_BASE + 0x90 );
++ SCU_a4h_old = ReadSOC_DD( SCU_BASE + 0xa4 );
++ SCU_ach_old = ReadSOC_DD( SCU_BASE + 0xac );
++ SCU_f0h_old = ReadSOC_DD( SCU_BASE + 0xf0 );
++ #ifdef AST1010_IOMAP
++ SCU_11Ch_old = ReadSOC_DD( SCU_BASE + 0x11C );
++ #endif
++
++ //WDT
++ #ifdef AST1010_IOMAP
++ #else
++ WDT_0ch_old = ReadSOC_DD( 0x1e78500c );
++ WDT_2ch_old = ReadSOC_DD( 0x1e78502c );
++ #endif
++
++ SCU_oldvld = 1;
++ } // End if (!SCU_oldvld)
++} // End read_scu()
++
++void Setting_scu (void)
++{
++ //SCU
++ if (AST1010) {
++ do {
++ WriteSOC_DD( SCU_BASE + 0x00 , 0x1688a8a8);
++ #ifndef SLT_UBOOT
++ WriteSOC_DD( SCU_BASE + 0x70 , SCU_70h_old & 0xfffffffe); // Disable CPU
++ #endif
++ } while ( ReadSOC_DD( SCU_BASE + 0x00 ) != 0x1 );
++
++ #if( AST1010_IOMAP == 1)
++ WriteSOC_DD( SCU_BASE + 0x11C, 0x00000000); // Disable Cache functionn
++ #endif
++ }
++ else {
++ do {
++ WriteSOC_DD( SCU_BASE + 0x00, 0x1688a8a8);
++ #ifndef SLT_UBOOT
++ WriteSOC_DD( SCU_BASE + 0x70, SCU_70h_old | 0x3 ); // Disable CPU
++ #endif
++ } while ( ReadSOC_DD( SCU_BASE + 0x00 ) != 0x1 );
++ } // End if (AST1010)
++
++ //WDT
++ #ifdef AST1010_IOMAP
++ #else
++ WriteSOC_DD( 0x1e78500c, WDT_0ch_old & 0xfffffffc );
++ WriteSOC_DD( 0x1e78502c, WDT_2ch_old & 0xfffffffc );
++ #endif
++}
++
++//------------------------------------------------------------
++void init_scu1 (void) {
++ #ifdef DbgPrn_FuncHeader
++ printf ("init_scu1\n");
++ Debug_delay();
++ #endif
++
++ if (AST3200) {
++ WriteSOC_DD( SCU_BASE + 0x0c, (SCU_0ch_old & 0xffefffff) );//Clock Stop Control
++ }
++ else if (AST1010) {
++ WriteSOC_DD( SCU_BASE + 0x0c, ( SCU_0ch_old & 0xffffffbf ) );//Clock Stop Control
++ WriteSOC_DD( SCU_BASE + 0x88, ((SCU_88h_old & 0x003fffff ) | 0xffc00000) );//Multi-function Pin Control
++ }
++ else if (AST2300) {
++#ifdef Enable_BufMerge
++ WriteSOC_DD( SCU_BASE + 0xf0, 0x66559959 );//MAC buffer merge
++#endif
++
++#ifdef Enable_AST2300_Int125MHz
++ SCU_48h_mix = (SCU_48h_old & 0xf0000000) | 0x80000000;
++// WriteSOC_DD( SCU_BASE + 0xf0, 0xa0e0e0d3 );//Enable I2S
++// WriteSOC_DD( SCU_BASE + 0x04, SCU_04h_old & 0xfffdffff );//Rst(Enable I2S)
++//
++//// WriteSOC_DD( 0x1e6e5020, ReadSOC_DD(0x1e6e5020) | 0x00010000 );//P_I2SPLLAdjEnable
++// WriteSOC_DD( 0x1e6e5020, ReadSOC_DD(0x1e6e5020) | 0x00000000 );//P_I2SPLLAdjEnable
++// WriteSOC_DD( 0x1e6e5024, 0x00000175 );//P_I2SPLLAdjCnt
++
++// WriteSOC_DD( SCU_BASE + 0x1c, 0x0000a51a );//124800000(24MHz)
++// WriteSOC_DD( SCU_BASE + 0x1c, 0x0000a92f );//125333333(24MHz)
++// WriteSOC_DD( SCU_BASE + 0x1c, 0x0000587d );//125000000(24MHz)
++ WriteSOC_DD( SCU_BASE + 0x1c, 0x00006c7d );//125000000(24MHz)
++ WriteSOC_DD( SCU_BASE + 0x2c, 0x00300000 | (SCU_2ch_old & 0xffcfffef) );//D-PLL assigned to VGA, D2-PLL assigned to I2S.
++ WriteSOC_DD( SCU_BASE + 0x48, 0x80000000 | SCU_48h_old );//125MHz come from I2SPLL
++#else
++ SCU_48h_mix = (SCU_48h_old & 0xf0000000);
++#endif
++ switch (SelectMAC) {
++ case 0 :
++ WriteSOC_DD( SCU_BASE + 0x88, (SCU_88h_old & 0x3fffffff) | 0xc0000000 );//[31]MAC1 MDIO, [30]MAC1 MDC
++ break;
++ case 1 :
++ WriteSOC_DD( SCU_BASE + 0x90, (SCU_90h_old & 0xfffffffb) | 0x00000004 );//[2 ]MAC2 MDC/MDIO
++ break;
++ case 2 :
++ case 3 :
++ default : break;
++ }
++
++ WriteSOC_DD(SCU_BASE+0x0c, (SCU_0ch_old & 0xff0fffff) );//Clock Stop Control
++// WriteSOC_DD(SCU_BASE+0x80, (SCU_80h_old & 0xfffffff0) | 0x0000000f);//MAC1LINK/MAC2LINK
++ }
++ else {
++ switch (SelectMAC) {
++ case 0 :
++// WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xfdffffff) | 0x02000000);//[25]MAC1 PHYLINK
++ break;
++ case 1 :
++ if (MAC2_RMII) {
++// WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xfbefffff) | 0x04100000);//[26]MAC2 PHYLINK, [21]MAC2 MII, [20]MAC2 MDC/MDIO
++ WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xffefffff) | 0x00100000);//[26]MAC2 PHYLINK, [21]MAC2 MII, [20]MAC2 MDC/MDIO
++ } else {
++// WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xfbcfffff) | 0x04300000);//[26]MAC2 PHYLINK, [21]MAC2 MII, [20]MAC2 MDC/MDIO
++ WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xffcfffff) | 0x00300000);//[26]MAC2 PHYLINK, [21]MAC2 MII, [20]MAC2 MDC/MDIO
++ }
++ break;
++ default : break;
++ } // End switch (SelectMAC)
++ } // End if (AST3200)
++} // End void init_scu1 (void)
++
++//------------------------------------------------------------
++void init_scu_macrst (void) {
++
++#ifdef Enable_AST2300_Int125MHz
++ if (ASTChipType == 3) {
++ SCU_04h_mix = SCU_04h_old & 0xfffdffff;
++ } else {
++ SCU_04h_mix = SCU_04h_old;
++ }
++#else
++ SCU_04h_mix = SCU_04h_old;
++#endif
++
++ WriteSOC_DD ( SCU_BASE + 0x04, (SCU_04h_mix & ~SCU_04h) | SCU_04h);//Rst
++ DELAY(Delay_SCU);
++ WriteSOC_DD ( SCU_BASE + 0x04, (SCU_04h_mix & ~SCU_04h) );//Enable Engine
++// DELAY(Delay_SCU);
++} // End void init_scu_macrst (void)
++
++//------------------------------------------------------------
++void init_scu2 (void) {
++
++#ifdef SCU_74h
++ #ifdef DbgPrn_FuncHeader
++ printf ("init_scu2\n");
++ Debug_delay();
++ #endif
++
++ WriteSOC_DD( SCU_BASE + 0x74, SCU_74h_old | SCU_74h );//PinMux
++ delay(Delay_SCU);
++#endif
++
++} // End void init_scu2 (void)
++
++//------------------------------------------------------------
++void init_scu3 (void) {
++
++#ifdef SCU_74h
++ #ifdef DbgPrn_FuncHeader
++ printf ("init_scu3\n");
++ Debug_delay();
++ #endif
++
++ WriteSOC_DD( SCU_BASE + 0x74, SCU_74h_old | (SCU_74h & 0xffefffff) );//PinMux
++ delay(Delay_SCU);
++#endif
++
++} // End void init_scu3 (void)
++
++//------------------------------------------------------------
++// MAC
++//------------------------------------------------------------
++void init_mac (ULONG base, ULONG tdexbase, ULONG rdexbase) {
++ #ifdef DbgPrn_FuncHeader
++ printf ("init_mac\n");
++ Debug_delay();
++ #endif
++
++#ifdef Enable_MAC_SWRst
++ WriteSOC_DD( base + 0x50, 0x80000000 | MAC_50h | MAC_50h_Speed);
++// WriteSOC_DD( base + 0x50, 0x80000000);
++
++ while (0x80000000 & ReadSOC_DD(base+0x50)) {
++//printf(".");
++ DELAY(Delay_MACRst);
++ }
++ DELAY(Delay_MACRst);
++#endif
++
++ WriteSOC_DD( base + 0x20, (tdexbase + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
++ WriteSOC_DD( base + 0x24, (rdexbase + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
++
++#ifdef MAC_30h
++ WriteSOC_DD( base + 0x30, MAC_30h);//Int Thr/Cnt
++#endif
++
++#ifdef MAC_34h
++ WriteSOC_DD( base + 0x34, MAC_34h);//Poll Cnt
++#endif
++
++#ifdef MAC_38h
++ WriteSOC_DD( base + 0x38, MAC_38h);
++#endif
++
++#ifdef MAC_40h
++ if (Enable_MACLoopback) {
++ if (AST2300_NewMDIO) WriteSOC_DD( base + 0x40, MAC_40h | 0x80000000);
++ else WriteSOC_DD( base + 0x40, MAC_40h);
++ }
++#endif
++
++#ifdef MAC_48h
++ WriteSOC_DD( base + 0x48, MAC_48h);
++#endif
++
++ if ( ModeSwitch == MODE_NSCI )
++ WriteSOC_DD( base + 0x4c, NCSI_RxDMA_PakSize);
++ else
++ WriteSOC_DD( base + 0x4c, DMA_PakSize);
++
++ WriteSOC_DD( base + 0x50, MAC_50h | MAC_50h_Speed | 0xf);
++ DELAY(Delay_MACRst);
++} // End void init_mac (ULONG base, ULONG tdexbase, ULONG rdexbase)
++
++//------------------------------------------------------------
++// Basic
++//------------------------------------------------------------
++void FPri_RegValue (BYTE option) {
++
++#ifdef SLT_UBOOT
++#else
++ time_t timecur;
++#endif
++
++ FILE_VAR
++
++ GET_OBJ( option )
++
++ PRINT(OUT_OBJ "[SCU] 04:%08lx 08:%08lx 0c:%08lx 48:%08lx\n", SCU_04h_old, SCU_08h_old, SCU_0ch_old, SCU_48h_old);
++ PRINT(OUT_OBJ "[SCU] 70:%08lx 74:%08lx 7c:%08lx\n", SCU_70h_old, SCU_74h_old, SCU_7ch_old);
++ PRINT(OUT_OBJ "[SCU] 80:%08lx 88:%08lx 90:%08lx f0:%08lx\n", SCU_80h_old, SCU_88h_old, SCU_90h_old, SCU_f0h_old);
++ PRINT(OUT_OBJ "[SCU] a4:%08lx ac:%08lx\n", SCU_a4h_old, SCU_ach_old);
++ PRINT(OUT_OBJ "[WDT] 0c:%08lx 2c:%08lx\n", WDT_0ch_old, WDT_2ch_old);
++ PRINT(OUT_OBJ "[MAC] 08:%08lx 0c:%08lx\n", MAC_08h_old, MAC_0ch_old);
++ PRINT(OUT_OBJ "[MAC] A0|%08lx %08lx %08lx %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0xa0), ReadSOC_DD( MAC_PHYBASE + 0xa4 ), ReadSOC_DD( MAC_PHYBASE + 0xa8 ), ReadSOC_DD(MAC_PHYBASE + 0xac ) );
++ PRINT(OUT_OBJ "[MAC] B0|%08lx %08lx %08lx %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0xb0), ReadSOC_DD( MAC_PHYBASE + 0xb4 ), ReadSOC_DD( MAC_PHYBASE + 0xb8 ), ReadSOC_DD(MAC_PHYBASE + 0xbc ) );
++ PRINT(OUT_OBJ "[MAC] C0|%08lx %08lx %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0xc0), ReadSOC_DD( MAC_PHYBASE + 0xc4 ), ReadSOC_DD( MAC_PHYBASE + 0xc8 ));
++
++#ifdef SLT_UBOOT
++#else
++ fprintf(fp, "Time: %s", ctime(&timestart));
++ time(&timecur);
++ fprintf(fp, "----> %s", ctime(&timecur));
++#endif
++} // End void FPri_RegValue (BYTE *fp)
++
++//------------------------------------------------------------
++void FPri_End (BYTE option) {
++
++ FILE_VAR
++
++ GET_OBJ( option )
++
++ if ( !RxDataEnable ) {
++ }
++ else if ( Err_Flag ) {
++ PRINT(OUT_OBJ " \n----> fail !!!\n");
++ } else {
++ PRINT(OUT_OBJ " \n----> All Pass !!!\n");
++ }
++
++ if ( ModeSwitch == MODE_DEDICATED ) {
++ if (PHY_ADR_arg != PHY_ADR)
++ PRINT(OUT_OBJ "\n[Warning] PHY Address change from %d to %d !!!\n", PHY_ADR_arg, PHY_ADR);
++ }
++
++ if ( AST1010 ) {
++ Dat_ULONG = (SCU_ach_old >> 12) & 0xf;
++ if (Dat_ULONG) {
++ PRINT(OUT_OBJ "\n[Warning] SCUAC[15:12] == 0x%02lx is not the suggestion value 0.\n", Dat_ULONG);
++ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
++ }
++
++ SCU_48h_default = SCU_48h_AST1010 & 0x01000f00;
++ if ((SCU_48h_old != SCU_48h_default)) {
++ PRINT(OUT_OBJ "\n[Warning] SCU48 == 0x%08lx is not the suggestion value 0x%08lx.\n", SCU_48h_old, SCU_48h_default);
++ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
++ }
++ }
++ else if ( AST2300 ) {
++ if ( AST2400 ) {
++ Dat_ULONG = (SCU_90h_old >> 8) & 0xf;
++ if (Dat_ULONG) {
++ PRINT(OUT_OBJ "\n[Warning] SCU90[11: 8] == 0x%02lx is not the suggestion value 0.\n", Dat_ULONG);
++ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
++ }
++ }
++ else {
++ Dat_ULONG = (SCU_90h_old >> 8) & 0xff;
++ if (Dat_ULONG) {
++ PRINT(OUT_OBJ "\n[Warning] SCU90[15: 8] == 0x%02lx is not the suggestion value 0.\n", Dat_ULONG);
++ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
++ }
++ }
++
++ if (Enable_MAC34) SCU_48h_default = SCU_48h_AST2300;
++ else SCU_48h_default = SCU_48h_AST2300 & 0x0300ffff;
++
++ if ((SCU_48h_old != SCU_48h_default)) {
++ PRINT(OUT_OBJ "\n[Warning] SCU48 == 0x%08lx is not the suggestion value 0x%08lx.\n", SCU_48h_old, SCU_48h_default);
++ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
++ }
++ } // End if ( AST1010 )
++
++ if ( ModeSwitch == MODE_NSCI ) {
++ PRINT(OUT_OBJ "\n[Arg] %d %d %d %d %d %ld (%s)\n", GRun_Mode, PackageTolNum, ChannelTolNum, TestMode, IOTimingBund, (ARPNumCnt| (ULONG)PrintNCSIEn), ASTChipName);
++
++ switch (NCSI_Cap_SLT.PCI_DID_VID) {
++ case PCI_DID_VID_Intel_82574L : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82574L \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82575_10d6 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82575 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82575_10a7 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82575 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82575_10a9 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82575 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82576_10c9 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82576_10e6 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82576_10e7 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82576_10e8 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82576_1518 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82576_1526 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82576_150a : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82576_150d : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82599_10fb : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82599 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_82599_1557 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82599 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_I350_1521 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel I350 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_I350_1523 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel I350 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_I210 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel I210 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Intel_X540 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel X540 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Broadcom_BCM5718 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Broadcom BCM5718 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Broadcom_BCM5720 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Broadcom BCM5720 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Broadcom_BCM5725 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Broadcom BCM5725 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++// case PCI_DID_VID_Broadcom_BCM57810 : PRINT( OUT_OBJ "[NC]%08x %08x: Broadcom BCM57810 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case PCI_DID_VID_Mellanox_ConnectX_3 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Mellanox ConnectX-3\n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ default :
++ switch (NCSI_Cap_SLT.ManufacturerID) {
++ case ManufacturerID_Intel : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case ManufacturerID_Broadcom : PRINT( OUT_OBJ "[NC]%08lx %08lx: Broadcom\n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ case ManufacturerID_Mellanox : PRINT( OUT_OBJ "[NC]%08lx %08lx: Mellanox\n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
++ default : PRINT(OUT_OBJ "[NC]%08lx %08lx \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID); break;
++ } // End switch (NCSI_Cap_SLT.ManufacturerID)
++ } // End switch (NCSI_Cap_SLT.PCI_DID_VID)
++ }
++ else {
++ if (LOOP_INFINI) PRINT(OUT_OBJ "\n[Arg] %d %d %d # %d %d %d %lx (%s)[%d %d %d]\n" , GRun_Mode, GSpeed, GCtrl, TestMode, PHY_ADR_arg, IOTimingBund, UserDVal, ASTChipName, Loop_rl[0], Loop_rl[1], Loop_rl[2]);
++ else PRINT(OUT_OBJ "\n[Arg] %d %d %d %ld %d %d %d %lx (%s)[%d %d %d]\n", GRun_Mode, GSpeed, GCtrl, LOOP_MAX_arg, TestMode, PHY_ADR_arg, IOTimingBund, UserDVal, ASTChipName, Loop_rl[0], Loop_rl[1], Loop_rl[2]);
++
++ PRINT(OUT_OBJ "[PHY] Adr:%d ID2:%04lx ID3:%04lx (%s)\n", PHY_ADR, PHY_ID2, PHY_ID3, PHYName);
++ } // End if ( ModeSwitch == MODE_NSCI )
++
++#ifdef SUPPORT_PHY_LAN9303
++ PRINT(OUT_OBJ "[Ver II] %s (for LAN9303 with I2C%d)\n", version_name, LAN9303_I2C_BUSNUM);
++#else
++ PRINT(OUT_OBJ "[Ver II] %s\n", version_name);
++#endif
++} // End void FPri_End (BYTE option)
++
++//------------------------------------------------------------
++void FPri_ErrFlag (BYTE option) {
++
++ FILE_VAR
++
++ GET_OBJ( option )
++
++ if (Err_Flag && Err_Flag_PrintEn) {
++ PRINT(OUT_OBJ "\n\n");
++//fprintf(fp, "Err_Flag: %x\n\n", Err_Flag);
++
++ if ( Err_Flag & Err_PHY_Type ) PRINT( OUT_OBJ "[Err] Unidentifiable PHY \n" );
++ if ( Err_Flag & Err_MALLOC_FrmSize ) PRINT( OUT_OBJ "[Err] Malloc fail at frame size buffer \n" );
++ if ( Err_Flag & Err_MALLOC_LastWP ) PRINT( OUT_OBJ "[Err] Malloc fail at last WP buffer \n" );
++ if ( Err_Flag & Err_Check_Buf_Data ) PRINT( OUT_OBJ "[Err] Received data mismatch \n" );
++ if ( Err_Flag & Err_NCSI_Check_TxOwnTimeOut ) PRINT( OUT_OBJ "[Err] Time out of checking Tx owner bit in NCSI packet \n" );
++ if ( Err_Flag & Err_NCSI_Check_RxOwnTimeOut ) PRINT( OUT_OBJ "[Err] Time out of checking Rx owner bit in NCSI packet \n" );
++ if ( Err_Flag & Err_NCSI_Check_ARPOwnTimeOut) PRINT( OUT_OBJ "[Err] Time out of checking ARP owner bit in NCSI packet \n" );
++ if ( Err_Flag & Err_NCSI_No_PHY ) PRINT( OUT_OBJ "[Err] Can not find NCSI PHY \n" );
++ if ( Err_Flag & Err_NCSI_Channel_Num ) PRINT( OUT_OBJ "[Err] NCSI Channel Number Mismatch \n" );
++ if ( Err_Flag & Err_NCSI_Package_Num ) PRINT( OUT_OBJ "[Err] NCSI Package Number Mismatch \n" );
++ if ( Err_Flag & Err_PHY_TimeOut ) PRINT( OUT_OBJ "[Err] Time out of read/write/reset PHY register \n" );
++ if ( Err_Flag & Err_RXBUF_UNAVA ) PRINT( OUT_OBJ "[Err] MAC00h[2]:Receiving buffer unavailable \n" );
++ if ( Err_Flag & Err_RPKT_LOST ) PRINT( OUT_OBJ "[Err] MAC00h[3]:Received packet lost due to RX FIFO full \n" );
++ if ( Err_Flag & Err_NPTXBUF_UNAVA ) PRINT( OUT_OBJ "[Err] MAC00h[6]:Normal priority transmit buffer unavailable \n" );
++ if ( Err_Flag & Err_TPKT_LOST ) PRINT( OUT_OBJ "[Err] MAC00h[7]:Packets transmitted to Ethernet lost \n" );
++ if ( Err_Flag & Err_DMABufNum ) PRINT( OUT_OBJ "[Err] DMA Buffer is not enough \n" );
++ if ( Err_Flag & Err_IOMargin ) PRINT( OUT_OBJ "[Err] IO timing margin is not enough \n" );
++
++ if ( Err_Flag & Err_MHCLK_Ratio ) {
++ if ( AST1010 ) {
++ PRINT(OUT_OBJ "[Err] Error setting of MAC AHB bus clock (SCU08[13:12]) \n");
++ Dat_ULONG = (SCU_08h_old >> 12) & 0x3;
++ PRINT(OUT_OBJ " SCU08[13:12] == 0x%01lx is not the suggestion value 0.\n", Dat_ULONG);
++ }
++ else {
++ PRINT(OUT_OBJ "[Err] Error setting of MAC AHB bus clock (SCU08[18:16]) \n");
++ Dat_ULONG = (SCU_08h_old >> 16) & 0x7;
++
++ if (MAC1_1GEn | MAC2_1GEn) {
++ PRINT(OUT_OBJ " SCU08[18:16] == 0x%01lx is not the suggestion value 2.\n", Dat_ULONG);
++ }
++ else {
++ PRINT(OUT_OBJ " SCU08[18:16] == 0x%01lx is not the suggestion value 4.\n", Dat_ULONG);
++ }
++ } // end if ( AST1010 )
++ } // End if ( Err_Flag & Err_MHCLK_Ratio )
++
++ if (Err_Flag & Err_IOMarginOUF ) {
++ PRINT(OUT_OBJ "[Err] IO timing testing range out of boundary\n");
++ if (Enable_RMII) {
++#ifdef Enable_Old_Style
++ PRINT(OUT_OBJ " (%d,%d): 1x%d [%d]x[%d:%d]\n", IOdly_out_reg_idx, IOdly_in_reg_idx, IOTimingBund, IOdly_out_reg_idx, IOdly_in_reg_idx - (IOTimingBund>>1), IOdly_in_reg_idx + (IOTimingBund>>1));
++#else
++ PRINT(OUT_OBJ " (%d,%d): %dx1 [%d:%d]x[%d]\n", IOdly_in_reg_idx, IOdly_out_reg_idx, IOTimingBund, IOdly_in_reg_idx - (IOTimingBund>>1), IOdly_in_reg_idx + (IOTimingBund>>1), IOdly_out_reg_idx);
++#endif
++ } else {
++#ifdef Enable_Old_Style
++ PRINT(OUT_OBJ " (%d,%d): %dx%d [%d:%d]x[%d:%d]\n", IOdly_out_reg_idx, IOdly_in_reg_idx, IOTimingBund, IOTimingBund, IOdly_out_reg_idx - (IOTimingBund>>1), IOdly_out_reg_idx + (IOTimingBund>>1), IOdly_in_reg_idx - (IOTimingBund>>1), IOdly_in_reg_idx + (IOTimingBund>>1));
++#else
++ PRINT(OUT_OBJ " (%d,%d): %dx%d [%d:%d]x[%d:%d]\n", IOdly_in_reg_idx, IOdly_out_reg_idx, IOTimingBund, IOTimingBund, IOdly_in_reg_idx - (IOTimingBund>>1), IOdly_in_reg_idx + (IOTimingBund>>1), IOdly_out_reg_idx - (IOTimingBund>>1), IOdly_out_reg_idx + (IOTimingBund>>1));
++#endif
++ }
++ } // End if (Err_Flag & Err_IOMarginOUF )
++
++ if (Err_Flag & Err_Check_Des ) {
++ PRINT(OUT_OBJ "[Err] Descriptor error\n");
++ if ( Check_Des_Val & Check_Des_TxOwnTimeOut ) PRINT( OUT_OBJ "[Des] Time out of checking Tx owner bit\n" );
++ if ( Check_Des_Val & Check_Des_RxOwnTimeOut ) PRINT( OUT_OBJ "[Des] Time out of checking Rx owner bit\n" );
++ if ( Check_Des_Val & Check_Des_RxErr ) PRINT( OUT_OBJ "[Des] Input signal RxErr \n" );
++ if ( Check_Des_Val & Check_Des_OddNibble ) PRINT( OUT_OBJ "[Des] Nibble bit happen \n" );
++ if ( Check_Des_Val & Check_Des_CRC ) PRINT( OUT_OBJ "[Des] CRC error of frame \n" );
++ if ( Check_Des_Val & Check_Des_RxFIFOFull ) PRINT( OUT_OBJ "[Des] Rx FIFO full \n" );
++ if ( Check_Des_Val & Check_Des_FrameLen ) PRINT( OUT_OBJ "[Des] Frame length mismatch \n" );
++ } // End if (Err_Flag & Err_Check_Des )
++
++ if (Err_Flag & Err_MACMode ) {
++ PRINT(OUT_OBJ "[Err] MAC interface mode mismatch\n");
++ if ( AST1010 ) {
++ }
++ else if (AST2300) {
++ switch (MAC_Mode) {
++ case 0 : PRINT( OUT_OBJ " SCU70h[7:6] == 0: [MAC#1] RMII [MAC#2] RMII \n" ); break;
++ case 1 : PRINT( OUT_OBJ " SCU70h[7:6] == 1: [MAC#1] RGMII [MAC#2] RMII \n" ); break;
++ case 2 : PRINT( OUT_OBJ " SCU70h[7:6] == 2: [MAC#1] RMII [MAC#2] RGMII\n" ); break;
++ case 3 : PRINT( OUT_OBJ " SCU70h[7:6] == 3: [MAC#1] RGMII [MAC#2] RGMII\n" ); break;
++ }
++ }
++ else {
++ switch (MAC_Mode) {
++ case 0 : PRINT( OUT_OBJ " SCU70h[8:6] == 000: [MAC#1] GMII \n" ); break;
++ case 1 : PRINT( OUT_OBJ " SCU70h[8:6] == 001: [MAC#1] MII [MAC#2] MII \n" ); break;
++ case 2 : PRINT( OUT_OBJ " SCU70h[8:6] == 010: [MAC#1] RMII [MAC#2] MII \n" ); break;
++ case 3 : PRINT( OUT_OBJ " SCU70h[8:6] == 011: [MAC#1] MII \n" ); break;
++ case 4 : PRINT( OUT_OBJ " SCU70h[8:6] == 100: [MAC#1] RMII \n" ); break;
++ case 5 : PRINT( OUT_OBJ " SCU70h[8:6] == 101: Reserved \n" ); break;
++ case 6 : PRINT( OUT_OBJ " SCU70h[8:6] == 110: [MAC#1] RMII [MAC#2] RMII\n" ); break;
++ case 7 : PRINT( OUT_OBJ " SCU70h[8:6] == 111: Disable MAC \n" ); break;
++ }
++ } // End if ( AST1010 )
++ } // End if (Err_Flag & Err_MACMode )
++
++ if ( ModeSwitch == MODE_NSCI ) {
++ if (Err_Flag & Err_NCSI_LinkFail ) {
++ PRINT(OUT_OBJ "[Err] NCSI packet retry number over flows when find channel\n");
++
++ if (NCSI_LinkFail_Val & NCSI_LinkFail_Get_Version_ID ) PRINT(OUT_OBJ "[NCSI] Time out when Get Version ID \n");
++ if (NCSI_LinkFail_Val & NCSI_LinkFail_Get_Capabilities ) PRINT(OUT_OBJ "[NCSI] Time out when Get Capabilities \n");
++ if (NCSI_LinkFail_Val & NCSI_LinkFail_Select_Active_Package ) PRINT(OUT_OBJ "[NCSI] Time out when Select Active Package \n");
++ if (NCSI_LinkFail_Val & NCSI_LinkFail_Enable_Set_MAC_Address ) PRINT(OUT_OBJ "[NCSI] Time out when Enable Set MAC Address \n");
++ if (NCSI_LinkFail_Val & NCSI_LinkFail_Enable_Broadcast_Filter) PRINT(OUT_OBJ "[NCSI] Time out when Enable Broadcast Filter\n");
++ if (NCSI_LinkFail_Val & NCSI_LinkFail_Enable_Network_TX ) PRINT(OUT_OBJ "[NCSI] Time out when Enable Network TX \n");
++ if (NCSI_LinkFail_Val & NCSI_LinkFail_Enable_Channel ) PRINT(OUT_OBJ "[NCSI] Time out when Enable Channel \n");
++ if (NCSI_LinkFail_Val & NCSI_LinkFail_Disable_Network_TX ) PRINT(OUT_OBJ "[NCSI] Time out when Disable Network TX \n");
++ if (NCSI_LinkFail_Val & NCSI_LinkFail_Disable_Channel ) PRINT(OUT_OBJ "[NCSI] Time out when Disable Channel \n");
++ }
++
++ if (Err_Flag & Err_NCSI_Channel_Num ) PRINT(OUT_OBJ "[NCSI] Channel number expected: %d, real: %d\n", ChannelTolNum, number_chl);
++ if (Err_Flag & Err_NCSI_Package_Num ) PRINT(OUT_OBJ "[NCSI] Peckage number expected: %d, real: %d\n", PackageTolNum, number_pak);
++ } // End if ( ModeSwitch == MODE_NSCI )
++ } // End if (Err_Flag && Err_Flag_PrintEn)
++} // End void FPri_ErrFlag (BYTE option)
++
++//------------------------------------------------------------
++void Finish_Close (void) {
++
++ if (SCU_oldvld)
++ recov_scu();
++
++#ifdef SLT_DOS
++ if (fp_io && IOTiming)
++ fclose(fp_io);
++
++ if (fp_log)
++ fclose(fp_log);
++#endif
++} // End void Finish_Close (void)
++
++//------------------------------------------------------------
++char Finish_Check (int value) {
++ ULONG temp;
++ CHAR i = 0;
++
++#ifdef Disable_VGA
++ if (VGAModeVld) {
++ outp(0x3d4, 0x17);
++ outp(0x3d5, VGAMode);
++ }
++#endif
++ #ifdef DbgPrn_FuncHeader
++ printf ("Finish_Check\n");
++ Debug_delay();
++ #endif
++
++ if ( FRAME_LEN )
++ free(FRAME_LEN);
++
++ if ( wp_lst )
++ free(wp_lst );
++
++ Err_Flag = Err_Flag | value;
++
++ if ( DbgPrn_ErrFlg )
++ printf ("\nErr_Flag: [%08lx]\n", Err_Flag);
++
++ if ( !BurstEnable )
++ FPri_ErrFlag( FP_LOG );
++
++ if ( IOTiming )
++ FPri_ErrFlag( FP_IO );
++
++ FPri_ErrFlag( STD_OUT );
++
++ if ( !BurstEnable )
++ FPri_End( FP_LOG );
++
++ if ( IOTiming )
++ FPri_End( FP_IO );
++
++ FPri_End( STD_OUT );
++
++
++ if ( !BurstEnable ) FPri_RegValue( FP_LOG );
++ if ( IOTiming ) FPri_RegValue( FP_IO );
++
++ Finish_Close();
++
++ // 20140325
++ temp = ReadSOC_DD( 0x1e6e2040 );
++ if ( ModeSwitch == MODE_NSCI )
++ {
++ if ( SelectMAC == 0 )
++ i = 17;
++ else
++ i = 16;
++ }
++ else
++ {
++ if ( SelectMAC == 0 )
++ i = 19;
++ else
++ i = 18;
++ }
++ WriteSOC_DD( 0x1e6e2040, (temp | (1 << i)) );
++
++
++ if ( Err_Flag )
++ {
++ // Fail
++ return( 1 );
++ }
++ else
++ {
++ // Pass
++ return( 0 );
++ }
++} // End char Finish_Check (int value)
++
++//------------------------------------------------------------
++int FindErr (int value) {
++ Err_Flag = Err_Flag | value;
++
++ if ( DbgPrn_ErrFlg )
++ printf ("\nErr_Flag: [%08lx]\n", Err_Flag);
++
++ return(1);
++}
++
++//------------------------------------------------------------
++int FindErr_Des (int value) {
++ Check_Des_Val = Check_Des_Val | value;
++ Err_Flag = Err_Flag | Err_Check_Des;
++ if ( DbgPrn_ErrFlg )
++ printf ("\nErr_Flag: [%08lx] Check_Des_Val: [%08lx]\n", Err_Flag, Check_Des_Val);
++
++ return(1);
++}
++
++//------------------------------------------------------------
++// Get and Check status of Interrupt
++//------------------------------------------------------------
++int check_int ( char *type ) {
++ #ifdef DbgPrn_FuncHeader
++ printf ("check_int : %d\n", Loop);
++ Debug_delay();
++ #endif
++
++ Dat_ULONG = ReadSOC_DD( H_MAC_BASE + 0x00 );//Interrupt Status
++#ifdef SLT_DOS
++#ifdef CheckRxbufUNAVA
++ if ( Dat_ULONG & 0x00000004 ) {
++ fprintf(fp_log, "[%sIntStatus] Receiving buffer unavailable : %08lx [loop:%d]\n", type, Dat_ULONG, Loop);
++ FindErr( Err_RXBUF_UNAVA );
++ }
++#endif
++
++#ifdef CheckRPktLost
++ if ( Dat_ULONG & 0x00000008 ) {
++ fprintf(fp_log, "[%sIntStatus] Received packet lost due to RX FIFO full : %08lx [loop:%d]\n", type, Dat_ULONG, Loop);
++ FindErr( Err_RPKT_LOST );
++ }
++#endif
++
++#ifdef CheckNPTxbufUNAVA
++ if ( Dat_ULONG & 0x00000040 ) {
++ fprintf(fp_log, "[%sIntStatus] Normal priority transmit buffer unavailable: %08lx [loop:%d]\n", type, Dat_ULONG, Loop);
++ FindErr( Err_NPTXBUF_UNAVA );
++ }
++#endif
++
++#ifdef CheckTPktLost
++ if ( Dat_ULONG & 0x00000080 ) {
++ fprintf(fp_log, "[%sIntStatus] Packets transmitted to Ethernet lost : %08lx [loop:%d]\n", type, Dat_ULONG, Loop);
++ FindErr( Err_TPKT_LOST );
++ }
++#endif
++#endif
++ if (Err_Flag)
++ return(1);
++ else
++ return(0);
++} // End int check_int (char *type)
++
++
++//------------------------------------------------------------
++// Buffer
++//------------------------------------------------------------
++void setup_framesize (void) {
++ int i;
++
++ #ifdef DbgPrn_FuncHeader
++ printf ("setup_framesize\n");
++ Debug_delay();
++ #endif
++
++ //------------------------------------------------------------
++ // Fill Frame Size out descriptor area
++ //------------------------------------------------------------
++ #ifdef SLT_UBOOT
++ if (0)
++ #else
++ if ( ENABLE_RAND_SIZE )
++ #endif
++ {
++ for (i = 0; i < DES_NUMBER; i++) {
++ if ( FRAME_Rand_Simple ) {
++ switch(rand() % 5) {
++ case 0 : FRAME_LEN[i] = 0x4e ; break;
++ case 1 : FRAME_LEN[i] = 0x4ba; break;
++ default: FRAME_LEN[i] = 0x5ea; break;
++ }
++ }
++ else {
++ FRAME_LEN_Cur = rand() % (MAX_FRAME_RAND_SIZE + 1);
++
++ if (FRAME_LEN_Cur < MIN_FRAME_RAND_SIZE)
++ FRAME_LEN_Cur = MIN_FRAME_RAND_SIZE;
++
++ FRAME_LEN[i] = FRAME_LEN_Cur;
++ }
++#ifdef SLT_DOS
++ if (DbgPrn_FRAME_LEN)
++ fprintf(fp_log, "[setup_framesize] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", FRAME_LEN[i], i, Loop);
++#endif
++ }
++ }
++ else {
++ for (i = 0; i < DES_NUMBER; i++) {
++ #ifdef SelectSimpleLength
++ if (i % FRAME_SELH_PERD)
++ FRAME_LEN[i] = FRAME_LENH;
++ else
++ FRAME_LEN[i] = FRAME_LENL;
++ #else
++ if ( BurstEnable ) {
++ if (IEEETesting) {
++ FRAME_LEN[i] = 1514;
++ }
++ else {
++ #ifdef ENABLE_ARP_2_WOL
++ FRAME_LEN[i] = 164;
++ #else
++ FRAME_LEN[i] = 60;
++ #endif
++ }
++ }
++ else {
++ #ifdef SelectLengthInc
++// FRAME_LEN[i] = (i%1455)+60;
++ FRAME_LEN[i] = 1514-( i % 1455 );
++ #else
++ if (i % FRAME_SELH_PERD)
++ FRAME_LEN[i] = FRAME_LENH;
++ else
++ FRAME_LEN[i] = FRAME_LENL;
++ #endif
++ } // End if (BurstEnable)
++ #endif
++/*
++ switch(i % 20) {
++ case 0 : FRAME_LEN[i] = FRAME_LENH; break;
++ case 1 : FRAME_LEN[i] = FRAME_LENH; break;
++ case 2 : FRAME_LEN[i] = FRAME_LENH; break;
++ default: FRAME_LEN[i] = FRAME_LENL; break;
++ }
++*/
++#ifdef SLT_DOS
++ if (DbgPrn_FRAME_LEN)
++ fprintf(fp_log, "[setup_framesize] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", FRAME_LEN[i], i, Loop);
++#endif
++ } // End for (i = 0; i < DES_NUMBER; i++)
++ } // End if ( ENABLE_RAND_SIZE )
++
++ // Calculate average of frame size
++ Avg_frame_len = 0;
++
++ for ( i = 0; i < DES_NUMBER; i++ ) {
++ Avg_frame_len += FRAME_LEN[i];
++ }
++
++ Avg_frame_len = Avg_frame_len / (double)DES_NUMBER;
++
++ //------------------------------------------------------------
++ // Write Plane
++ //------------------------------------------------------------
++ switch( ZeroCopy_OFFSET & 0x3 ) {
++ case 0: wp_fir = 0xffffffff; break;
++ case 1: wp_fir = 0xffffff00; break;
++ case 2: wp_fir = 0xffff0000; break;
++ case 3: wp_fir = 0xff000000; break;
++ }
++
++ for ( i = 0; i < DES_NUMBER; i++ ) {
++ switch( ( ZeroCopy_OFFSET + FRAME_LEN[i] - 1 ) & 0x3 ) {
++ case 0: wp_lst[i] = 0x000000ff; break;
++ case 1: wp_lst[i] = 0x0000ffff; break;
++ case 2: wp_lst[i] = 0x00ffffff; break;
++ case 3: wp_lst[i] = 0xffffffff; break;
++ }
++ } // End for ( i = 0; i < DES_NUMBER; i++ )
++} // End void setup_framesize (void)
++
++//------------------------------------------------------------
++void setup_arp (void) {
++ int i;
++ for (i = 0; i < 16; i++ )
++ ARP_data[i] = ARP_org_data[i];
++
++ ARP_data[1] = 0x0000ffff | ( SA[0] << 16 )
++ | ( SA[1] << 24 );
++
++ ARP_data[2] = ( SA[2] )
++ | ( SA[3] << 8 )
++ | ( SA[4] << 16 )
++ | ( SA[5] << 24 );
++
++ ARP_data[5] = 0x00000100 | ( SA[0] << 16 )
++ | ( SA[1] << 24 );
++
++ ARP_data[6] = ( SA[2] )
++ | ( SA[3] << 8 )
++ | ( SA[4] << 16 )
++ | ( SA[5] << 24 );
++} // End void setup_arp (void)
++
++//------------------------------------------------------------
++void setup_buf (void) {
++ int i;
++ int j;
++ ULONG adr;
++ ULONG adr_srt;
++ ULONG adr_end;
++ ULONG len;
++ #ifdef SelectSimpleDA
++ int cnt;
++ ULONG Current_framelen;
++ #endif
++
++ #ifdef ENABLE_ARP_2_WOL
++ int DA[3];
++
++ DA[0] = ( ( SelectWOLDA_DatH >> 8 ) & 0x00ff ) |
++ ( ( SelectWOLDA_DatH << 8 ) & 0xff00 );
++
++ DA[1] = ( ( SelectWOLDA_DatL >> 24 ) & 0x00ff ) |
++ ( ( SelectWOLDA_DatL >> 8 ) & 0xff00 );
++
++ DA[2] = ( ( SelectWOLDA_DatL >> 8 ) & 0x00ff ) |
++ ( ( SelectWOLDA_DatL << 8 ) & 0xff00 );
++ #endif
++
++ #ifdef DbgPrn_FuncHeader
++ printf ("setup_buf : %d\n", Loop);
++ Debug_delay();
++ #endif
++
++ // It need be multiple of 4
++ adr_srt = GET_DMA_BASE_SETUP & 0xfffffffc;
++
++ for (j = 0; j < DES_NUMBER; j++) {
++ if ( DbgPrn_BufAdr )
++ printf("[loop:%4d][des:%4d][setup_buf ] %08lx\n", Loop, j, adr_srt);
++
++ if ( BurstEnable ) {
++ if ( IEEETesting ) {
++ #ifdef ENABLE_DASA
++ WriteSOC_DD( adr_srt , 0xffffffff );
++ WriteSOC_DD( adr_srt + 4, ARP_data[1] );
++ WriteSOC_DD( adr_srt + 8, ARP_data[2] );
++
++ for (adr = (adr_srt + 12); adr < (adr_srt + DMA_PakSize); adr += 4 )
++ #else
++ for (adr = adr_srt; adr < (adr_srt + DMA_PakSize); adr += 4 )
++ #endif
++ {
++ switch( TestMode ) {
++ case 1: gdata = 0xffffffff; break;
++ case 2: gdata = 0x55555555; break;
++ case 3: gdata = rand() | (rand() << 16); break;
++ case 5: gdata = UserDVal; break;
++ }
++ WriteSOC_DD(adr, gdata);
++ } // End for()
++ }
++ else {
++ for (i = 0; i < 16; i++) {
++ WriteSOC_DD( adr_srt + ( i << 2 ), ARP_data[i] );
++ }
++
++ #ifdef ENABLE_ARP_2_WOL
++ for (i = 16; i < 40; i += 3) {
++ WriteSOC_DD( adr_srt + ( i << 2 ), ( DA[1] << 16 ) | DA[0] );
++ WriteSOC_DD( adr_srt + ( i << 2 ) + 4, ( DA[0] << 16 ) | DA[2] );
++ WriteSOC_DD( adr_srt + ( i << 2 ) + 8, ( DA[2] << 16 ) | DA[1] );
++ }
++ #endif
++ } // End if ( IEEETesting )
++ }
++ else {
++ // --------------------------------------------
++ #ifdef SelectSimpleData
++ #ifdef SimpleData_Fix
++ switch( j % SimpleData_FixNum ) {
++ case 0 : gdata = SimpleData_FixVal00; break;
++ case 1 : gdata = SimpleData_FixVal01; break;
++ case 2 : gdata = SimpleData_FixVal02; break;
++ case 3 : gdata = SimpleData_FixVal03; break;
++ case 4 : gdata = SimpleData_FixVal04; break;
++ case 5 : gdata = SimpleData_FixVal05; break;
++ case 6 : gdata = SimpleData_FixVal06; break;
++ case 7 : gdata = SimpleData_FixVal07; break;
++ case 8 : gdata = SimpleData_FixVal08; break;
++ case 9 : gdata = SimpleData_FixVal09; break;
++ case 10 : gdata = SimpleData_FixVal10; break;
++ default : gdata = SimpleData_FixVal11; break;
++ }
++ #else
++ gdata = 0x11111111 * ((j + SEED_START) % 256);
++ #endif
++
++ adr_end = adr_srt + DMA_PakSize;
++ for ( adr = adr_srt; adr < adr_end; adr += 4 ) {
++ WriteSOC_DD( adr, gdata );
++ }
++ // --------------------------------------------
++ #elif SelectSimpleDA
++
++ gdata = DATA_SEED(j + SEED_START);
++ Current_framelen = FRAME_LEN[j];
++
++ if ( DbgPrn_FRAME_LEN )
++ fprintf(fp_log, "[setup_buf ] Current_framelen:%08lx[Des:%d][loop:%d]\n", Current_framelen, j, Loop);
++
++ cnt = 0;
++ len = ( ( ( Current_framelen - 14 ) & 0xff ) << 8) |
++ ( ( Current_framelen - 14 ) >> 8 );
++
++ adr_end = adr_srt + DMA_PakSize;
++ for ( adr = adr_srt; adr < adr_end; adr += 4 ) {
++ cnt++;
++ if (cnt == 1 ) WriteSOC_DD( adr, SelectSimpleDA_Dat0 );
++ else if (cnt == 2 ) WriteSOC_DD( adr, SelectSimpleDA_Dat1 );
++ else if (cnt == 3 ) WriteSOC_DD( adr, SelectSimpleDA_Dat2 );
++ else if (cnt == 4 ) WriteSOC_DD( adr, len | (len << 16) );
++ else
++ WriteSOC_DD( adr, gdata );
++
++ gdata += DATA_IncVal;
++ }
++ // --------------------------------------------
++ #else
++
++ gdata = DATA_SEED(j + SEED_START);
++ adr_end = adr_srt + DMA_PakSize;
++ for ( adr = adr_srt; adr < adr_end; adr += 4 ) {
++ WriteSOC_DD( adr, gdata );
++
++ gdata += DATA_IncVal;
++ }
++
++ #endif
++
++ } // End if ( BurstEnable )
++
++ adr_srt += DMA_PakSize;
++ } // End for (j = 0; j < DES_NUMBER; j++)
++} // End void setup_buf (void)
++
++//------------------------------------------------------------
++// Check data of one packet
++//------------------------------------------------------------
++char check_Data (ULONG desadr, LONG number) {
++ int index;
++ int cnt;
++ ULONG rdata;
++ ULONG wp_lst_cur;
++ ULONG adr_las;
++ ULONG adr;
++ ULONG adr_srt;
++ ULONG adr_end;
++ ULONG len;
++ #ifdef SelectSimpleDA
++ ULONG gdata_bak;
++ #endif
++
++ #ifdef DbgPrn_FuncHeader
++ printf ("check_Data : %d\n", Loop);
++ Debug_delay();
++ #endif
++ //printf("[Des:%d][loop:%d]Desadr:%08x\n", number, Loop, desadr);
++
++ wp_lst_cur = wp_lst[number];
++ FRAME_LEN_Cur = FRAME_LEN[number];
++#ifdef SLT_DOS
++ if ( DbgPrn_FRAME_LEN )
++ fprintf(fp_log, "[check_Data ] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", FRAME_LEN_Cur, number, Loop);
++#endif
++ adr_srt = ReadSOC_DD(desadr) & 0xfffffffc;
++ adr_end = adr_srt + PktByteSize;
++
++ #ifdef SelectSimpleData
++ #ifdef SimpleData_Fix
++ switch( number % SimpleData_FixNum ) {
++ case 0 : gdata = SimpleData_FixVal00; break;
++ case 1 : gdata = SimpleData_FixVal01; break;
++ case 2 : gdata = SimpleData_FixVal02; break;
++ case 3 : gdata = SimpleData_FixVal03; break;
++ case 4 : gdata = SimpleData_FixVal04; break;
++ case 5 : gdata = SimpleData_FixVal05; break;
++ case 6 : gdata = SimpleData_FixVal06; break;
++ case 7 : gdata = SimpleData_FixVal07; break;
++ case 8 : gdata = SimpleData_FixVal08; break;
++ case 9 : gdata = SimpleData_FixVal09; break;
++ case 10 : gdata = SimpleData_FixVal10; break;
++ default : gdata = SimpleData_FixVal11; break;
++ }
++ #else
++ gdata = 0x11111111 * ((number + SEED_START) % 256);
++ #endif
++ #else
++ gdata = DATA_SEED(number + SEED_START);
++ #endif
++
++ wp = wp_fir;
++ adr_las = adr_end - 4;
++
++ cnt = 0;
++ len = (((FRAME_LEN_Cur-14) & 0xff) << 8) | ((FRAME_LEN_Cur-14) >> 8);
++#ifdef SLT_DOS
++ if (DbgPrn_Bufdat)
++ fprintf(fp_log, " Inf:%08lx ~ %08lx(%08lx) %08lx [Des:%d][loop:%d]\n", adr_srt, adr_end, adr_las, gdata, number, Loop);
++#endif
++ for (adr = adr_srt; adr < adr_end; adr+=4) {
++
++ #ifdef SelectSimpleDA
++ cnt++;
++ if ( cnt == 1 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat0; }
++ else if ( cnt == 2 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat1; }
++ else if ( cnt == 3 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat2; }
++ else if ( cnt == 4 ) { gdata_bak = gdata; gdata = len | (len << 16); }
++ #endif
++ rdata = ReadSOC_DD(adr);
++ if (adr == adr_las)
++ wp = wp & wp_lst_cur;
++
++ if ( (rdata & wp) != (gdata & wp) ) {
++#ifdef SLT_DOS
++ fprintf(fp_log, "\nError: Adr:%08lx[%3d] (%08lx) (%08lx:%08lx) [Des:%d][loop:%d]\n", adr, (adr - adr_srt) / 4, rdata, gdata, wp, number, Loop);
++#endif
++ for (index = 0; index < 6; index++) {
++ rdata = ReadSOC_DD(adr);
++#ifdef SLT_DOS
++ fprintf(fp_log, "Rep : Adr:%08lx (%08lx) (%08lx:%08lx) [Des:%d][loop:%d]\n", adr, rdata, gdata, wp, number, Loop);
++#endif
++ }
++
++ if ( DbgPrn_DumpMACCnt )
++ dump_mac_ROreg();
++
++ return( FindErr( Err_Check_Buf_Data ) );
++ } // End if ( (rdata & wp) != (gdata & wp) )
++#ifdef SLT_DOS
++ if ( DbgPrn_BufdatDetail )
++ fprintf(fp_log, " Adr:%08lx[%3d] (%08lx) (%08lx:%08lx) [Des:%d][loop:%d]\n", adr, (adr - adr_srt) / 4, rdata, gdata, wp, number, Loop);
++#endif
++ #ifdef SelectSimpleDA
++ if ( cnt <= 4 )
++ gdata = gdata_bak;
++ #endif
++
++ #ifdef SelectSimpleData
++ #else
++ gdata += DATA_IncVal;
++ #endif
++
++ wp = 0xffffffff;
++ }
++ return(0);
++} // End char check_Data (ULONG desadr, LONG number)
++
++//------------------------------------------------------------
++char check_buf (int loopcnt) {
++ int count;
++ ULONG desadr;
++
++ #ifdef DbgPrn_FuncHeader
++ printf ("check_buf : %d\n", Loop);
++ Debug_delay();
++ #endif
++
++ for ( count = DES_NUMBER - 1; count >= 0; count-- ) {
++ desadr = H_RDES_BASE + ( 16 * count ) + 12;
++ //printf("%d:%08x\n", count, desadr);
++ if (check_Data(desadr, count)) {
++ check_int ("");
++
++ return(1);
++ }
++ }
++ if ( check_int ("") )
++ return(1);
++
++ return(0);
++} // End char check_buf (int loopcnt)
++
++//------------------------------------------------------------
++// Descriptor
++//------------------------------------------------------------
++void setup_txdes (ULONG desadr, ULONG bufbase) {
++ ULONG bufadr;
++ ULONG desval;
++ int count;
++
++ #ifdef DbgPrn_FuncHeader
++ printf ("setup_txdes: %d\n", Loop);
++ Debug_delay();
++ #endif
++
++ bufadr = bufbase + ZeroCopy_OFFSET;
++
++ if (TxDataEnable) {
++ for (count = 0; count < DES_NUMBER; count++) {
++ FRAME_LEN_Cur = FRAME_LEN[count];
++ desval = TDES_IniVal;
++ #ifdef SLT_DOS
++ if (DbgPrn_FRAME_LEN)
++ fprintf(fp_log, "[setup_txdes ] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", FRAME_LEN_Cur, count, Loop);
++ #endif
++ if (DbgPrn_BufAdr)
++ printf("[loop:%4d][des:%4d][setup_txdes] %08lx\n", Loop, count, bufadr);
++
++ WriteSOC_DD( desadr + 0x04, 0 );
++ WriteSOC_DD( desadr + 0x08, 0 );
++ WriteSOC_DD( desadr + 0x0C, (bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
++ if ( count == ( DES_NUMBER - 1 ) )
++ WriteSOC_DD( desadr , desval | EOR_IniVal);
++ else
++ WriteSOC_DD( desadr , desval );
++
++ bufadr += DMA_PakSize;
++ desadr += 16;
++ }
++ }
++ else {
++ WriteSOC_DD( desadr , 0);
++ }
++} // End void setup_txdes (ULONG desadr, ULONG bufbase)
++
++//------------------------------------------------------------
++void setup_rxdes (ULONG desadr, ULONG bufbase) {
++ ULONG bufadr;
++ ULONG desval;
++ int count;
++
++ #ifdef DbgPrn_FuncHeader
++ printf ("setup_rxdes: %d\n", Loop);
++ Debug_delay();
++ #endif
++
++ bufadr = bufbase+ZeroCopy_OFFSET;
++ desval = RDES_IniVal;
++
++ if ( RxDataEnable ) {
++ for (count = 0; count < DES_NUMBER; count++) {
++ if (DbgPrn_BufAdr)
++ printf("[loop:%4d][des:%4d][setup_rxdes] %08lx\n", Loop, count, bufadr);
++ WriteSOC_DD( desadr + 0x04, 0 );
++ WriteSOC_DD( desadr + 0x08, 0 );
++ WriteSOC_DD( desadr + 0x0C, ( bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
++ if ( count == ( DES_NUMBER - 1 ) )
++ WriteSOC_DD( desadr , desval | EOR_IniVal );
++ else
++ WriteSOC_DD( desadr , desval );
++
++ desadr += 16;
++ bufadr += DMA_PakSize;
++ }
++ }
++ else {
++ WriteSOC_DD( desadr , 0x80000000 );
++ } // End if ( RxDataEnable )
++} // End void setup_rxdes (ULONG desadr, ULONG bufbase)
++
++//------------------------------------------------------------
++// First setting TX and RX information
++//------------------------------------------------------------
++void setup_des (ULONG bufnum) {
++
++ if ( DbgPrn_BufAdr ) {
++ printf ("setup_rxdes: %ld\n", bufnum);
++ Debug_delay();
++ }
++
++ setup_txdes( H_TDES_BASE, GET_DMA_BASE_SETUP );
++ setup_rxdes( H_RDES_BASE, GET_DMA_BASE(0) );
++
++} // End void setup_des (ULONG bufnum)
++
++//------------------------------------------------------------
++// Move buffer point of TX and RX descriptor to next DMA buffer
++//------------------------------------------------------------
++void setup_des_loop (ULONG bufnum) {
++ int count;
++ ULONG H_rx_desadr;
++ ULONG H_tx_desadr;
++ ULONG H_tx_bufadr;
++ ULONG H_rx_bufadr;
++
++ if ( DbgPrn_BufAdr ) {
++ printf ("setup_rxdes_loop: %ld\n", bufnum);
++ Debug_delay();
++ }
++
++ if (RxDataEnable) {
++ H_rx_bufadr = GET_DMA_BASE( bufnum + 1 ) + ZeroCopy_OFFSET;
++ H_rx_desadr = H_RDES_BASE;
++//printf (" =====>setup_rxdes_loop: %ld [%lX]\n", bufnum, H_rx_bufadr);
++ for (count = 0; count < DES_NUMBER; count++) {
++ WriteSOC_DD(H_rx_desadr + 0x0C, (H_rx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
++
++ if (count == (DES_NUMBER - 1)) {
++ WriteSOC_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal );
++ }
++ else {
++ WriteSOC_DD( H_rx_desadr, RDES_IniVal );
++ }
++ H_rx_bufadr += DMA_PakSize;
++ H_rx_desadr += 16;
++ }
++ }
++
++ if (TxDataEnable) {
++ if (RxDataEnable) {
++ H_tx_bufadr = GET_DMA_BASE( bufnum ) + ZeroCopy_OFFSET;
++ }
++ else {
++ H_tx_bufadr = GET_DMA_BASE( 0 ) + ZeroCopy_OFFSET;
++ }
++ H_tx_desadr = H_TDES_BASE;
++//printf (" =====>setup_Txdes_loop: %ld [%lX]\n", bufnum, H_tx_bufadr);
++ for (count = 0; count < DES_NUMBER; count++) {
++ FRAME_LEN_Cur = FRAME_LEN[count];
++ WriteSOC_DD( H_tx_desadr + 0x0C, ( H_tx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
++ if (count == (DES_NUMBER - 1)) {
++ WriteSOC_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal );
++ }
++ else {
++ WriteSOC_DD( H_tx_desadr, TDES_IniVal );
++ }
++ H_tx_bufadr += DMA_PakSize;
++ H_tx_desadr += 16;
++ }
++ }
++
++ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 ); // Tx Poll
++ WriteSOC_DD( H_MAC_BASE + 0x1c, 0x00000000 ); // Rx Poll
++} // End void setup_des_loop (ULONG bufnum)
++
++//------------------------------------------------------------
++char check_des_header_Tx (char *type, ULONG adr, LONG desnum) {
++ int timeout = 0;
++ ULONG dat;
++
++ dat = ReadSOC_DD(adr);
++
++ while ( HWOwnTx(dat) ) {
++ // we will run again, if transfer has not been completed.
++ if ( RxDataEnable && (++timeout > TIME_OUT_Des) ) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[%sTxDesOwn] Address %08lx = %08lx [Des:%d][loop:%d]\n", type, adr, dat, desnum, Loop);
++ #endif
++ return(FindErr_Des(Check_Des_TxOwnTimeOut));
++ }
++ WriteSOC_DD(H_MAC_BASE + 0x18, 0x00000000);//Tx Poll
++ WriteSOC_DD(H_MAC_BASE + 0x1c, 0x00000000);//Rx Poll
++
++ #ifdef Delay_ChkTxOwn
++ delay(Delay_ChkTxOwn);
++ #endif
++ dat = ReadSOC_DD(adr);
++ }
++
++ return(0);
++} // End char check_des_header_Tx (char *type, ULONG adr, LONG desnum)
++
++//------------------------------------------------------------
++char check_des_header_Rx (char *type, ULONG adr, LONG desnum) {
++ #ifdef CheckRxOwn
++ int timeout = 0;
++ ULONG dat;
++
++ dat = ReadSOC_DD(adr);
++
++ while ( HWOwnRx( dat ) ) {
++ // we will run again, if transfer has not been completed.
++ if (TxDataEnable && (++timeout > TIME_OUT_Des)) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[%sRxDesOwn] Address %08lx = %08lx [Des:%d][loop:%d]\n", type, adr, dat, desnum, Loop);
++ #endif
++ return(FindErr_Des(Check_Des_RxOwnTimeOut));
++ }
++
++ WriteSOC_DD(H_MAC_BASE + 0x18, 0x00000000);//Tx Poll
++ WriteSOC_DD(H_MAC_BASE + 0x1c, 0x00000000);//Rx Poll
++
++ #ifdef Delay_ChkRxOwn
++ delay(Delay_ChkRxOwn);
++ #endif
++ dat = ReadSOC_DD(adr);
++ };
++
++ Dat_ULONG = ReadSOC_DD( adr + 12 );
++
++ #ifdef CheckRxLen
++ #ifdef SLT_DOS
++ if ( DbgPrn_FRAME_LEN )
++ fprintf(fp_log, "[%sRxDes ] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", type, (FRAME_LEN_Cur + 4), desnum, Loop);
++ #endif
++
++ if ((dat & 0x3fff) != (FRAME_LEN_Cur + 4)) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[%sRxDes] Error Frame Length %08lx:%08lx %08lx(%4d/%4d) [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, (dat & 0x3fff), (FRAME_LEN_Cur + 4), desnum, Loop);
++ #endif
++ FindErr_Des(Check_Des_FrameLen);
++ }
++ #endif // End CheckRxLen
++
++ #ifdef CheckRxErr
++ if (dat & 0x00040000) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[%sRxDes] Error RxErr %08lx:%08lx %08lx [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, desnum, Loop);
++ #endif
++ FindErr_Des(Check_Des_RxErr);
++ }
++ #endif // End CheckRxErr
++
++ #ifdef CheckOddNibble
++ if (dat & 0x00400000) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[%sRxDes] Odd Nibble %08lx:%08lx %08lx [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, desnum, Loop);
++ #endif
++ FindErr_Des(Check_Des_OddNibble);
++ }
++ #endif // End CheckOddNibble
++
++ #ifdef CheckCRC
++ if (dat & 0x00080000) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[%sRxDes] Error CRC %08lx:%08lx %08lx [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, desnum, Loop);
++ #endif
++ FindErr_Des(Check_Des_CRC);
++ }
++ #endif // End CheckCRC
++
++ #ifdef CheckRxFIFOFull
++ if (dat & 0x00800000) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[%sRxDes] Error Rx FIFO Full %08lx:%08lx %08lx [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, desnum, Loop);
++ #endif
++ FindErr_Des(Check_Des_RxFIFOFull);
++ }
++ #endif // End CheckRxFIFOFull
++
++ // if (check_int ("")) {return(1);}
++ #endif // End CheckRxOwn
++
++ if (Err_Flag)
++ return(1);
++ else
++ return(0);
++} // End char check_des_header_Rx (char *type, ULONG adr, LONG desnum)
++
++//------------------------------------------------------------
++char check_des (ULONG bufnum, int checkpoint) {
++ int desnum;
++ ULONG H_rx_desadr;
++ ULONG H_tx_desadr;
++ ULONG H_tx_bufadr;
++ ULONG H_rx_bufadr;
++
++ #ifdef Delay_DesGap
++ ULONG dly_cnt = 0;
++ ULONG dly_max = Delay_CntMaxIncVal;
++ #endif
++
++ #ifdef DbgPrn_FuncHeader
++ printf ("check_des : %d(%d)\n", Loop, checkpoint);
++ Debug_delay();
++ #endif
++
++ // Fire the engine to send and recvice
++ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 );//Tx Poll
++ WriteSOC_DD( H_MAC_BASE + 0x1c, 0x00000000 );//Rx Poll
++
++ #ifdef SelectSimpleDes
++ #else
++ if ( IEEETesting == 1 ) {
++ // IEEE test mode, there is the same data in every lan packet
++ H_tx_bufadr = GET_DMA_BASE_SETUP;
++ H_rx_bufadr = GET_DMA_BASE(0);
++ }
++ else {
++ H_rx_bufadr = GET_DMA_BASE( bufnum + 1 ) + ZeroCopy_OFFSET;
++
++ if (RxDataEnable) {
++ H_tx_bufadr = GET_DMA_BASE(bufnum ) + ZeroCopy_OFFSET;
++ }
++ else {
++ H_tx_bufadr = GET_DMA_BASE( 0 ) + ZeroCopy_OFFSET;
++ }
++ }
++ #endif
++
++ H_rx_desadr = H_RDES_BASE;
++ H_tx_desadr = H_TDES_BASE;
++
++ #ifdef Delay_DES
++ delay(Delay_DES);
++ #endif
++
++ for (desnum = 0; desnum < DES_NUMBER; desnum++) {
++ if ( DbgPrn_BufAdr )
++ printf( "[loop:%4d][des:%4d][check_des ] %08lx %08lx [%08lx] [%08lx]\n", Loop, desnum, ( H_tx_desadr ), ( H_rx_desadr ), ReadSOC_DD( H_tx_desadr + 12 ), ReadSOC_DD( H_rx_desadr + 12 ) );
++
++ //[Delay]--------------------
++ #ifdef Delay_DesGap
++ if ( dly_cnt++ > 3 ) {
++ switch ( rand() % 12 ) {
++ case 1 : dly_max = 00000; break;
++ case 3 : dly_max = 20000; break;
++ case 5 : dly_max = 40000; break;
++ case 7 : dly_max = 60000; break;
++ defaule: dly_max = 70000; break;
++ }
++
++ dly_max += ( rand() % 4 ) * 14321;
++
++ while (dly_cnt < dly_max) {
++ dly_cnt++;
++ }
++
++ dly_cnt = 0;
++ }
++ else {
++// timeout = 0;
++// while (timeout < 50000) {timeout++;};
++ }
++ #endif // End Delay_DesGap
++
++ //[Check Owner Bit]--------------------
++ FRAME_LEN_Cur = FRAME_LEN[desnum];
++#ifdef SLT_DOS
++ if ( DbgPrn_FRAME_LEN )
++ fprintf(fp_log, "[check_des ] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]%d\n", FRAME_LEN_Cur, desnum, Loop, checkpoint);
++#endif
++// if (BurstEnable) {
++// if (check_des_header_Tx("", H_tx_desadr, desnum)) {CheckDesFail_DesNum = desnum; return(1);}
++// } else {
++// if (check_des_header_Rx("", H_rx_desadr, desnum)) {CheckDesFail_DesNum = desnum; return(1);}
++// if (check_des_header_Tx("", H_tx_desadr, desnum)) {CheckDesFail_DesNum = desnum; return(1);}
++// }
++
++ // Check the description of Tx and Rx
++ if ( RxDataEnable && check_des_header_Rx("", H_rx_desadr, desnum) ) {
++ CheckDesFail_DesNum = desnum;
++
++ return(1);
++ }
++ if ( TxDataEnable && check_des_header_Tx("", H_tx_desadr, desnum) ) {
++ CheckDesFail_DesNum = desnum;
++
++ return(1);
++ }
++// else {
++// printf(" %d \r", desnum);
++// }
++
++ #ifdef SelectSimpleDes
++ #else
++ if ( !checkpoint ) {
++ // Setting buffer address to description of Tx and Rx on next stage
++
++// if (!BurstEnable) {
++// WriteSOC_DD( H_rx_desadr + 0x0C, (H_rx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) );
++// WriteSOC_DD( H_tx_desadr + 0x0C, (H_tx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) );
++// }
++//
++// if ( desnum == (DES_NUMBER - 1) ) {
++// WriteSOC_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal );
++// WriteSOC_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal );
++// }
++// else {
++// WriteSOC_DD( H_rx_desadr, RDES_IniVal );
++// WriteSOC_DD( H_tx_desadr, TDES_IniVal );
++// }
++// WriteSOC_DD( H_MAC_BASE+0x18, 0x00000000 ); //Tx Poll
++// WriteSOC_DD( H_MAC_BASE+0x1c, 0x00000000 ); //Rx Poll
++
++ if ( RxDataEnable ) {
++ WriteSOC_DD( H_rx_desadr + 0x0C, (H_rx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
++
++ if ( desnum == (DES_NUMBER - 1) ) {
++ WriteSOC_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal );
++ } else {
++ WriteSOC_DD( H_rx_desadr, RDES_IniVal );
++ }
++ }
++ if ( TxDataEnable ) {
++ WriteSOC_DD( H_tx_desadr + 0x0C, (H_tx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
++ if ( desnum == (DES_NUMBER - 1) ) {
++ WriteSOC_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal );
++ }
++ else {
++ WriteSOC_DD( H_tx_desadr, TDES_IniVal );
++ }
++ }
++ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 ); //Tx Poll
++ WriteSOC_DD( H_MAC_BASE + 0x1c, 0x00000000 ); //Rx Poll
++ }
++ H_rx_bufadr += DMA_PakSize;
++ H_tx_bufadr += DMA_PakSize;
++ #endif // End SelectSimpleDes
++
++ H_rx_desadr += 16;
++ H_tx_desadr += 16;
++ } // End for (desnum = 0; desnum < DES_NUMBER; desnum++)
++
++ return(0);
++} // End char check_des (ULONG bufnum, int checkpoint)
++//#endif
++
++//------------------------------------------------------------
++// Print
++//------------------------------------------------------------
++void PrintMode (void) {
++ if (Enable_MAC34) printf ("run_mode[dec] | 0->MAC1 1->MAC2 2->MAC3 3->MAC4\n");
++ else printf ("run_mode[dec] | 0->MAC1 1->MAC2\n");
++}
++
++//------------------------------------------------------------
++void PrintSpeed (void) {
++ printf ("speed[dec] | 0->1G 1->100M 2->10M 3->all speed (default:%3d)\n", DEF_SPEED);
++}
++
++//------------------------------------------------------------
++void PrintCtrl (void) {
++ printf ("ctrl[dec] | bit0~2: Reserved\n");
++ printf ("(default:%3d) | bit3 : 1->Enable PHY init 0->Disable PHY init\n", GCtrl);
++ printf (" | bit4 : 1->Enable PHY int-loop 0->Disable PHY int-loop\n");
++ printf (" | bit5 : 1->Ignore PHY ID 0->Check PHY ID\n");
++ if (AST2400) {
++ printf (" | bit6 : 1->Enable MAC int-loop 0->Disable MAC int-loop\n");
++ }
++}
++
++//------------------------------------------------------------
++void PrintLoop (void) {
++ printf ("loop_max[dec] | 1G : 20 will run 1 sec (default:%3d)\n", DEF_LOOP_MAX * 20);
++ printf (" | 100M: 2 will run 1 sec (default:%3d)\n", DEF_LOOP_MAX * 2);
++ printf (" | 10M : 1 will run 1 sec (default:%3d)\n", DEF_LOOP_MAX);
++}
++
++//------------------------------------------------------------
++void PrintTest (void) {
++ if ( ModeSwitch == MODE_NSCI ) {
++ printf ("test_mode[dec] | 0: NCSI configuration with Disable_Channel request\n");
++ printf ("(default:%3d) | 1: NCSI configuration without Disable_Channel request\n", DEF_TESTMODE);
++ }
++ else {
++ printf ("test_mode[dec] | 0: Tx/Rx frame checking\n");
++ printf ("(default:%3d) | 1: Tx output 0xff frame\n", DEF_TESTMODE);
++ printf (" | 2: Tx output 0x55 frame\n");
++ printf (" | 3: Tx output random frame\n");
++ printf (" | 4: Tx output ARP frame\n");
++ printf (" | 5: Tx output user defined value frame (default:0x%8x)\n", DEF_USER_DEF_PACKET_VAL);
++ } // End if ( ModeSwitch == MODE_NSCI )
++
++ if (AST2300) {
++ printf (" | 6: IO timing testing\n");
++ printf (" | 7: IO timing/strength testing\n");
++ }
++}
++
++//------------------------------------------------------------
++void PrintPHYAdr (void) {
++ printf ("phy_adr[dec] | 0~31: PHY Address (default:%d)\n", DEF_PHY_ADR);
++}
++
++//------------------------------------------------------------
++void PrintIOTimingBund (void) {
++ printf ("IO margin[dec] | 0/1/3/5 (default:%d)\n", DEF_IOTIMINGBUND);
++}
++
++//------------------------------------------------------------
++void PrintPakNUm (void) {
++ printf ("package_num[dec] | 1~ 8: Total Number of NCSI Package (default:%d)\n", DEF_PACKAGE2NUM);
++}
++
++//------------------------------------------------------------
++void PrintChlNUm (void) {
++ printf ("channel_num[dec] | 1~32: Total Number of NCSI Channel (default:%d)\n", DEF_CHANNEL2NUM);
++}
++
++//------------------------------------------------------------
++
++void Print_Header (BYTE option) {
++
++ FILE_VAR
++
++ GET_OBJ( option )
++
++ if (GSpeed_sel[0]) PRINT(OUT_OBJ " 1G ");
++ else if (GSpeed_sel[1]) PRINT(OUT_OBJ " 100M ");
++ else PRINT(OUT_OBJ " 10M ");
++
++ switch (TestMode) {
++ case 0 : PRINT(OUT_OBJ "Tx/Rx frame checking \n" ); break;
++ case 1 : PRINT(OUT_OBJ "Tx output 0xff frame \n" ); break;
++ case 2 : PRINT(OUT_OBJ "Tx output 0x55 frame \n" ); break;
++ case 3 : PRINT(OUT_OBJ "Tx output random frame \n" ); break;
++ case 4 : PRINT(OUT_OBJ "Tx output ARP frame \n" ); break;
++ case 5 : PRINT(OUT_OBJ "Tx output 0x%08lx frame \n", UserDVal); break;
++ case 6 : PRINT(OUT_OBJ "IO delay testing \n" ); break;
++ case 7 : PRINT(OUT_OBJ "IO delay testing(Strength) \n" ); break;
++ case 8 : PRINT(OUT_OBJ "Tx frame \n" ); break;
++ case 9 : PRINT(OUT_OBJ "Rx frame checking \n" ); break;
++ }
++}
++
++//------------------------------------------------------------
++void PrintIO_Header (BYTE option) {
++
++ FILE_VAR
++
++ GET_OBJ( option )
++
++ if ( IOStrength ) {
++ if (GSpeed_sel[0]) PRINT(OUT_OBJ "[Strength %ld][1G ]========================================\n", IOStr_i);
++ else if (GSpeed_sel[1]) PRINT(OUT_OBJ "[Strength %ld][100M]========================================\n", IOStr_i);
++ else PRINT(OUT_OBJ "[Strength %ld][10M ]========================================\n", IOStr_i);
++ } else {
++ if (GSpeed_sel[0]) PRINT(OUT_OBJ "[1G ]========================================\n");
++ else if (GSpeed_sel[1]) PRINT(OUT_OBJ "[100M]========================================\n");
++ else PRINT(OUT_OBJ "[10M ]========================================\n");
++ }
++
++#ifdef Enable_Old_Style
++ if (Enable_RMII) PRINT(OUT_OBJ "Tx:SCU48[ %2d]= ", IOdly_out_shf);
++ else PRINT(OUT_OBJ "Tx:SCU48[%2d:%2d]= ", IOdly_out_shf+3, IOdly_out_shf);
++
++ for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) {
++ IOdly_out = valary[IOdly_j];
++ PRINT(OUT_OBJ "%2x", IOdly_out);
++ }
++
++ PRINT(OUT_OBJ "\n ");
++ for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) {
++ if (IOdly_out_reg_idx == IOdly_j) PRINT(OUT_OBJ " |");
++ else PRINT(OUT_OBJ " ");
++ }
++#else
++ PRINT(OUT_OBJ "Rx:SCU48[%2d:%2d]= ", IOdly_in_shf+3, IOdly_in_shf);
++
++ for (IOdly_i = IOdly_in_str; IOdly_i <= IOdly_in_end; IOdly_i+=IOdly_incval) {
++ IOdly_in = valary[IOdly_i];
++ PRINT(OUT_OBJ "%2x", IOdly_in);
++ }
++
++ PRINT(OUT_OBJ "\n ");
++ for (IOdly_i = IOdly_in_str; IOdly_i <= IOdly_in_end; IOdly_i+=IOdly_incval) {
++ if (IOdly_in_reg_idx == IOdly_i) PRINT(OUT_OBJ " |");
++ else PRINT(OUT_OBJ " ");
++ }
++#endif
++
++ PRINT(OUT_OBJ "\n");
++} // End void PrintIO_Header (BYTE option)
++
++//------------------------------------------------------------
++void PrintIO_LineS (BYTE option) {
++
++ FILE_VAR
++
++ GET_OBJ( option )
++
++
++#ifdef Enable_Old_Style
++ if (IOdly_in_reg == IOdly_in) {
++ PRINT(OUT_OBJ "Rx:SCU48[%2d:%2d]=%01x:-", IOdly_in_shf+3, IOdly_in_shf, IOdly_in);
++ }
++ else {
++ PRINT(OUT_OBJ "Rx:SCU48[%2d:%2d]=%01x: ", IOdly_in_shf+3, IOdly_in_shf, IOdly_in);
++ }
++#else
++ if (Enable_RMII) {
++ if (IOdly_out_reg == IOdly_out) {
++ PRINT(OUT_OBJ "Tx:SCU48[ %2d]=%01x:-", IOdly_out_shf, IOdly_out);
++ }
++ else {
++ PRINT(OUT_OBJ "Tx:SCU48[ %2d]=%01x: ", IOdly_out_shf, IOdly_out);
++ }
++ } else {
++ if (IOdly_out_reg == IOdly_out) {
++ PRINT(OUT_OBJ "Tx:SCU48[%2d:%2d]=%01x:-", IOdly_out_shf+3, IOdly_out_shf, IOdly_out);
++ }
++ else {
++ PRINT(OUT_OBJ "Tx:SCU48[%2d:%2d]=%01x: ", IOdly_out_shf+3, IOdly_out_shf, IOdly_out);
++ }
++ }
++#endif
++} // void PrintIO_LineS (BYTE option)
++
++//------------------------------------------------------------
++void PrintIO_Line (BYTE option) {
++
++ FILE_VAR
++
++ GET_OBJ( option )
++
++ if ( ( IOdly_in_reg == IOdly_in ) && ( IOdly_out_reg == IOdly_out ) ) {
++ if (dlymap[IOdly_i][IOdly_j]) PRINT(OUT_OBJ " X");
++ else PRINT(OUT_OBJ " O");
++ }
++ else {
++ if (dlymap[IOdly_i][IOdly_j]) PRINT(OUT_OBJ " x");
++ else PRINT(OUT_OBJ " o");
++ }
++} // End void PrintIO_Line (BYTE option)
++
++//------------------------------------------------------------
++void PrintIO_Line_LOG (void) {
++#ifndef SLT_UBOOT
++#ifdef Enable_Old_Style
++ if (Enable_RMII) fprintf(fp_log, "\nTx:SCU48[ %2d]=%2x, ", IOdly_out_shf, IOdly_out);
++ else fprintf(fp_log, "\nTx:SCU48[%2d:%2d]=%2x, ", IOdly_out_shf+3, IOdly_out_shf, IOdly_out);
++
++ fprintf(fp_log, "Rx:SCU48[%2d:%2d]=%01x: ", IOdly_in_shf+3, IOdly_in_shf, IOdly_in);
++
++ if (dlymap[IOdly_i][IOdly_j]) fprintf(fp_log, " X\n");
++ else fprintf(fp_log, " O\n");
++#else
++ fprintf(fp_log, "\nRx:SCU48[%2d:%2d]=%2x, ", IOdly_in_shf+3, IOdly_in_shf, IOdly_in);
++
++ if (Enable_RMII) fprintf(fp_log, "Tx:SCU48[ %2d]=%01x: ", IOdly_out_shf, IOdly_out);
++ else fprintf(fp_log, "Tx:SCU48[%2d:%2d]=%01x: ", IOdly_out_shf+3, IOdly_out_shf, IOdly_out);
++
++ if (dlymap[IOdly_i][IOdly_j]) fprintf(fp_log, " X\n");
++ else fprintf(fp_log, " O\n");
++#endif
++#endif
++}
++
++//------------------------------------------------------------
++// main
++//------------------------------------------------------------
++void Calculate_LOOP_CheckNum (void) {
++
++#define ONE_MBYTE 1048576
++
++ #ifdef CheckDataEveryTime
++ LOOP_CheckNum = 1;
++ #else
++ if (IOTiming || IOTimingBund || (GSpeed == SET_1G_100M_10MBPS)) {
++ LOOP_CheckNum = LOOP_MAX;
++ }
++ else {
++ switch ( GSpeed ) {
++ case SET_1GBPS : CheckBuf_MBSize = MOVE_DATA_MB_SEC ; break; // 1G
++ case SET_100MBPS : CheckBuf_MBSize = (MOVE_DATA_MB_SEC >> 3); break; // 100M ~ 1G / 8
++ case SET_10MBPS : CheckBuf_MBSize = (MOVE_DATA_MB_SEC >> 6); break; // 10M ~ 1G / 64
++ }
++ LOOP_CheckNum = ( CheckBuf_MBSize / ( ((DES_NUMBER * DMA_PakSize) / ONE_MBYTE ) + 1) );
++ }
++ #endif
++}
++
++//------------------------------------------------------------
++void TestingSetup (void) {
++ #ifdef DbgPrn_FuncHeader
++ printf ("TestingSetup\n");
++ Debug_delay();
++ #endif
++
++ #ifdef SLT_UBOOT
++ #else
++ #ifdef Rand_Sed
++ srand((unsigned) Rand_Sed);
++ #else
++ srand((unsigned) timestart);
++ #endif
++ #endif
++
++ //[Disable VGA]--------------------
++ #ifdef Disable_VGA
++ if ( LOOP_INFINI & ~(BurstEnable || IOTiming) ) {
++ VGAModeVld = 1;
++ outp(0x3d4, 0x17);
++ VGAMode = inp(0x3d5);
++ outp(0x3d4, 0x17);
++ outp(0x3d5, 0);
++ }
++ #endif
++
++ //[Setup]--------------------
++ setup_framesize();
++ setup_buf();
++}
++
++//------------------------------------------------------------
++// Return 1 ==> fail
++// Return 0 ==> PASS
++//------------------------------------------------------------
++char TestingLoop (ULONG loop_checknum) {
++ char checkprd;
++ char looplast;
++ char checken;
++
++ #ifdef SLT_UBOOT
++ #else
++ clock_t timeold;
++ #endif
++
++ #ifdef DbgPrn_FuncHeader
++ printf ("TestingLoop: %d\n", Loop);
++ Debug_delay();
++ #endif
++
++ if ( DbgPrn_DumpMACCnt )
++ dump_mac_ROreg();
++
++ //[Setup]--------------------
++ Loop = 0;
++ checkprd = 0;
++ checken = 0;
++ looplast = 0;
++
++ setup_des( 0 );
++
++ #ifdef SLT_UBOOT
++ #else
++ timeold = clock();
++ #endif
++
++ while ( (Loop < LOOP_MAX) || LOOP_INFINI ) {
++ looplast = !LOOP_INFINI && (Loop == LOOP_MAX - 1);
++
++ #ifdef CheckRxBuf
++ if (!BurstEnable) {
++ checkprd = ((Loop % loop_checknum) == (loop_checknum - 1));
++ }
++ checken = looplast | checkprd;
++ #endif
++
++ if ( DataDelay & ( Loop == 0 ) ) {
++ printf ("Press any key to start...\n");
++ GET_CAHR();
++ }
++
++#ifdef DbgPrn_FuncHeader
++ if ( DbgPrn_BufAdr ) {
++ printf ("for start ======> %d/%d(%d) looplast:%d checkprd:%d checken:%d\n", Loop, LOOP_MAX, LOOP_INFINI, looplast, checkprd, checken);
++ Debug_delay();
++ }
++#endif
++
++ //[Check DES]--------------------
++ if ( check_des(Loop, checken) ) {
++ //descriptor error
++ #ifdef CheckRxBuf
++ DES_NUMBER = CheckDesFail_DesNum + 1;
++ if ( checkprd ) {
++ check_buf(loop_checknum);
++ }
++ else {
++ check_buf((LOOP_MAX % loop_checknum));
++ }
++ DES_NUMBER = DES_NUMBER_Org;
++ #endif
++
++ if (DbgPrn_DumpMACCnt)
++ dump_mac_ROreg();
++
++ return(1);
++ }
++
++ //[Check Buf]--------------------
++ if ( RxDataEnable && checken ) {
++ #ifdef SLT_UBOOT
++ #else
++ timeused = (clock() - timeold) / (double) CLK_TCK;
++ #endif
++
++ if ( checkprd ) {
++ #ifdef SLT_DOS
++ #else
++ #ifdef SLT_UBOOT
++ #else
++ printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)DES_NUMBER * Avg_frame_len * 8.0) / ((double)timeused * 1000000.0), timeused);
++ fprintf(fp_log, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)DES_NUMBER * Avg_frame_len * 8.0) / ((double)timeused * 1000000.0), timeused);
++ #endif
++ #endif
++
++ #ifdef CheckRxBuf
++ if ( check_buf( loop_checknum ) )
++ return(1);
++ #endif
++ }
++ else {
++ #ifdef SLT_DOS
++ #else
++ #ifdef SLT_UBOOT
++ #else
++ printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (LOOP_MAX % loop_checknum), ((double)(LOOP_MAX % loop_checknum) * (double)DES_NUMBER * Avg_frame_len * 8.0) / ((double)timeused * 1000000.0), timeused);
++ fprintf(fp_log, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (LOOP_MAX % loop_checknum), ((double)(LOOP_MAX % loop_checknum) * (double)DES_NUMBER * Avg_frame_len * 8.0) / ((double)timeused * 1000000.0), timeused);
++ #endif
++ #endif
++
++ #ifdef CheckRxBuf
++ if ( check_buf( ( LOOP_MAX % loop_checknum ) ) )
++ return(1);
++ #endif
++ } // End if ( checkprd )
++
++ #ifdef SelectSimpleDes
++ #else
++ if ( !looplast )
++ setup_des_loop( Loop );
++ #endif
++
++ #ifdef SLT_DOS
++ #else
++ #ifdef SLT_UBOOT
++ #else
++ timeold = clock();
++ #endif
++ #endif
++
++ } // End if ( RxDataEnable && checken )
++
++ #ifdef SelectSimpleDes
++ if ( !looplast )
++ setup_des_loop( Loop );
++ #endif
++
++ if ( LOOP_INFINI ) {
++ printf("===============> Loop: %d \r", Loop);
++ }
++ else if (TestMode == 0) {
++ if (!(DbgPrn_BufAdr || IOTimingBund))
++ printf(" %d \r", Loop);
++// switch (Loop % 4) {
++// case 0x00: printf("| %d \r", Loop); break;
++// case 0x01: printf("/ %d \r", Loop); break;
++// case 0x02: printf("- %d \r", Loop); break;
++// default : printf("\ %d \r", Loop); break;
++// }
++ }
++
++ if ( DbgPrn_BufAdr ) {
++ printf ("for end ======> %d/%d(%d)\n", Loop, LOOP_MAX, LOOP_INFINI);
++ Debug_delay();
++ }
++
++ Loop++;
++ } // End while ((Loop < LOOP_MAX) || LOOP_INFINI)
++
++ Loop_rl[GSpeed_idx] = Loop;
++
++ return(0);
++} // End char TestingLoop (ULONG loop_checknum)
++
++
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/Makefile b/arch/arm/cpu/arm926ejs/aspeed/Makefile
+new file mode 100644
+index 0000000..378745e
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/Makefile
+@@ -0,0 +1,53 @@
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(SOC).a
++
++COBJS = timer.o
++COBJS += reset.o
++COBJS += mactest.o
++COBJS += DRAM_SPI.o
++COBJS += IO.o
++COBJS += LIB.o
++COBJS += MAC.o
++COBJS += NCSI.o
++COBJS += PCI_SPI.o
++COBJS += PHY.o
++COBJS += SPIM.o
++COBJS += STDUBOOT.o
++COBJS += PLLTESTU.o
++COBJS += TRAPTEST.o
++COBJS += STRESS.o
++
++SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
++START := $(addprefix $(obj),$(START))
++
++all: $(obj).depend $(LIB)
++
++$(LIB): $(OBJS)
++ $(AR) $(ARFLAGS) $@ $(OBJS)
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/NCSI.H b/arch/arm/cpu/arm926ejs/aspeed/NCSI.H
+new file mode 100644
+index 0000000..a0e448b
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/NCSI.H
+@@ -0,0 +1,189 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef NCSI_H
++#define NCSI_H
++
++#include "TYPEDEF.H"
++
++//---------------------------------------------------------
++// Define
++//---------------------------------------------------------
++#define MAX_PACKAGE_NUM 8 // 1 ~ 8
++#define MAX_CHANNEL_NUM 4 // 1 ~ 32
++//#define Enable_NCSI_LOOP_INFINI //[off]
++
++//---------------------------------------------------------
++// Function
++//---------------------------------------------------------
++#define SENT_RETRY_COUNT 1
++#define NCSI_RxDESNum 50
++
++//#define NCSI_Skip_Phase1_DeSelectPackage
++//#define NCSI_Skip_DeSelectPackage
++//#define NCSI_Skip_DiSChannel
++//#define NCSI_EnableDelay_DeSelectPackage
++//#define NCSI_EnableDelay_GetLinkStatus
++//#define NCSI_EnableDelay_EachPackage
++//#define Print_Version_ID
++//#define Print_PackageName
++
++//---------------------------------------------------------
++// PCI DID/VID & Manufacturer ID
++//---------------------------------------------------------
++#define ManufacturerID_Intel 0x00000157 //343
++#define ManufacturerID_Broadcom 0x0000113d //4413
++#define ManufacturerID_Mellanox 0x000002c9 //713
++
++//PCI VID: [163c]intel
++//PCI VID: [8086]Intel Corporation
++//PCI VID: [8087]Intel
++//PCI VID: [14e4]Broadcom Corporation
++//PCI VID: [15b3]Mellanox
++#define PCI_DID_VID_Intel_82574L 0x10d38086 // IntelR 82574L Gigabit Ethernet Controller
++#define PCI_DID_VID_Intel_82575_10d6 0x10d68086 // 82566 DM-2-gigabyte
++#define PCI_DID_VID_Intel_82575_10a7 0x10a78086 // 82575EB Gigabit Network Connection
++#define PCI_DID_VID_Intel_82575_10a9 0x10a98086 // 82575EB Gigabit Network Connection
++#define PCI_DID_VID_Intel_82576_10c9 0x10c98086 //*82576 Gigabit ET Dual Port Server Adapter
++#define PCI_DID_VID_Intel_82576_10e6 0x10e68086 // 82576 Gigabit Network Connection
++#define PCI_DID_VID_Intel_82576_10e7 0x10e78086 // 82576 Gigabit Network Connection
++#define PCI_DID_VID_Intel_82576_10e8 0x10e88086 // E64750-xxx Intel Gigabit ET Quad Port Server Adapter
++#define PCI_DID_VID_Intel_82576_1518 0x15188086 // 82576NS SerDes Gigabit Network Connectio
++#define PCI_DID_VID_Intel_82576_1526 0x15268086 // Intel Gigabit ET2 Quad Port Server Adapter
++#define PCI_DID_VID_Intel_82576_150a 0x150a8086 // 82576NS Gigabit Ethernet Controller
++#define PCI_DID_VID_Intel_82576_150d 0x150d8086 // 82576 Gigabit Backplane Connection
++#define PCI_DID_VID_Intel_82599_10fb 0x10fb8086 // 10 Gb Ethernet controller
++#define PCI_DID_VID_Intel_82599_1557 0x15578086 //
++#define PCI_DID_VID_Intel_I350_1521 0x15218086 //
++#define PCI_DID_VID_Intel_I350_1523 0x15238086 //
++#define PCI_DID_VID_Intel_I210 0x15338086 //
++#define PCI_DID_VID_Intel_X540 0x15288086 //
++#define PCI_DID_VID_Broadcom_BCM5718 0x165614e4 //
++#define PCI_DID_VID_Broadcom_BCM5720 0x165f14e4 //
++#define PCI_DID_VID_Broadcom_BCM5725 0x164314e4 //
++#define PCI_DID_VID_Mellanox_ConnectX_3 0x100315b3 //*
++
++//---------------------------------------------------------
++// Delay (ms)
++//---------------------------------------------------------
++#define Delay_EachPackage 1000
++#define Delay_DeSelectPackage 50
++#define Delay_GetLinkStatus 50
++
++//---------------------------------------------------------
++// NCSI Parameter
++//---------------------------------------------------------
++//Command and Response Type
++#define CLEAR_INITIAL_STATE 0x00 //M
++#define SELECT_PACKAGE 0x01 //M
++#define DESELECT_PACKAGE 0x02 //M
++#define ENABLE_CHANNEL 0x03 //M
++#define DISABLE_CHANNEL 0x04 //M
++#define RESET_CHANNEL 0x05 //M
++#define ENABLE_CHANNEL_NETWORK_TX 0x06 //M
++#define DISABLE_CHANNEL_NETWORK_TX 0x07 //M
++#define AEN_ENABLE 0x08
++#define SET_LINK 0x09 //M
++#define GET_LINK_STATUS 0x0A //M
++#define SET_VLAN_FILTER 0x0B //M
++#define ENABLE_VLAN 0x0C //M
++#define DISABLE_VLAN 0x0D //M
++#define SET_MAC_ADDRESS 0x0E //M
++#define ENABLE_BROADCAST_FILTERING 0x10 //M
++#define DISABLE_BROADCAST_FILTERING 0x11 //M
++#define ENABLE_GLOBAL_MULTICAST_FILTERING 0x12
++#define DISABLE_GLOBAL_MULTICAST_FILTERING 0x13
++#define SET_NCSI_FLOW_CONTROL 0x14
++#define GET_VERSION_ID 0x15 //M
++#define GET_CAPABILITIES 0x16 //M
++#define GET_PARAMETERS 0x17 //M
++#define GET_CONTROLLER_PACKET_STATISTICS 0x18
++#define GET_NCSI_STATISTICS 0x19
++#define GET_NCSI_PASS_THROUGH_STATISTICS 0x1A
++
++//Standard Response Code
++#define COMMAND_COMPLETED 0x00
++#define COMMAND_FAILED 0x01
++#define COMMAND_UNAVAILABLE 0x02
++#define COMMAND_UNSUPPORTED 0x03
++
++//Standard Reason Code
++#define NO_ERROR 0x0000
++#define INTERFACE_INITIALIZATION_REQUIRED 0x0001
++#define PARAMETER_IS_INVALID 0x0002
++#define CHANNEL_NOT_READY 0x0003
++#define PACKAGE_NOT_READY 0x0004
++#define INVALID_PAYLOAD_LENGTH 0x0005
++#define UNKNOWN_COMMAND_TYPE 0x7FFF
++
++//SET_MAC_ADDRESS
++#define UNICAST ( 0x00 << 5 )
++#define MULTICAST ( 0x01 << 5 )
++#define DISABLE_MAC_ADDRESS_FILTER 0x00
++#define ENABLE_MAC_ADDRESS_FILTER 0x01
++
++//GET_LINK_STATUS
++#define LINK_DOWN 0
++#define LINK_UP 1
++
++#define NCSI_RxDMA_PakSize 2048
++#define NCSI_RxDMA_BASE (DMA_BASE+0x00100000)
++
++//---------------------------------------------------------
++// Variable
++//---------------------------------------------------------
++//NC-SI Command Packet
++typedef struct {
++//Ethernet Header
++ unsigned char DA[6]; // Destination Address
++ unsigned char SA[6]; // Source Address
++ unsigned short EtherType; // DMTF NC-SI, it should be 0x88F8
++//NC-SI Control Packet
++ unsigned char MC_ID; // Management Controller should set this field to 0x00
++ unsigned char Header_Revision; // For NC-SI 1.0 spec, this field has to set 0x01
++ unsigned char Reserved_1; // Reserved has to set to 0x00
++ unsigned char IID; // Instance ID
++ unsigned char Command;
++ unsigned char Channel_ID;
++ unsigned short Payload_Length; // Payload Length = 12 bits, 4 bits are reserved
++ unsigned long Reserved_2;
++ unsigned long Reserved_3;
++
++ unsigned short Reserved_4;
++ unsigned short Reserved_5;
++ unsigned short Response_Code;
++ unsigned short Reason_Code;
++ unsigned char Payload_Data[64];
++} NCSI_Command_Packet;
++
++//NC-SI Response Packet
++typedef struct {
++ unsigned char DA[6];
++ unsigned char SA[6];
++ unsigned short EtherType; //DMTF NC-SI
++//NC-SI Control Packet
++ unsigned char MC_ID; //Management Controller should set this field to 0x00
++ unsigned char Header_Revision; //For NC-SI 1.0 spec, this field has to set 0x01
++ unsigned char Reserved_1; //Reserved has to set to 0x00
++ unsigned char IID; //Instance ID
++ unsigned char Command;
++ unsigned char Channel_ID;
++ unsigned short Payload_Length; //Payload Length = 12 bits, 4 bits are reserved
++ unsigned short Reserved_2;
++ unsigned short Reserved_3;
++ unsigned short Reserved_4;
++ unsigned short Reserved_5;
++
++ unsigned short Response_Code;
++ unsigned short Reason_Code;
++ unsigned char Payload_Data[64];
++} NCSI_Response_Packet;
++
++#endif // NCSI_H
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/NCSI.c b/arch/arm/cpu/arm926ejs/aspeed/NCSI.c
+new file mode 100644
+index 0000000..7de06c3
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/NCSI.c
+@@ -0,0 +1,934 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define NCSI_C
++static const char ThisFile[] = "NCSI.c";
++
++#include "SWFUNC.H"
++
++#ifdef SLT_UBOOT
++ #include <common.h>
++ #include <command.h>
++ #include <COMMINF.H>
++ #include <NCSI.H>
++ #include <IO.H>
++#endif
++#ifdef SLT_DOS
++ #include <stdio.h>
++ #include <stdlib.h>
++ #include <conio.h>
++ #include <string.h>
++ #include "COMMINF.H"
++ #include "NCSI.H"
++ #include "IO.H"
++#endif
++
++NCSI_Command_Packet NCSI_Request_SLT;
++NCSI_Response_Packet NCSI_Respond_SLT;
++int InstanceID;
++int NCSI_RxTimeOutScale;
++ULONG NCSI_RxDesBase;
++ULONG NCSI_TxDWBUF[512];
++ULONG NCSI_RxDWBUF[512];
++char NCSI_CommandStr[512];
++unsigned char *NCSI_TxByteBUF;
++unsigned char *NCSI_RxByteBUF;
++unsigned char NCSI_Payload_Data[16];
++unsigned long Payload_Checksum_NCSI = 0x00000000;
++ULONG select_flag[MAX_PACKAGE_NUM];
++
++ULONG DWSwap_SLT (ULONG in) {
++ return( ((in & 0xff000000) >> 24)
++ | ((in & 0x00ff0000) >> 8)
++ | ((in & 0x0000ff00) << 8)
++ | ((in & 0x000000ff) << 24)
++ );
++}
++USHORT WDSwap_SLT (USHORT in) {
++ return( ((in & 0xff00) >> 8)
++ | ((in & 0x00ff) << 8)
++ );
++}
++
++//------------------------------------------------------------
++int FindErr_NCSI (int value) {
++ NCSI_LinkFail_Val = NCSI_LinkFail_Val | value;
++ Err_Flag = Err_Flag | Err_NCSI_LinkFail;
++ if ( DbgPrn_ErrFlg )
++ printf ("\nErr_Flag: [%08lx] NCSI_LinkFail_Val: [%08lx]\n", Err_Flag, NCSI_LinkFail_Val);
++
++ return(1);
++}
++
++//------------------------------------------------------------
++// PHY IC(NC-SI)
++//------------------------------------------------------------
++void ncsi_respdump ( NCSI_Response_Packet *in ) {
++ printf ("DA : %02x %02x %02x %02x %02x %02x\n", in->DA[5], in->DA[4], in->DA[3], in->DA[2], in->DA[1], in->DA[0]);
++ printf ("SA : %02x %02x %02x %02x %02x %02x\n", in->SA[5], in->SA[4], in->SA[3], in->SA[2], in->SA[1], in->SA[0]);
++ printf ("EtherType : %04x\n", in->EtherType );//DMTF NC-SI
++ printf ("MC_ID : %02x\n", in->MC_ID );//Management Controller should set this field to 0x00
++ printf ("Header_Revision: %02x\n", in->Header_Revision );//For NC-SI 1.0 spec, this field has to set 0x01
++// printf ("Reserved_1 : %02x\n", in->Reserved_1 ); //Reserved has to set to 0x00
++ printf ("IID : %02x\n", in->IID );//Instance ID
++ printf ("Command : %02x\n", in->Command );
++ printf ("Channel_ID : %02x\n", in->Channel_ID );
++ printf ("Payload_Length : %04x\n", in->Payload_Length );//Payload Length = 12 bits, 4 bits are reserved
++// printf ("Reserved_2 : %04x\n", in->Reserved_2 );
++// printf ("Reserved_3 : %04x\n", in->Reserved_3 );
++// printf ("Reserved_4 : %04x\n", in->Reserved_4 );
++// printf ("Reserved_5 : %04x\n", in->Reserved_5 );
++ printf ("Response_Code : %04x\n", in->Response_Code );
++ printf ("Reason_Code : %04x\n", in->Reason_Code );
++ printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[ 3], in->Payload_Data[ 2], in->Payload_Data[ 1], in->Payload_Data[ 0]);
++// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[ 7], in->Payload_Data[ 6], in->Payload_Data[ 5], in->Payload_Data[ 4]);
++// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[11], in->Payload_Data[10], in->Payload_Data[ 9], in->Payload_Data[ 8]);
++// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[15], in->Payload_Data[14], in->Payload_Data[13], in->Payload_Data[12]);
++// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[19], in->Payload_Data[18], in->Payload_Data[17], in->Payload_Data[16]);
++// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[23], in->Payload_Data[22], in->Payload_Data[21], in->Payload_Data[20]);
++}
++
++//------------------------------------------------------------
++void NCSI_Struct_Initialize_SLT (void) {
++ int i;
++
++ ULONG NCSI_RxDatBase;
++
++ InstanceID = 0;
++ NCSI_RxTimeOutScale = 1;
++
++ for (i = 0; i < 6; i++) {
++ NCSI_Request_SLT.DA[i] = 0xFF;
++ }
++
++ for (i = 0; i < 6; i++) {
++// NCSI_Request.SA[i] = i<<2;
++ NCSI_Request_SLT.SA[i] = SA[i];
++ }
++
++ NCSI_Request_SLT.EtherType = WDSwap_SLT(0x88F8); // EtherType = 0x88F8 (DMTF NC-SI) page 50, table 8, NC-SI spec. version 1.0.0
++ NCSI_Request_SLT.MC_ID = 0;
++ NCSI_Request_SLT.Header_Revision = 0x01;
++ NCSI_Request_SLT.Reserved_1 = 0;
++ NCSI_Request_SLT.Reserved_2 = 0;
++ NCSI_Request_SLT.Reserved_3 = 0;
++
++ NCSI_TxByteBUF = (unsigned char *) &NCSI_TxDWBUF[0];
++ NCSI_RxByteBUF = (unsigned char *) &NCSI_RxDWBUF[0];
++
++ NCSI_RxDesBase = H_RDES_BASE;
++ NCSI_RxDatBase = NCSI_RxDMA_BASE;
++
++ for (i = 0; i < NCSI_RxDESNum - 1; i++) {
++ WriteSOC_DD( ( NCSI_RxDesBase + 0 ), 0x00000000 );
++ WriteSOC_DD( ( NCSI_RxDesBase + 4 ), 0x00000000 );
++ WriteSOC_DD( ( NCSI_RxDesBase + 8 ), 0x00000000 );
++ WriteSOC_DD( ( NCSI_RxDesBase + 0x0C ), (NCSI_RxDatBase + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
++ NCSI_RxDesBase += 16;
++ NCSI_RxDatBase += NCSI_RxDMA_PakSize;
++ }
++ WriteSOC_DD( ( NCSI_RxDesBase + 0 ), EOR_IniVal );
++ WriteSOC_DD( ( NCSI_RxDesBase + 4 ), 0x00000000 );
++ WriteSOC_DD( ( NCSI_RxDesBase + 8 ), 0x00000000 );
++ WriteSOC_DD( ( NCSI_RxDesBase + 0x0C ), (NCSI_RxDatBase + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
++
++ NCSI_RxDesBase = H_RDES_BASE;
++}
++
++//------------------------------------------------------------
++void Calculate_Checksum_NCSI (unsigned char *buffer_base, int Length) {
++ ULONG CheckSum = 0;
++ ULONG Data;
++ ULONG Data1;
++ int i;
++
++ // Calculate checksum is from byte 14 of ethernet Haeder and Control packet header
++ // Page 50, NC-SI spec. ver. 1.0.0 form DMTF
++ for (i = 14; i < Length; i += 2 ) {
++ Data = buffer_base[i];
++ Data1 = buffer_base[i + 1];
++ CheckSum += ((Data << 8) + Data1);
++ }
++ Payload_Checksum_NCSI = DWSwap_SLT(~(CheckSum) + 1); //2's complement
++}
++
++//------------------------------------------------------------
++// return 0: it is PASS
++// return 1: it is FAIL
++//------------------------------------------------------------
++char NCSI_Rx_SLT (unsigned char command) {
++
++#define NCSI_RX_RETRY_TIME 2
++ int timeout = 0;
++ int bytesize;
++ int dwsize;
++ int i;
++ int retry = 0;
++ char ret = 1;
++
++ ULONG NCSI_RxDatBase;
++ ULONG NCSI_RxDesDat;
++ ULONG NCSI_RxData;
++
++
++ do {
++ WriteSOC_DD( ( H_MAC_BASE + 0x1C ), 0x00000000 );//Rx Poll
++
++ do {
++ NCSI_RxDesDat = ReadSOC_DD(NCSI_RxDesBase);
++ if ( ++timeout > TIME_OUT_NCSI * NCSI_RxTimeOutScale ) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[Cmd:%02X][NCSI-RxDesOwn] %08lX \n", command, NCSI_RxDesDat );
++ #endif
++ return( FindErr(Err_NCSI_Check_RxOwnTimeOut) );
++ }
++ } while( HWOwnRx(NCSI_RxDesDat) );
++
++ #ifdef CheckRxErr
++ if (NCSI_RxDesDat & 0x00040000) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[RxDes] Error RxErr %08lx\n", NCSI_RxDesDat);
++ #endif
++ FindErr_Des(Check_Des_RxErr);
++ }
++ #endif
++
++ #ifdef CheckOddNibble
++ if (NCSI_RxDesDat & 0x00400000) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[RxDes] Odd Nibble %08lx\n", NCSI_RxDesDat);
++ #endif
++ FindErr_Des(Check_Des_OddNibble);
++ }
++ #endif
++
++ #ifdef CheckCRC
++ if (NCSI_RxDesDat & 0x00080000) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[RxDes] Error CRC %08lx\n", NCSI_RxDesDat);
++ #endif
++ FindErr_Des(Check_Des_CRC);
++ }
++ #endif
++
++ #ifdef CheckRxFIFOFull
++ if (NCSI_RxDesDat & 0x00800000) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[RxDes] Error Rx FIFO Full %08lx\n", NCSI_RxDesDat);
++ #endif
++ FindErr_Des(Check_Des_RxFIFOFull);
++ }
++ #endif
++
++ // Get point of RX DMA buffer
++ NCSI_RxDatBase = ReadSOC_DD( NCSI_RxDesBase + 0x0C );
++ NCSI_RxData = ReadSOC_DD( NCSI_RxDatBase + 0x0C );
++
++ if ( HWEOR( NCSI_RxDesDat ) ) {
++ // it is last the descriptor in the receive Ring
++ WriteSOC_DD( NCSI_RxDesBase , EOR_IniVal );
++ NCSI_RxDesBase = H_RDES_BASE;
++ }
++ else {
++ WriteSOC_DD( NCSI_RxDesBase , 0x00000000 );
++ NCSI_RxDesBase += 16;
++ }
++
++ // Get RX valid data in offset 00h of RXDS#0
++ bytesize = (NCSI_RxDesDat & 0x3fff);
++
++ // Fill up to multiple of 4
++ if ( ( bytesize % 4 ) != 0 )
++ dwsize = ( bytesize >> 2 ) + 1;
++ else
++ dwsize = bytesize >> 2;
++
++ #ifdef SLT_DOS
++ if ( PrintNCSIEn )
++ fprintf(fp_log ,"[Rx] %d bytes(%xh)\n", bytesize, bytesize);
++ #endif
++
++ for (i = 0; i < dwsize; i++) {
++ NCSI_RxDWBUF[i] = ReadSOC_DD(NCSI_RxDatBase + ( i << 2 ));
++ if ( PrintNCSIEn ) {
++ if ( i == ( dwsize - 1 ) ) {
++ switch (bytesize % 4) {
++ case 0 : NCSI_RxDWBUF[i] = NCSI_RxDWBUF[i] & 0xffffffff; break;
++ case 3 : NCSI_RxDWBUF[i] = NCSI_RxDWBUF[i] & 0xffffff ; break;
++ case 2 : NCSI_RxDWBUF[i] = NCSI_RxDWBUF[i] & 0xffff ; break;
++ case 1 : NCSI_RxDWBUF[i] = NCSI_RxDWBUF[i] & 0xff ; break;
++ }
++ #ifdef SLT_DOS
++ switch (bytesize % 4) {
++ case 0 : fprintf(fp_log ,"[Rx%02d]%08lx %08lx\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]) ); break;
++ case 3 : fprintf(fp_log ,"[Rx%02d]--%06lx %06lx--\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]) >> 8 ); break;
++ case 2 : fprintf(fp_log ,"[Rx%02d]----%04lx %04lx----\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]) >> 16 ); break;
++ case 1 : fprintf(fp_log ,"[Rx%02d]------%02lx %02lx------\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]) >> 24 ); break;
++ default : fprintf(fp_log ,"[Rx%02d]error", i); break;
++ }
++ #endif
++ }
++ else {
++ #ifdef SLT_DOS
++ fprintf(fp_log ,"[Rx%02d]%08lx %08lx\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]));
++ #endif
++ }
++ }
++ } // End for (i = 0; i < dwsize; i++)
++
++ // EtherType field of the response packet should be 0x88F8
++ if ((NCSI_RxData & 0xffff) == 0xf888) {
++ memcpy (&NCSI_Respond_SLT, NCSI_RxByteBUF, bytesize);
++
++ #ifdef SLT_DOS
++ if ( PrintNCSIEn )
++ fprintf(fp_log ,"[Rx IID:%2d]\n", NCSI_Respond_SLT.IID);
++ #endif
++
++ NCSI_Respond_SLT.EtherType = WDSwap_SLT( NCSI_Respond_SLT.EtherType );
++ NCSI_Respond_SLT.Payload_Length = WDSwap_SLT( NCSI_Respond_SLT.Payload_Length );
++ NCSI_Respond_SLT.Response_Code = WDSwap_SLT( NCSI_Respond_SLT.Response_Code );
++ NCSI_Respond_SLT.Reason_Code = WDSwap_SLT( NCSI_Respond_SLT.Reason_Code );
++
++ ret = 0;
++ break;
++ }
++ else {
++ #ifdef SLT_DOS
++ if ( PrintNCSIEn )
++ fprintf(fp_log, "[Skip] Not NCSI Response: %08lx\n", NCSI_RxData);
++ #endif
++
++ retry++;
++ }
++ } while ( retry < NCSI_RX_RETRY_TIME );
++
++ return( ret );
++} // End char NCSI_Rx_SLT (void)
++
++//------------------------------------------------------------
++char NCSI_Tx (void) {
++ int bytesize;
++ int dwsize;
++ int i;
++ int timeout = 0;
++ ULONG NCSI_TxDesDat;
++
++ // Header of NC-SI command format is 34 bytes. page 58, NC-SI spec. ver 1.0.0 from DMTF
++ // The minimum size of a NC-SI package is 64 bytes.
++ bytesize = 34 + WDSwap_SLT(NCSI_Request_SLT.Payload_Length);
++ if ( bytesize < 64 ) {
++ memset (NCSI_TxByteBUF + bytesize, 0, 60 - bytesize);
++ bytesize = 64;
++ }
++
++ // Fill up to multiple of 4
++// dwsize = (bytesize + 3) >> 2;
++ if ( ( bytesize % 4 ) != 0 )
++ dwsize = ( bytesize >> 2 ) + 1;
++ else
++ dwsize = bytesize >> 2;
++
++ #ifdef SLT_DOS
++ if ( PrintNCSIEn )
++ fprintf(fp_log ,"[Tx IID:%2d] %d bytes(%xh)\n", NCSI_Request_SLT.IID, bytesize, bytesize);
++ #endif
++
++ // Copy data to DMA buffer
++ for (i = 0; i < dwsize; i++) {
++ WriteSOC_DD( DMA_BASE + (i << 2), NCSI_TxDWBUF[i] );
++ if ( PrintNCSIEn ) {
++ if (i == (dwsize - 1)) {
++ switch (bytesize % 4) {
++ case 0 : NCSI_TxDWBUF[i] = NCSI_TxDWBUF[i] & 0xffffffff; break;
++ case 3 : NCSI_TxDWBUF[i] = NCSI_TxDWBUF[i] & 0x00ffffff; break;
++ case 2 : NCSI_TxDWBUF[i] = NCSI_TxDWBUF[i] & 0x0000ffff; break;
++ case 1 : NCSI_TxDWBUF[i] = NCSI_TxDWBUF[i] & 0x000000ff; break;
++ }
++ #ifdef SLT_DOS
++ switch (bytesize % 4) {
++ case 0 : fprintf(fp_log ,"[Tx%02d]%08x %08x\n", i, NCSI_TxDWBUF[i], DWSwap_SLT( NCSI_TxDWBUF[i]) ); break;
++ case 3 : fprintf(fp_log ,"[Tx%02d]--%06x %06x--\n", i, NCSI_TxDWBUF[i], DWSwap_SLT( NCSI_TxDWBUF[i]) >> 8 ); break;
++ case 2 : fprintf(fp_log ,"[Tx%02d]----%04x %04x----\n", i, NCSI_TxDWBUF[i], DWSwap_SLT( NCSI_TxDWBUF[i]) >> 16 ); break;
++ case 1 : fprintf(fp_log ,"[Tx%02d]------%02x %02x------\n", i, NCSI_TxDWBUF[i], DWSwap_SLT( NCSI_TxDWBUF[i]) >> 24 ); break;
++ default : fprintf(fp_log ,"[Tx%02d]error", i); break;
++ }
++ #endif
++ }
++ else {
++ #ifdef SLT_DOS
++ fprintf( fp_log , "[Tx%02d]%08x %08x\n", i, NCSI_TxDWBUF[i], DWSwap_SLT(NCSI_TxDWBUF[i]) );
++ #endif
++ }
++ }
++ } // End for (i = 0; i < dwsize; i++)
++
++ // Setting one TX descriptor
++ WriteSOC_DD( H_TDES_BASE + 0x04, 0 );
++ WriteSOC_DD( H_TDES_BASE + 0x08, 0 );
++ WriteSOC_DD( H_TDES_BASE + 0x0C, (DMA_BASE + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
++ WriteSOC_DD( H_TDES_BASE , 0xf0008000 + bytesize );
++ // Fire
++ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 );//Tx Poll
++
++ do {
++ NCSI_TxDesDat = ReadSOC_DD(H_TDES_BASE);
++ if ( ++timeout > TIME_OUT_NCSI ) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[NCSI-TxDesOwn] %08lx\n", NCSI_TxDesDat);
++ #endif
++
++ return(FindErr(Err_NCSI_Check_TxOwnTimeOut));
++ }
++ } while ( HWOwnTx(NCSI_TxDesDat) );
++
++ return(0);
++} // End char NCSI_Tx (void)
++
++//------------------------------------------------------------
++char NCSI_ARP (void) {
++ int i;
++ int timeout = 0;
++ ULONG NCSI_TxDesDat;
++
++ if ( ARPNumCnt ) {
++ #ifdef SLT_DOS
++ if ( PrintNCSIEn )
++ fprintf(fp_log ,"[ARP] 60 bytes x%d\n", ARPNumCnt);
++ #endif
++
++ for (i = 0; i < 15; i++) {
++ #ifdef SLT_DOS
++ if ( PrintNCSIEn )
++ fprintf(fp_log ,"[Tx%02d] %08x %08x\n", i, ARP_data[i], DWSwap_SLT(ARP_data[i]));
++ #endif
++ WriteSOC_DD( DMA_BASE + ( i << 2 ), ARP_data[i] );
++ }
++ WriteSOC_DD( H_TDES_BASE + 0x04, 0 );
++ WriteSOC_DD( H_TDES_BASE + 0x08, 0 );
++ WriteSOC_DD( H_TDES_BASE + 0x0C, (DMA_BASE + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
++ WriteSOC_DD( H_TDES_BASE , 0xf0008000 + 60 );
++
++ for (i = 0; i < ARPNumCnt; i++) {
++ WriteSOC_DD( H_TDES_BASE , 0xf0008000 + 60);
++
++ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 );//Tx Poll
++
++ timeout = 0;
++ do {
++ NCSI_TxDesDat = ReadSOC_DD(H_TDES_BASE);
++
++ if (++timeout > TIME_OUT_NCSI) {
++ #ifdef SLT_DOS
++ fprintf(fp_log, "[ARP-TxDesOwn] %08lx\n", NCSI_TxDesDat);
++ #endif
++
++ return(FindErr(Err_NCSI_Check_ARPOwnTimeOut));
++ }
++ } while (HWOwnTx(NCSI_TxDesDat));
++ }
++ }
++ return(0);
++} // End char NCSI_ARP (void)
++
++//------------------------------------------------------------
++void WrRequest (unsigned char command, unsigned char id, unsigned short length) {
++
++ NCSI_Request_SLT.IID = InstanceID;
++ NCSI_Request_SLT.Command = command;
++ NCSI_Request_SLT.Channel_ID = id;
++ NCSI_Request_SLT.Payload_Length = WDSwap_SLT(length);
++
++ memcpy ( NCSI_TxByteBUF , &NCSI_Request_SLT , 30 );
++ memcpy ((NCSI_TxByteBUF + 30 ), &NCSI_Payload_Data , length);
++ Calculate_Checksum_NCSI(NCSI_TxByteBUF, 30 + length);
++ memcpy ((NCSI_TxByteBUF + 30 + length), &Payload_Checksum_NCSI, 4 );
++}
++
++//------------------------------------------------------------
++void NCSI_PrintCommandStr (unsigned char command, unsigned iid) {
++ switch (command & 0x80) {
++ case 0x80 : sprintf(NCSI_CommandStr, "IID:%3d [%02x][Respond]", iid, command); break;
++ default : sprintf(NCSI_CommandStr, "IID:%3d [%02x][Request]", iid, command); break;
++ }
++ switch (command & 0x7f) {
++ case 0x00 : sprintf(NCSI_CommandStr, "%s[CLEAR_INITIAL_STATE ]", NCSI_CommandStr); break;
++ case 0x01 : sprintf(NCSI_CommandStr, "%s[SELECT_PACKAGE ]", NCSI_CommandStr); break;
++ case 0x02 : sprintf(NCSI_CommandStr, "%s[DESELECT_PACKAGE ]", NCSI_CommandStr); break;
++ case 0x03 : sprintf(NCSI_CommandStr, "%s[ENABLE_CHANNEL ]", NCSI_CommandStr); break;
++ case 0x04 : sprintf(NCSI_CommandStr, "%s[DISABLE_CHANNEL ]", NCSI_CommandStr); break;
++ case 0x05 : sprintf(NCSI_CommandStr, "%s[RESET_CHANNEL ]", NCSI_CommandStr); break;
++ case 0x06 : sprintf(NCSI_CommandStr, "%s[ENABLE_CHANNEL_NETWORK_TX ]", NCSI_CommandStr); break;
++ case 0x07 : sprintf(NCSI_CommandStr, "%s[DISABLE_CHANNEL_NETWORK_TX ]", NCSI_CommandStr); break;
++ case 0x08 : sprintf(NCSI_CommandStr, "%s[AEN_ENABLE ]", NCSI_CommandStr); break;
++ case 0x09 : sprintf(NCSI_CommandStr, "%s[SET_LINK ]", NCSI_CommandStr); break;
++ case 0x0A : sprintf(NCSI_CommandStr, "%s[GET_LINK_STATUS ]", NCSI_CommandStr); break;
++ case 0x0B : sprintf(NCSI_CommandStr, "%s[SET_VLAN_FILTER ]", NCSI_CommandStr); break;
++ case 0x0C : sprintf(NCSI_CommandStr, "%s[ENABLE_VLAN ]", NCSI_CommandStr); break;
++ case 0x0D : sprintf(NCSI_CommandStr, "%s[DISABLE_VLAN ]", NCSI_CommandStr); break;
++ case 0x0E : sprintf(NCSI_CommandStr, "%s[SET_MAC_ADDRESS ]", NCSI_CommandStr); break;
++ case 0x10 : sprintf(NCSI_CommandStr, "%s[ENABLE_BROADCAST_FILTERING ]", NCSI_CommandStr); break;
++ case 0x11 : sprintf(NCSI_CommandStr, "%s[DISABLE_BROADCAST_FILTERING ]", NCSI_CommandStr); break;
++ case 0x12 : sprintf(NCSI_CommandStr, "%s[ENABLE_GLOBAL_MULTICAST_FILTERING ]", NCSI_CommandStr); break;
++ case 0x13 : sprintf(NCSI_CommandStr, "%s[DISABLE_GLOBAL_MULTICAST_FILTERING ]", NCSI_CommandStr); break;
++ case 0x14 : sprintf(NCSI_CommandStr, "%s[SET_NCSI_FLOW_CONTROL ]", NCSI_CommandStr); break;
++ case 0x15 : sprintf(NCSI_CommandStr, "%s[GET_VERSION_ID ]", NCSI_CommandStr); break;
++ case 0x16 : sprintf(NCSI_CommandStr, "%s[GET_CAPABILITIES ]", NCSI_CommandStr); break;
++ case 0x17 : sprintf(NCSI_CommandStr, "%s[GET_PARAMETERS ]", NCSI_CommandStr); break;
++ case 0x18 : sprintf(NCSI_CommandStr, "%s[GET_CONTROLLER_PACKET_STATISTICS ]", NCSI_CommandStr); break;
++ case 0x19 : sprintf(NCSI_CommandStr, "%s[GET_NCSI_STATISTICS ]", NCSI_CommandStr); break;
++ case 0x1A : sprintf(NCSI_CommandStr, "%s[GET_NCSI_PASS_THROUGH_STATISTICS ]", NCSI_CommandStr); break;
++ case 0x50 : sprintf(NCSI_CommandStr, "%s[OEM_COMMAND ]", NCSI_CommandStr); break;
++ default : sprintf(NCSI_CommandStr, "%s Not Support Command", NCSI_CommandStr); break ;
++ }
++} // End void NCSI_PrintCommandStr (unsigned char command, unsigned iid)
++
++//------------------------------------------------------------
++void NCSI_PrintCommandType (unsigned char command, unsigned iid) {
++ NCSI_PrintCommandStr(command, iid);
++ printf ("%s\n", NCSI_CommandStr);
++}
++
++//------------------------------------------------------------
++void NCSI_PrintCommandType2File (unsigned char command, unsigned iid) {
++ NCSI_PrintCommandStr(command, iid);
++ #ifdef SLT_DOS
++ fprintf(fp_log, "%s\n", NCSI_CommandStr);
++ #endif
++}
++
++//------------------------------------------------------------
++char NCSI_SentWaitPacket (unsigned char command, unsigned char id, unsigned short length) {
++ int Retry = 0;
++ char ret;
++
++ do {
++ InstanceID++;
++ WrRequest(command, id, length);
++
++ ret = NCSI_Tx(); if ( ret != 0 )
++ {
++ // printf("======> NCSI_Tx return code = %X\n", ret );
++ return(1);
++ }
++#ifdef Print_PackageName
++ NCSI_PrintCommandType(command, InstanceID);
++#endif
++
++#ifdef NCSI_EnableDelay_EachPackage
++ delay(Delay_EachPackage);
++#endif
++ if ( NCSI_Rx_SLT( command ) )
++ return(2);
++
++ #ifdef SLT_DOS
++ if ( PrintNCSIEn )
++ fprintf(fp_log, "[Request] ETyp:%04x MC_ID:%02x HeadVer:%02x IID:%02x Comm:%02x ChlID:%02x PayLen:%04x\n", WDSwap_SLT(NCSI_Request_SLT.EtherType),
++ NCSI_Request_SLT.MC_ID,
++ NCSI_Request_SLT.Header_Revision,
++ NCSI_Request_SLT.IID,
++ NCSI_Request_SLT.Command,
++ NCSI_Request_SLT.Channel_ID,
++ WDSwap_SLT(NCSI_Request_SLT.Payload_Length) );
++ if ( PrintNCSIEn )
++ fprintf(fp_log, "[Respond] ETyp:%04x MC_ID:%02x HeadVer:%02x IID:%02x Comm:%02x ChlID:%02x PayLen:%04x ResCd:%02x ReaCd:%02x\n",
++ NCSI_Respond_SLT.EtherType,
++ NCSI_Respond_SLT.MC_ID,
++ NCSI_Respond_SLT.Header_Revision,
++ NCSI_Respond_SLT.IID,
++ NCSI_Respond_SLT.Command,
++ NCSI_Respond_SLT.Channel_ID,
++ NCSI_Respond_SLT.Payload_Length,
++ NCSI_Respond_SLT.Response_Code,
++ NCSI_Respond_SLT.Reason_Code);
++ #endif
++
++ if ( (NCSI_Respond_SLT.IID != InstanceID) ||
++ (NCSI_Respond_SLT.Command != (command | 0x80)) ||
++ (NCSI_Respond_SLT.Response_Code != COMMAND_COMPLETED) ) {
++ #ifdef SLT_DOS
++ if ( PrintNCSIEn )
++ fprintf(fp_log, "Retry: Command = %x, Response_Code = %x\n", NCSI_Request_SLT.Command, NCSI_Respond_SLT.Response_Code);
++
++ #endif
++ Retry++;
++ }
++ else {
++ if ( PrintNCSIEn )
++ NCSI_PrintCommandType2File(command, InstanceID);
++
++ return(0);
++ }
++ } while (Retry <= SENT_RETRY_COUNT);
++
++ return( 3 );
++} // End char NCSI_SentWaitPacket (unsigned char command, unsigned char id, unsigned short length)
++
++//------------------------------------------------------------
++char Clear_Initial_State_SLT (int Channel_ID) {//Command:0x00
++ return(NCSI_SentWaitPacket(CLEAR_INITIAL_STATE, (NCSI_Cap_SLT.Package_ID << 5) + Channel_ID, 0));//Internal Channel ID = 0
++}
++
++//------------------------------------------------------------
++char Select_Package_SLT (int Package_ID) {//Command:0x01
++ memset ((void *)NCSI_Payload_Data, 0, 4);
++ NCSI_Payload_Data[3] = 1; //Arbitration Disable
++
++ return(NCSI_SentWaitPacket(SELECT_PACKAGE, (Package_ID << 5) + 0x1F, 4));//Internal Channel ID = 0x1F, 0x1F means all channel
++}
++
++//------------------------------------------------------------
++void Select_Active_Package_SLT (void) {//Command:0x01
++ memset ((void *)NCSI_Payload_Data, 0, 4);
++ NCSI_Payload_Data[3] = 1; //Arbitration Disable
++
++ if (NCSI_SentWaitPacket(SELECT_PACKAGE, (NCSI_Cap_SLT.Package_ID << 5) + 0x1F, 4)) {//Internal Channel ID = 0x1F
++ FindErr_NCSI(NCSI_LinkFail_Select_Active_Package);
++ }
++}
++
++//------------------------------------------------------------
++void DeSelect_Package_SLT (int Package_ID) {//Command:0x02
++ NCSI_SentWaitPacket(DESELECT_PACKAGE, (Package_ID << 5) + 0x1F, 0);//Internal Channel ID = 0x1F, 0x1F means all channel
++
++#ifdef NCSI_EnableDelay_DeSelectPackage
++ delay(Delay_DeSelectPackage);
++#endif
++}
++
++//------------------------------------------------------------
++void Enable_Channel_SLT (void) {//Command:0x03
++ if ( NCSI_SentWaitPacket(ENABLE_CHANNEL, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0) ) {
++ FindErr_NCSI(NCSI_LinkFail_Enable_Channel);
++ }
++}
++
++//------------------------------------------------------------
++void Disable_Channel_SLT (void) {//Command:0x04
++ memset ((void *)NCSI_Payload_Data, 0, 4);
++ NCSI_Payload_Data[3] = 0x1; //ALD
++
++ if (NCSI_SentWaitPacket(DISABLE_CHANNEL, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 4)) {
++ FindErr_NCSI(NCSI_LinkFail_Disable_Channel);
++ }
++}
++void Enable_Network_TX_SLT (void) {//Command:0x06
++ if ( NCSI_SentWaitPacket(ENABLE_CHANNEL_NETWORK_TX, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0) ) {
++ FindErr_NCSI(NCSI_LinkFail_Enable_Network_TX);
++ }
++}
++
++//------------------------------------------------------------
++void Disable_Network_TX_SLT (void) {//Command:0x07
++ if ( NCSI_SentWaitPacket(DISABLE_CHANNEL_NETWORK_TX, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0) ) {
++ FindErr_NCSI(NCSI_LinkFail_Disable_Network_TX);
++ }
++}
++
++//------------------------------------------------------------
++void Set_Link_SLT (void) {//Command:0x09
++ memset ((void *)NCSI_Payload_Data, 0, 8);
++ NCSI_Payload_Data[2] = 0x02; //full duplex
++// NCSI_Payload_Data[3] = 0x04; //100M, auto-disable
++ NCSI_Payload_Data[3] = 0x05; //100M, auto-enable
++
++ NCSI_SentWaitPacket(SET_LINK, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 8);
++}
++
++//------------------------------------------------------------
++char Get_Link_Status_SLT (void) {//Command:0x0a
++
++ if (NCSI_SentWaitPacket(GET_LINK_STATUS, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0)) {
++ return(0);
++ }
++ else {
++ if (NCSI_Respond_SLT.Payload_Data[3] & 0x20) {
++ if (NCSI_Respond_SLT.Payload_Data[3] & 0x40) {
++ if (NCSI_Respond_SLT.Payload_Data[3] & 0x01)
++ return(1); //Link Up or Not
++ else
++ return(0);
++ } else
++ return(0); //Auto Negotiate did not finish
++ } else {
++ if (NCSI_Respond_SLT.Payload_Data[3] & 0x01)
++ return(1); //Link Up or Not
++ else
++ return(0);
++ }
++ }
++} // End char Get_Link_Status_SLT (void)
++
++//------------------------------------------------------------
++void Enable_Set_MAC_Address_SLT (void) {//Command:0x0e
++ int i;
++
++ for ( i = 0; i < 6; i++ ) {
++ NCSI_Payload_Data[i] = NCSI_Request_SLT.SA[i];
++ }
++ NCSI_Payload_Data[6] = 1; //MAC Address Num = 1 --> address filter 1, fixed in sample code
++ NCSI_Payload_Data[7] = UNICAST + 0 + ENABLE_MAC_ADDRESS_FILTER; //AT + Reserved + E
++
++ if ( NCSI_SentWaitPacket(SET_MAC_ADDRESS, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 8) ) {
++ FindErr_NCSI(NCSI_LinkFail_Enable_Set_MAC_Address);
++ }
++}
++
++//------------------------------------------------------------
++void Enable_Broadcast_Filter_SLT (void) {//Command:0x10
++ memset ((void *)NCSI_Payload_Data, 0, 4);
++ NCSI_Payload_Data[3] = 0xF; //ARP, DHCP, NetBIOS
++
++ if (NCSI_SentWaitPacket(ENABLE_BROADCAST_FILTERING, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 4) ) {
++ FindErr_NCSI(NCSI_LinkFail_Enable_Broadcast_Filter);
++ }
++}
++
++//------------------------------------------------------------
++void Get_Version_ID_SLT (void) {//Command:0x15
++
++ if (NCSI_SentWaitPacket(GET_VERSION_ID, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0) ) {
++ FindErr_NCSI(NCSI_LinkFail_Get_Version_ID);
++ }
++ else {
++#ifdef Print_Version_ID
++ printf ("NCSI Version : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[ 0], NCSI_Respond_SLT.Payload_Data[ 1], NCSI_Respond_SLT.Payload_Data[ 2], NCSI_Respond_SLT.Payload_Data[ 3]);
++ printf ("NCSI Version : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[ 4], NCSI_Respond_SLT.Payload_Data[ 5], NCSI_Respond_SLT.Payload_Data[ 6], NCSI_Respond_SLT.Payload_Data[ 7]);
++ printf ("Firmware Name String: %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[ 8], NCSI_Respond_SLT.Payload_Data[ 9], NCSI_Respond_SLT.Payload_Data[10], NCSI_Respond_SLT.Payload_Data[11]);
++ printf ("Firmware Name String: %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[12], NCSI_Respond_SLT.Payload_Data[13], NCSI_Respond_SLT.Payload_Data[14], NCSI_Respond_SLT.Payload_Data[15]);
++ printf ("Firmware Name String: %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[16], NCSI_Respond_SLT.Payload_Data[17], NCSI_Respond_SLT.Payload_Data[18], NCSI_Respond_SLT.Payload_Data[19]);
++ printf ("Firmware Version : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[20], NCSI_Respond_SLT.Payload_Data[21], NCSI_Respond_SLT.Payload_Data[22], NCSI_Respond_SLT.Payload_Data[23]);
++ printf ("PCI DID/VID : %02x %02x/%02x %02x\n", NCSI_Respond_SLT.Payload_Data[24], NCSI_Respond_SLT.Payload_Data[25], NCSI_Respond_SLT.Payload_Data[26], NCSI_Respond_SLT.Payload_Data[27]);
++ printf ("PCI SSID/SVID : %02x %02x/%02x %02x\n", NCSI_Respond_SLT.Payload_Data[28], NCSI_Respond_SLT.Payload_Data[29], NCSI_Respond_SLT.Payload_Data[30], NCSI_Respond_SLT.Payload_Data[31]);
++ printf ("Manufacturer ID : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[32], NCSI_Respond_SLT.Payload_Data[33], NCSI_Respond_SLT.Payload_Data[34], NCSI_Respond_SLT.Payload_Data[35]);
++ printf ("Checksum : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[36], NCSI_Respond_SLT.Payload_Data[37], NCSI_Respond_SLT.Payload_Data[38], NCSI_Respond_SLT.Payload_Data[39]);
++#endif
++ NCSI_Cap_SLT.PCI_DID_VID = (NCSI_Respond_SLT.Payload_Data[24]<<24)
++ | (NCSI_Respond_SLT.Payload_Data[25]<<16)
++ | (NCSI_Respond_SLT.Payload_Data[26]<< 8)
++ | (NCSI_Respond_SLT.Payload_Data[27] );
++ NCSI_Cap_SLT.ManufacturerID = (NCSI_Respond_SLT.Payload_Data[32]<<24)
++ | (NCSI_Respond_SLT.Payload_Data[33]<<16)
++ | (NCSI_Respond_SLT.Payload_Data[34]<< 8)
++ | (NCSI_Respond_SLT.Payload_Data[35] );
++ }
++} // End void Get_Version_ID_SLT (void)
++
++//------------------------------------------------------------
++void Get_Capabilities_SLT (void) {//Command:0x16
++
++ if (NCSI_SentWaitPacket(GET_CAPABILITIES, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0)) {
++ FindErr_NCSI(NCSI_LinkFail_Get_Capabilities);
++ }
++ else {
++ NCSI_Cap_SLT.Capabilities_Flags = NCSI_Respond_SLT.Payload_Data[0];
++ NCSI_Cap_SLT.Broadcast_Packet_Filter_Capabilities = NCSI_Respond_SLT.Payload_Data[1];
++ NCSI_Cap_SLT.Multicast_Packet_Filter_Capabilities = NCSI_Respond_SLT.Payload_Data[2];
++ NCSI_Cap_SLT.Buffering_Capabilities = NCSI_Respond_SLT.Payload_Data[3];
++ NCSI_Cap_SLT.AEN_Control_Support = NCSI_Respond_SLT.Payload_Data[4];
++ }
++}
++
++//------------------------------------------------------------
++void Get_Controller_Packet_Statistics (void) {//Command:0x18
++
++ NCSI_SentWaitPacket(GET_CONTROLLER_PACKET_STATISTICS, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0);
++}
++
++//------------------------------------------------------------
++char phy_ncsi (void) {
++ ULONG Channel_Found = 0;
++ ULONG Package_Found = 0;
++ ULONG Re_Send;
++ ULONG Err_Flag_bak;
++ ULONG pkg_idx;
++ ULONG chl_idx;
++ ULONG Link_Status;
++ ULONG NCSI_LinkFail_Val_bak;
++
++ number_chl = 0;
++ number_pak = 0;
++
++ NCSI_LinkFail_Val = 0;
++ #ifdef SLT_DOS
++ fprintf(fp_log, "\n\n======> Start:\n" );
++ #endif
++ NCSI_Struct_Initialize_SLT();
++
++ #ifdef NCSI_Skip_Phase1_DeSelectPackage
++ #else
++
++ //NCSI Start
++ //Disable Channel then DeSelect Package
++ for (pkg_idx = 0; pkg_idx < MAX_PACKAGE_NUM; pkg_idx++) {
++ // Ignore error flag in the NCSI command
++ Err_Flag_bak = Err_Flag;
++ NCSI_LinkFail_Val_bak = NCSI_LinkFail_Val;
++ select_flag[pkg_idx] = Select_Package_SLT (pkg_idx); // Command:0x01
++ Err_Flag = Err_Flag_bak;
++ NCSI_LinkFail_Val = NCSI_LinkFail_Val_bak;
++
++ if ( select_flag[pkg_idx] == 0 ) {
++ NCSI_Cap_SLT.Package_ID = pkg_idx;
++
++ for ( chl_idx = 0; chl_idx < MAX_CHANNEL_NUM; chl_idx++ ) {
++ NCSI_Cap_SLT.Channel_ID = chl_idx;
++ // Ignore error flag in the NCSI command
++ Err_Flag_bak = Err_Flag;
++ NCSI_LinkFail_Val_bak = NCSI_LinkFail_Val;
++ Disable_Channel_SLT(); // Command: 0x04
++ Err_Flag = Err_Flag_bak;
++ NCSI_LinkFail_Val = NCSI_LinkFail_Val_bak;
++ }
++ #ifdef NCSI_Skip_DeSelectPackage
++ #else
++ DeSelect_Package_SLT (pkg_idx); // Command:0x02
++ #endif
++ } // End if ( select_flag[pkg_idx] == 0 )
++ } // End for (pkg_idx = 0; pkg_idx < MAX_PACKAGE_NUM; pkg_idx++)
++ #endif
++
++ //Select Package
++ for (pkg_idx = 0; pkg_idx < MAX_PACKAGE_NUM; pkg_idx++) {
++ #ifdef NCSI_Skip_Phase1_DeSelectPackage
++ // Ignore error flag in the NCSI command
++ Err_Flag_bak = Err_Flag;
++ NCSI_LinkFail_Val_bak = NCSI_LinkFail_Val;
++ select_flag[pkg_idx] = Select_Package_SLT (pkg_idx);//Command:0x01
++ Err_Flag = Err_Flag_bak;
++ NCSI_LinkFail_Val = NCSI_LinkFail_Val_bak;
++ #endif
++
++ if (select_flag[pkg_idx] == 0) {
++ //NCSI_RxTimeOutScale = 1000;
++ NCSI_RxTimeOutScale = 10;
++ number_pak++;
++ Package_Found = 1;
++ NCSI_Cap_SLT.Package_ID = pkg_idx;
++
++ if ( !(IOTiming||IOTimingBund) )
++ printf ("====Find Package ID: %d\n", NCSI_Cap_SLT.Package_ID);
++ #ifdef SLT_DOS
++ fprintf(fp_log, "====Find Package ID: %d\n", NCSI_Cap_SLT.Package_ID);
++ #endif
++
++ #ifdef NCSI_Skip_Phase1_DeSelectPackage
++ #else
++ Select_Package_SLT (pkg_idx);//Command:0x01
++ #endif
++
++ // Scan all channel in the package
++ for ( chl_idx = 0; chl_idx < MAX_CHANNEL_NUM; chl_idx++ ) {
++ // backup error flag
++ Err_Flag_bak = Err_Flag;
++ NCSI_LinkFail_Val_bak = NCSI_LinkFail_Val;
++ if (Clear_Initial_State_SLT(chl_idx) == 0) { //Command:0x00
++ number_chl++;
++ Channel_Found = 1;
++ NCSI_Cap_SLT.Channel_ID = chl_idx;
++
++ if ( !(IOTiming || IOTimingBund) )
++ printf ("--------Find Channel ID: %d\n", NCSI_Cap_SLT.Channel_ID);
++
++ #ifdef SLT_DOS
++ fprintf(fp_log, "--------Find Channel ID: %d\n", NCSI_Cap_SLT.Channel_ID);
++ #endif
++ // Get Version and Capabilities
++ Get_Version_ID_SLT(); //Command:0x15
++ Get_Capabilities_SLT(); //Command:0x16
++ Select_Active_Package_SLT(); //Command:0x01
++ Enable_Set_MAC_Address_SLT(); //Command:0x0e
++ Enable_Broadcast_Filter_SLT(); //Command:0x10
++
++ // Enable TX
++ Enable_Network_TX_SLT(); //Command:0x06
++
++ // Enable Channel
++ Enable_Channel_SLT(); //Command:0x03
++
++ // Get Link Status
++ Re_Send = 0;
++ do {
++ #ifdef NCSI_EnableDelay_GetLinkStatus
++ if ( Re_Send >= 2 )
++ delay(Delay_GetLinkStatus);
++ #endif
++
++ Link_Status = Get_Link_Status_SLT();//Command:0x0a
++
++ if ( Link_Status == LINK_UP ) {
++ if (!(IOTiming||IOTimingBund))
++ printf (" This Channel is LINK_UP\n");
++
++ #ifdef SLT_DOS
++ fprintf(fp_log, " This Channel is LINK_UP\n");
++ #endif
++
++ NCSI_ARP ();
++
++ break;
++ }
++ else if ( Link_Status == LINK_DOWN ) {
++ if ( Re_Send >= 2 ) {
++ if ( !(IOTiming || IOTimingBund) )
++ printf (" This Channel is LINK_DOWN\n");
++
++ #ifdef SLT_DOS
++ fprintf(fp_log, " This Channel is LINK_DOWN\n");
++ #endif
++
++ break;
++ }
++ } // End if ( Link_Status == LINK_UP )
++ } while ( Re_Send++ <= 2 );
++
++ #ifdef NCSI_Skip_DiSChannel
++ #else
++ if ( NCSI_DiSChannel ) {
++ // Disable TX
++ Disable_Network_TX_SLT(); //Command:0x07
++ // Disable Channel
++ Disable_Channel_SLT(); //Command:0x04
++ }
++ #endif
++ }
++ else {
++ Err_Flag = Err_Flag_bak;
++ NCSI_LinkFail_Val = NCSI_LinkFail_Val_bak;
++ }
++ } // End for ( chl_idx = 0; chl_idx < MAX_CHANNEL_NUM; chl_idx++ )
++
++ #ifdef NCSI_Skip_DeSelectPackage
++ #else
++ DeSelect_Package_SLT (pkg_idx);//Command:0x02
++ #endif
++ NCSI_RxTimeOutScale = 1;
++ }
++ else {
++ if (!(IOTiming||IOTimingBund)) {
++ printf ("====Absence of Package ID: %ld\n", pkg_idx);
++ #ifdef SLT_DOS
++ fprintf(fp_log, "====Absence of Package ID: %ld\n", pkg_idx);
++ #endif
++ }
++ } // End if (select_flag[pkg_idx] == 0)
++ } // End for (pkg_idx = 0; pkg_idx < MAX_PACKAGE_NUM; pkg_idx++)
++
++ if ( !Package_Found ) FindErr( Err_NCSI_No_PHY );
++ if ( ChannelTolNum != number_chl ) FindErr( Err_NCSI_Channel_Num );
++ if ( PackageTolNum != number_pak ) FindErr( Err_NCSI_Package_Num );
++// if ( !Channel_Found) FindErr();
++
++ if ( Err_Flag )
++ return(1);
++ else
++ return(0);
++}
++
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/PCI_SPI.c b/arch/arm/cpu/arm926ejs/aspeed/PCI_SPI.c
+new file mode 100644
+index 0000000..77aac47
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/PCI_SPI.c
+@@ -0,0 +1,83 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define PCI_SPI_C
++static const char ThisFile[] = "PCI_SPI.c";
++
++#include "SWFUNC.H"
++
++#ifdef SLT_UBOOT
++ #include <common.h>
++ #include <command.h>
++#endif
++#ifdef SLT_DOS
++ #include <stdio.h>
++ #include <stdlib.h>
++ #include <conio.h>
++ #include <string.h>
++ #include <dos.h>
++#endif
++
++#include "DEF_SPI.H"
++#include "LIB.H"
++#include "TYPEDEF.H"
++
++#ifdef SPI_BUS
++ULONG GetPCIInfo (DEVICE_PCI_INFO *VGAPCIInfo)
++{
++ ULONG ulPCIBaseAddress, MMIOBaseAddress, LinearAddressBase, busnum, data;
++
++ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x2000, ACTIVE);
++ busnum = 0;
++ while (ulPCIBaseAddress == 0 && busnum < 256) {
++ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x2000, busnum);
++ if (ulPCIBaseAddress == 0) {
++ ulPCIBaseAddress = FindPCIDevice (0x1688, 0x2000, busnum);
++ }
++ if (ulPCIBaseAddress == 0) {
++ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x1160, busnum);
++ }
++ if (ulPCIBaseAddress == 0) {
++ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x1180, busnum);
++ }
++ busnum++;
++ }
++ printf ("ulPCIBaseAddress = %lx\n", ulPCIBaseAddress);
++ if (ulPCIBaseAddress != 0) {
++ VGAPCIInfo->ulPCIConfigurationBaseAddress = ulPCIBaseAddress;
++ VGAPCIInfo->usVendorID = ReadPCIReg(ulPCIBaseAddress, 0, 0xFFFF);
++ VGAPCIInfo->usDeviceID = ReadPCIReg(ulPCIBaseAddress, 0, 0xFFFF0000) >> 16;
++ LinearAddressBase = ReadPCIReg (ulPCIBaseAddress, 0x10, 0xFFFFFFF0);
++ VGAPCIInfo->ulPhysicalBaseAddress = MapPhysicalToLinear (LinearAddressBase, 64 * 1024 * 1024 + 0x200000);
++ MMIOBaseAddress = ReadPCIReg (ulPCIBaseAddress, 0x14, 0xFFFF0000);
++ VGAPCIInfo->ulMMIOBaseAddress = MapPhysicalToLinear (MMIOBaseAddress, 64 * 1024 * 1024);
++ VGAPCIInfo->usRelocateIO = ReadPCIReg (ulPCIBaseAddress, 0x18, 0x0000FF80);
++ OUTDWPORT(0xcf8, ulPCIBaseAddress + 0x4);
++ data = INDWPORT(0xcfc);
++ OUTDWPORT(0xcfc, data | 0x3);
++ return TRUE;
++ }
++ else {
++ return FALSE;
++ }
++} // End ULONG GetPCIInfo (DEVICE_PCI_INFO *VGAPCIInfo)
++
++BOOLEAN GetDevicePCIInfo (VIDEO_ENGINE_INFO *VideoEngineInfo)
++{
++ if (GetPCIInfo (&VideoEngineInfo->VGAPCIInfo) == TRUE) {
++ return TRUE;
++ }
++ else {
++ printf("Can not find PCI device!\n");
++ exit(0);
++ return FALSE;
++ }
++} // End
++#endif // End ifdef SPI_BUS
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/PHY.H b/arch/arm/cpu/arm926ejs/aspeed/PHY.H
+new file mode 100644
+index 0000000..81d9470
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/PHY.H
+@@ -0,0 +1,56 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef PHY_H
++#define PHY_H
++
++//
++// Define
++//
++#define Enable_SearchPHYID //[ON] (Search vlid PHY ID)
++#define Enable_CheckZeroPHYID //[ON] (Check PHY ID with value 0)
++
++#ifdef Enable_CheckZeroPHYID
++ #define PHY_IS_VALID( dat ) ( ( (dat & 0xffff) != 0xffff ) && ( ( dat & 0xffff ) != 0x0 ) )
++#else
++ #define PHY_IS_VALID( dat ) ( ( dat & 0xffff) != 0xffff )
++#endif
++
++// Define PHY basic register
++#define PHY_REG_BMCR 0x00 // Basic Mode Control Register
++#define PHY_REG_BMSR 0x01 // Basic Mode Status Register
++#define PHY_REG_ID_1 0x02
++#define PHY_REG_ID_2 0x03
++#define PHY_ANER 0x06 // Auto-negotiation Expansion Register
++#define PHY_GBCR 0x09 // 1000Base-T Control Register
++#define PHY_SR 0x11 // PHY Specific Status Register
++#define PHY_INER 0x12 // Interrupt Enable Register
++
++#define TIME_OUT_PHY_RW 10000
++#define TIME_OUT_PHY_Rst 10000
++
++#define PHYID3_Mask 0xfc00 //0xffc0
++
++/* --- Note for SettingPHY chip ---
++void phy_xxxx (int loop_phy) {
++
++ if ( BurstEnable ) {
++ // IEEE test
++ }
++ else if (loop_phy) {
++ // Internal loop back
++ }
++ else {
++ // external loop back
++ }
++}
++----------------------------------- */
++
++#endif // PHY_H
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/PHY.c b/arch/arm/cpu/arm926ejs/aspeed/PHY.c
+new file mode 100644
+index 0000000..6afed9d
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/PHY.c
+@@ -0,0 +1,1541 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define PHY_C
++static const char ThisFile[] = "PHY.c";
++
++#include "SWFUNC.H"
++
++#ifdef SLT_UBOOT
++ #include <common.h>
++ #include <command.h>
++ #include <COMMINF.H>
++ #include "STDUBOOT.H"
++#endif
++#ifdef SLT_DOS
++ #include <stdio.h>
++ #include <stdlib.h>
++ #include <conio.h>
++ #include <string.h>
++ #include "COMMINF.H"
++#endif
++
++#include "PHY.H"
++#include "TYPEDEF.H"
++#include "IO.H"
++
++ULONG PHY_09h;
++ULONG PHY_18h;
++ULONG PHY_1fh;
++ULONG PHY_06hA[7];
++ULONG PHY_11h;
++ULONG PHY_12h;
++ULONG PHY_15h;
++ULONG PHY_06h;
++char PHYID[256];
++ULONG PHY_00h;
++
++//------------------------------------------------------------
++// PHY R/W basic
++//------------------------------------------------------------
++void phy_write (int adr, ULONG data) {
++ int timeout = 0;
++
++ if (AST2300_NewMDIO) {
++ WriteSOC_DD( MAC_PHYBASE + 0x60, ( data << 16 ) | MAC_PHYWr_New | (PHY_ADR<<5) | (adr & 0x1f));
++
++ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYBusy_New ) {
++ if ( ++timeout > TIME_OUT_PHY_RW ) {
++ if (!BurstEnable)
++#ifdef SLT_DOS
++ fprintf(fp_log, "[PHY-Write] Time out: %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0x60 ) );
++#endif
++ FindErr( Err_PHY_TimeOut );
++ break;
++ }
++ }
++ }
++ else {
++ WriteSOC_DD( MAC_PHYBASE + 0x64, data );
++
++ WriteSOC_DD( MAC_PHYBASE + 0x60, MDC_Thres | MAC_PHYWr | (PHY_ADR<<16) | ((adr & 0x1f) << 21));
++
++ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYWr ) {
++ if ( ++timeout > TIME_OUT_PHY_RW ) {
++#ifdef SLT_DOS
++ if (!BurstEnable)
++ fprintf(fp_log, "[PHY-Write] Time out: %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0x60 ) );
++#endif
++ FindErr( Err_PHY_TimeOut );
++ break;
++ }
++ }
++ } // End if (AST2300_NewMDIO)
++
++ if ( DbgPrn_PHYRW )
++ printf ("[Wr ]%02d: %04lx\n", adr, data);
++} // End void phy_write (int adr, ULONG data)
++
++//------------------------------------------------------------
++ULONG phy_read (int adr) {
++ int timeout = 0;
++
++ if ( AST2300_NewMDIO ) {
++ WriteSOC_DD( MAC_PHYBASE + 0x60, MAC_PHYRd_New | (PHY_ADR << 5) | ( adr & 0x1f ) );
++
++ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYBusy_New ) {
++ if ( ++timeout > TIME_OUT_PHY_RW ) {
++ if ( !BurstEnable )
++#ifdef SLT_DOS
++ fprintf(fp_log, "[PHY-Read] Time out: %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0x60 ));
++#endif
++ FindErr( Err_PHY_TimeOut );
++ break;
++ }
++ }
++
++ DELAY(Delay_PHYRd);
++ Dat_ULONG = ReadSOC_DD( MAC_PHYBASE + 0x64 ) & 0xffff;
++ }
++ else {
++ WriteSOC_DD( MAC_PHYBASE + 0x60, MDC_Thres | MAC_PHYRd | (PHY_ADR << 16) | ((adr & 0x1f) << 21) );
++
++ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYRd ) {
++ if ( ++timeout > TIME_OUT_PHY_RW ) {
++#ifdef SLT_DOS
++ if ( !BurstEnable )
++ fprintf( fp_log, "[PHY-Read] Time out: %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0x60 ) );
++#endif
++ FindErr( Err_PHY_TimeOut );
++ break;
++ }
++ }
++
++ DELAY( Delay_PHYRd );
++ Dat_ULONG = ReadSOC_DD( MAC_PHYBASE + 0x64 ) >> 16;
++ }
++
++ if ( DbgPrn_PHYRW )
++ printf ("[Rd ]%02d: %04lx\n", adr, Dat_ULONG );
++
++ return( Dat_ULONG );
++} // End ULONG phy_read (int adr)
++
++//------------------------------------------------------------
++void phy_Read_Write (int adr, ULONG clr_mask, ULONG set_mask) {
++ if ( DbgPrn_PHYRW )
++ printf ("[RW ]%02d: clr:%04lx: set:%04lx\n", adr, clr_mask, set_mask);
++ phy_write(adr, ((phy_read(adr) & (~clr_mask)) | set_mask));
++}
++
++//------------------------------------------------------------
++void phy_out ( int adr ) {
++ printf ("%02d: %04lx\n", adr, phy_read(adr));
++}
++
++//------------------------------------------------------------
++//void phy_outchg ( int adr ) {
++// ULONG PHY_valold = 0;
++// ULONG PHY_val;
++//
++// while (1) {
++// PHY_val = phy_read(adr);
++// if (PHY_valold != PHY_val) {
++// printf ("%02d: %04lx\n", adr, PHY_val);
++// PHY_valold = PHY_val;
++// }
++// }
++//}
++
++//------------------------------------------------------------
++void phy_dump (char *name) {
++ int index;
++
++ printf ("[%s][%d]----------------\n", name, PHY_ADR);
++ for (index = 0; index < 32; index++) {
++ printf ("%02d: %04lx ", index, phy_read(index));
++
++ if ((index % 8) == 7)
++ printf ("\n");
++ }
++}
++
++//------------------------------------------------------------
++void phy_id (BYTE option) {
++
++ ULONG reg_adr;
++ CHAR PHY_ADR_org;
++ FILE_VAR
++
++ GET_OBJ( option )
++
++ PHY_ADR_org = PHY_ADR;
++ for (PHY_ADR = 0; PHY_ADR < 32; PHY_ADR++) {
++
++ PRINT(OUT_OBJ "[%02d] ", PHY_ADR);
++
++ for (reg_adr = 2; reg_adr <= 3; reg_adr++)
++ PRINT(OUT_OBJ "%ld:%04lx ", reg_adr, phy_read(reg_adr));
++
++ if ((PHY_ADR % 4) == 3)
++ PRINT(OUT_OBJ "\n");
++ }
++ PHY_ADR = PHY_ADR_org;
++}
++
++
++//------------------------------------------------------------
++void phy_delay (int dt) {
++ DELAY( dt );
++}
++
++//------------------------------------------------------------
++// PHY IC
++//------------------------------------------------------------
++void phy_basic_setting (int loop_phy) {
++ phy_Read_Write(0, 0x7140, PHY_00h); //clr set
++ if ( DbgPrn_PHYRW )
++ printf ("[Set]00: %04lx\n", phy_read( PHY_REG_BMCR ));
++}
++
++//------------------------------------------------------------
++void phy_Wait_Reset_Done (void) {
++ int timeout = 0;
++
++ while ( phy_read( PHY_REG_BMCR ) & 0x8000 ) {
++ if (DbgPrn_PHYRW)
++ printf ("00: %04lx\n", phy_read( PHY_REG_BMCR ));
++
++ if (++timeout > TIME_OUT_PHY_Rst) {
++#ifdef SLT_DOS
++ if (!BurstEnable) fprintf(fp_log, "[PHY-Reset] Time out: %08lx\n", ReadSOC_DD(MAC_PHYBASE+0x60));
++#endif
++ FindErr(Err_PHY_TimeOut);
++ break;
++ }
++ }//wait Rst Done
++
++ if (DbgPrn_PHYRW) printf ("[Clr]00: %04lx\n", phy_read( PHY_REG_BMCR ));
++ DELAY(Delay_PHYRst);
++}
++
++//------------------------------------------------------------
++void phy_Reset (int loop_phy) {
++ phy_basic_setting(loop_phy);
++
++ phy_Read_Write(0, 0x0000, 0x8000 | PHY_00h);//clr set//Rst PHY
++ phy_Wait_Reset_Done();
++
++ phy_basic_setting(loop_phy);
++ DELAY(Delay_PHYRst);
++}
++
++//------------------------------------------------------------
++void recov_phy_marvell (int loop_phy) {//88E1111
++ if ( BurstEnable ) {
++ }
++ else if ( loop_phy ) {
++ }
++ else {
++ if (GSpeed_sel[0]) {
++ phy_write(9, PHY_09h);
++
++ phy_Reset(loop_phy);
++
++ phy_write(29, 0x0007);
++ phy_Read_Write(30, 0x0008, 0x0000);//clr set
++ phy_write(29, 0x0010);
++ phy_Read_Write(30, 0x0002, 0x0000);//clr set
++ phy_write(29, 0x0012);
++ phy_Read_Write(30, 0x0001, 0x0000);//clr set
++
++ phy_write(18, PHY_12h);
++ }
++ }
++}
++
++//------------------------------------------------------------
++void phy_marvell (int loop_phy) {//88E1111
++ int Retry;
++
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)[Marvell] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ if ( BurstEnable ) {
++ phy_Reset(loop_phy);
++ }
++ else if ( loop_phy ) {
++ phy_Reset(loop_phy);
++ }
++ else {
++ if ( GSpeed_sel[0] ) {
++ PHY_09h = phy_read( PHY_GBCR );
++ PHY_12h = phy_read( PHY_INER );
++ phy_write ( 18, 0x0000 );
++ phy_Read_Write( 9, 0x0000, 0x1800 );//clr set
++ }
++
++ phy_Reset(loop_phy);
++
++ if (GSpeed_sel[0]) {
++ phy_write ( 29, 0x0007 );
++ phy_Read_Write( 30, 0x0000, 0x0008 );//clr set
++ phy_write ( 29, 0x0010 );
++ phy_Read_Write( 30, 0x0000, 0x0002 );//clr set
++ phy_write ( 29, 0x0012 );
++ phy_Read_Write( 30, 0x0000, 0x0001 );//clr set
++ }
++ }
++
++ Retry = 0;
++ do {
++ PHY_11h = phy_read( PHY_SR );
++ } while ( !( ( PHY_11h & 0x0400 ) | loop_phy | ( Retry++ > 20 ) ) );
++}
++
++//------------------------------------------------------------
++void recov_phy_marvell0 (int loop_phy) {//88E1310
++ if (BurstEnable) {
++ } else if (loop_phy) {
++ } else {
++ if (GSpeed_sel[0]) {
++ phy_write(22, 0x0006);
++ phy_Read_Write(16, 0x0020, 0x0000);//clr set
++ phy_write(22, 0x0000);
++ }
++ }
++}
++
++//------------------------------------------------------------
++void phy_marvell0 (int loop_phy) {//88E1310
++ int Retry;
++
++ if (DbgPrn_PHYName)
++ printf ("--->(%04lx %04lx)[Marvell] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ phy_write( 22, 0x0002 );
++
++ PHY_15h = phy_read(21);
++ if (PHY_15h & 0x0030) {
++ printf ("\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15_2:%04lx]\n\n", PHY_15h);
++#ifdef SLT_DOS
++ if ( IOTiming )
++ fprintf (fp_io, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15_2:%04lx]\n\n", PHY_15h);
++ if ( !BurstEnable)
++ fprintf (fp_log, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15_2:%04lx]\n\n", PHY_15h);
++#endif
++// phy_Read_Write(21, 0x0030, 0x0000);//clr set//[5]Rx Dly, [4]Tx Dly
++ phy_write(21, PHY_15h & 0xffcf); // Set [5]Rx Dly, [4]Tx Dly to 0
++ }
++ phy_write(22, 0x0000);
++
++ if ( BurstEnable ) {
++ phy_Reset(loop_phy);
++ }
++ else if ( loop_phy ) {
++ phy_write( 22, 0x0002 );
++
++ if ( GSpeed_sel[0] ) {
++ phy_Read_Write( 21, 0x6040, 0x0040 );//clr set
++ }
++ else if ( GSpeed_sel[1] ) {
++ phy_Read_Write( 21, 0x6040, 0x2000 );//clr set
++ }
++ else {
++ phy_Read_Write( 21, 0x6040, 0x0000 );//clr set
++ }
++ phy_write( 22, 0x0000 );
++ phy_Reset( loop_phy );
++ }
++ else {
++ if ( GSpeed_sel[0] ) {
++ phy_write( 22, 0x0006 );
++ phy_Read_Write( 16, 0x0000, 0x0020 );//clr set
++ phy_write( 22, 0x0000 );
++ }
++
++ phy_Reset(loop_phy);
++ }
++
++ Retry = 0;
++ do {
++ PHY_11h = phy_read( PHY_SR );
++ } while (!((PHY_11h & 0x0400) | loop_phy | (Retry++ > 20)));
++}
++
++//------------------------------------------------------------
++void recov_phy_marvell1 (int loop_phy) {//88E6176
++ CHAR PHY_ADR_org;
++
++ PHY_ADR_org = PHY_ADR;
++ for ( PHY_ADR = 16; PHY_ADR <= 22; PHY_ADR++ ) {
++ if ( BurstEnable ) {
++ }
++ else {
++ phy_write(6, PHY_06hA[PHY_ADR-16]);//06h[5]P5 loopback, 06h[6]P6 loopback
++ }
++ }
++ for ( PHY_ADR = 21; PHY_ADR <= 22; PHY_ADR++ ) {
++ phy_write(1, 0x3); //01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
++ }
++ PHY_ADR = PHY_ADR_org;
++}
++
++//------------------------------------------------------------
++void phy_marvell1 (int loop_phy) {//88E6176
++// ULONG PHY_01h;
++ CHAR PHY_ADR_org;
++
++ if (DbgPrn_PHYName)
++ printf ("--->(%04lx %04lx)[Marvell] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ //The 88E6176 is switch with 7 Port(P0~P6) and the PHYAdr will be fixed at 0x10~0x16, and only P5/P6 can be connected to the MAC.
++ //Therefor, the 88E6176 only can run the internal loopback.
++ PHY_ADR_org = PHY_ADR;
++ for ( PHY_ADR = 16; PHY_ADR <= 20; PHY_ADR++ ) {
++ if ( BurstEnable ) {
++ }
++ else {
++ PHY_06hA[PHY_ADR-16] = phy_read( PHY_ANER );
++ phy_write(6, 0x00);//06h[5]P5 loopback, 06h[6]P6 loopback
++ }
++ }
++
++ for ( PHY_ADR = 21; PHY_ADR <= 22; PHY_ADR++ ) {
++// PHY_01h = phy_read( PHY_REG_BMSR );
++// if (GSpeed_sel[0]) phy_write(1, (PHY_01h & 0xfffc) | 0x2);//[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
++// else if (GSpeed_sel[1]) phy_write(1, (PHY_01h & 0xfffc) | 0x1);//[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
++// else phy_write(1, (PHY_01h & 0xfffc) );//[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
++ if (GSpeed_sel[0]) phy_write(1, 0x2);//01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
++ else if (GSpeed_sel[1]) phy_write(1, 0x1);//01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
++ else phy_write(1, 0x0);//01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
++
++ if (BurstEnable) {
++ }
++ else {
++ PHY_06hA[PHY_ADR-16] = phy_read( PHY_ANER );
++ if (PHY_ADR == 21) phy_write(6, 0x20);//06h[5]P5 loopback, 06h[6]P6 loopback
++ else phy_write(6, 0x40);//06h[5]P5 loopback, 06h[6]P6 loopback
++ }
++ }
++ PHY_ADR = PHY_ADR_org;
++}
++
++//------------------------------------------------------------
++void recov_phy_marvell2 (int loop_phy) {//88E1512
++ if (BurstEnable) {
++ }
++ else if (loop_phy) {
++ }
++ else {
++ if (GSpeed_sel[0]) {
++ phy_write(22, 0x0006);
++ phy_Read_Write(18, 0x0008, 0x0000);//clr set
++ phy_write(22, 0x0000);
++ }
++ }
++}
++
++//------------------------------------------------------------
++void phy_marvell2 (int loop_phy) {//88E1512
++ int Retry = 0;
++ ULONG temp_reg;
++
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)[Marvell] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ phy_write(22, 0x0002);
++ PHY_15h = phy_read(21);
++
++ if ( PHY_15h & 0x0030 ) {
++ printf ("\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15h_2:%04lx]\n\n", PHY_15h);
++#ifdef SLT_DOS
++ if (IOTiming ) fprintf (fp_io, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15h_2:%04lx]\n\n", PHY_15h);
++ if (!BurstEnable) fprintf (fp_log, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15h_2:%04lx]\n\n", PHY_15h);
++#endif
++ // phy_Read_Write(21, 0x0030, 0x0000);//clr set//[5]Rx Dly, [4]Tx Dly
++// phy_write(21, PHY_15h & 0xffcf);
++ }
++ phy_write(22, 0x0000);
++
++ if ( BurstEnable ) {
++ phy_Reset(loop_phy);
++ }
++ else if (loop_phy) {
++ // Internal loopback funciton only support in copper mode
++ // switch page 18
++ phy_write(22, 0x0012);
++ // Change mode to Copper mode
++ phy_write(20, 0x8210);
++ // do software reset
++ do {
++ temp_reg = phy_read( 20 );
++ } while ( ( (temp_reg & 0x8000) == 0x8000 ) & (Retry++ < 20) );
++
++ // switch page 2
++ phy_write(22, 0x0002);
++ if (GSpeed_sel[0]) {
++ phy_Read_Write(21, 0x2040, 0x0040);//clr set
++ }
++ else if (GSpeed_sel[1]) {
++ phy_Read_Write(21, 0x2040, 0x2000);//clr set
++ }
++ else {
++ phy_Read_Write(21, 0x2040, 0x0000);//clr set
++ }
++ phy_write(22, 0x0000);
++
++ phy_Reset(loop_phy);
++ }
++ else {
++ if (GSpeed_sel[0]) {
++ phy_write(22, 0x0006);
++ phy_Read_Write(18, 0x0000, 0x0008);//clr set
++ phy_write(22, 0x0000);
++ }
++
++ phy_Reset(loop_phy);
++ }
++
++ Retry = 0;
++ do {
++ PHY_11h = phy_read( PHY_SR );
++ } while (!((PHY_11h & 0x0400) | loop_phy | (Retry++ > 20)));
++}
++
++//------------------------------------------------------------
++void phy_broadcom (int loop_phy) {//BCM5221
++ if (DbgPrn_PHYName)
++ printf ("--->(%04lx %04lx)[Broadcom] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ phy_Reset(loop_phy);
++
++ if (IEEETesting) {
++ if (IOTimingBund_arg == 0) {
++ phy_write(25, 0x1f01);//Force MDI //Measuring from channel A
++ }
++ else {
++ phy_Read_Write(24, 0x0000, 0x4000);//clr set//Force Link
++// phy_write( 0, PHY_00h);
++// phy_write(30, 0x1000);
++ }
++ }
++}
++
++//------------------------------------------------------------
++void recov_phy_broadcom0 (int loop_phy) {//BCM54612
++
++ // Need to do it for AST2400
++ phy_write(0x1C, 0x8C00); // Disable GTXCLK Clock Delay Enable
++ phy_write(0x18, 0xF0E7); // Disable RGMII RXD to RXC Skew
++
++ if (BurstEnable) {
++ }
++ else if (loop_phy) {
++ phy_write( 0, PHY_00h);
++ }
++ else {
++ phy_write(0x00, PHY_00h);
++ phy_write(0x09, PHY_09h);
++ phy_write(0x18, PHY_18h);
++ }
++}
++
++//------------------------------------------------------------
++void phy_broadcom0 (int loop_phy) {//BCM54612
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)[Broadcom] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ // Need to do it for AST2400
++ phy_write(0x1C, 0x8C00); // Disable GTXCLK Clock Delay Enable
++ phy_write(0x18, 0xF0E7); // Disable RGMII RXD to RXC Skew
++
++ // Backup org value
++ // read reg 18H, Page 103, BCM54612EB1KMLG_Spec.pdf
++ phy_write(0x18, 0x7007);
++ PHY_18h = phy_read(0x18);
++
++ PHY_00h = phy_read( PHY_REG_BMCR );
++ PHY_09h = phy_read( PHY_GBCR );
++
++ if ( BurstEnable ) {
++ phy_basic_setting(loop_phy);
++ }
++ else if (loop_phy) {
++ phy_basic_setting(loop_phy);
++
++ // Enable Internal Loopback mode
++ // Page 58, BCM54612EB1KMLG_Spec.pdf
++ phy_write(0x0, 0x5140);
++ DELAY(Delay_PHYRst);
++ /* Only 1G Test is PASS, 100M and 10M is false @20130619 */
++
++// Waiting for BCM FAE's response
++// if (GSpeed_sel[0]) {
++// // Speed 1G
++// // Enable Internal Loopback mode
++// // Page 58, BCM54612EB1KMLG_Spec.pdf
++// phy_write(0x0, 0x5140);
++// }
++// else if (GSpeed_sel[1]) {
++// // Speed 100M
++// // Enable Internal Loopback mode
++// // Page 58, BCM54612EB1KMLG_Spec.pdf
++// phy_write(0x0, 0x7100);
++// phy_write(0x1E, 0x1000);
++// }
++// else if (GSpeed_sel[2]) {
++// // Speed 10M
++// // Enable Internal Loopback mode
++// // Page 58, BCM54612EB1KMLG_Spec.pdf
++// phy_write(0x0, 0x5100);
++// phy_write(0x1E, 0x1000);
++// }
++//
++// DELAY(Delay_PHYRst);
++ }
++ else {
++
++ if (GSpeed_sel[0]) {
++ // Page 60, BCM54612EB1KMLG_Spec.pdf
++ // need to insert loopback plug
++ phy_write( 9, 0x1800);
++ phy_write( 0, 0x0140);
++ phy_write( 0x18, 0x8400); // Enable Transmit test mode
++ } else if (GSpeed_sel[1]) {
++ // Page 60, BCM54612EB1KMLG_Spec.pdf
++ // need to insert loopback plug
++ phy_write( 0, 0x2100);
++ phy_write( 0x18, 0x8400); // Enable Transmit test mode
++ } else {
++ // Page 60, BCM54612EB1KMLG_Spec.pdf
++ // need to insert loopback plug
++ phy_write( 0, 0x0100);
++ phy_write( 0x18, 0x8400); // Enable Transmit test mode
++ }
++ }
++}
++
++//------------------------------------------------------------
++void phy_realtek (int loop_phy) {//RTL8201N
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ phy_Reset(loop_phy);
++}
++
++//------------------------------------------------------------
++//internal loop 100M: Don't support
++//internal loop 10M : no loopback stub
++void phy_realtek0 (int loop_phy) {//RTL8201E
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ phy_Reset(loop_phy);
++
++// phy_Read_Write(25, 0x2800, 0x0000);//clr set
++// printf("Enable phy output RMII clock\n");
++ if (IEEETesting) {
++ phy_write(31, 0x0001);
++ if (IOTimingBund_arg == 0) {
++ phy_write(25, 0x1f01);//Force MDI //Measuring from channel A
++ }
++ else {
++ phy_write(25, 0x1f00);//Force MDIX //Measuring from channel B
++ }
++ phy_write(31, 0x0000);
++ }
++}
++
++//------------------------------------------------------------
++void recov_phy_realtek1 (int loop_phy) {//RTL8211D
++ if ( BurstEnable ) {
++ if ( IEEETesting ) {
++ if ( GSpeed_sel[0] ) {
++ if (IOTimingBund_arg == 0) {
++ //Test Mode 1
++ phy_write( 31, 0x0002 );
++ phy_write( 2, 0xc203 );
++ phy_write( 31, 0x0000 );
++ phy_write( 9, 0x0000 );
++ }
++ else {
++ //Test Mode 4
++ phy_write( 31, 0x0000 );
++ phy_write( 9, 0x0000 );
++ }
++
++ phy_write( 31, 0x0000 );
++ }
++ else if ( GSpeed_sel[1] ) {
++ phy_write( 23, 0x2100 );
++ phy_write( 16, 0x016e );
++ }
++ else {
++// phy_write( 31, 0x0006 );
++// phy_write( 0, 0x5a00 );
++// phy_write( 31, 0x0000 );
++ }
++ } // End if ( IEEETesting )
++ }
++ else if (loop_phy) {
++ if ( GSpeed_sel[0] ) {
++ phy_write( 31, 0x0000 ); // new in Rev. 1.6
++ phy_write( 0, 0x1140 ); // new in Rev. 1.6
++ phy_write( 20, 0x8040 ); // new in Rev. 1.6
++ }
++ }
++ else {
++ if ( GSpeed_sel[0] ) {
++ phy_write( 31, 0x0001 );
++ phy_write( 3, 0xdf41 );
++ phy_write( 2, 0xdf20 );
++ phy_write( 1, 0x0140 );
++ phy_write( 0, 0x00bb );
++ phy_write( 4, 0xb800 );
++ phy_write( 4, 0xb000 );
++
++ phy_write( 31, 0x0000 );
++// phy_write( 26, 0x0020 ); // Rev. 1.2
++ phy_write( 26, 0x0040 ); // new in Rev. 1.6
++ phy_write( 0, 0x1140 );
++// phy_write( 21, 0x0006 ); // Rev. 1.2
++ phy_write( 21, 0x1006 ); // new in Rev. 1.6
++ phy_write( 23, 0x2100 );
++// } else if ( GSpeed_sel[1] ) {//option
++// phy_write( 31, 0x0000 );
++// phy_write( 9, 0x0200 );
++// phy_write( 0, 0x1200 );
++// } else if ( GSpeed_sel[2] ) {//option
++// phy_write( 31, 0x0000 );
++// phy_write( 9, 0x0200 );
++// phy_write( 4, 0x05e1 );
++// phy_write( 0, 0x1200 );
++ }
++ } // End if ( BurstEnable )
++} // End void recov_phy_realtek1 (int loop_phy)
++
++//------------------------------------------------------------
++//internal loop 1G : no loopback stub
++//internal loop 100M: no loopback stub
++//internal loop 10M : no loopback stub
++void phy_realtek1 (int loop_phy) {//RTL8211D
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ if ( BurstEnable ) {
++ if ( IEEETesting ) {
++ if ( GSpeed_sel[0] ) {
++ if (IOTimingBund_arg == 0) {
++ //Test Mode 1
++ phy_write( 31, 0x0002 );
++ phy_write( 2, 0xc22b );
++ phy_write( 31, 0x0000 );
++ phy_write( 9, 0x2000 );
++ }
++ else {
++ //Test Mode 4
++ phy_write( 31, 0x0000 );
++ phy_write( 9, 0x8000 );
++ }
++ phy_write( 31, 0x0000 );
++ }
++ else if ( GSpeed_sel[1] ) {
++ if ( IOTimingBund_arg == 0 ) {
++ //From Channel A
++ phy_write( 23, 0xa102 );
++ phy_write( 16, 0x01ae );//MDI
++ }
++ else {
++ //From Channel B
++ phy_Read_Write( 17, 0x0008, 0x0000 ); // clr set
++ phy_write( 23, 0xa102 ); // MDI
++ phy_write( 16, 0x010e );
++ }
++ } else {
++// if ( IOTimingBund_arg == 0 ) {//Pseudo-random pattern
++// phy_write( 31, 0x0006 );
++// phy_write( 0, 0x5a21 );
++// phy_write( 31, 0x0000 );
++// }
++// else if ( IOTimingBund_arg == 1 ) {//ˇ§FFˇ¨ pattern
++// phy_write( 31, 0x0006 );
++// phy_write( 2, 0x05ee );
++// phy_write( 0, 0xff21 );
++// phy_write( 31, 0x0000 );
++// } else {//ˇ§00ˇ¨ pattern
++// phy_write( 31, 0x0006 );
++// phy_write( 2, 0x05ee );
++// phy_write( 0, 0x0021 );
++// phy_write( 31, 0x0000 );
++// }
++ }
++ }
++ else {
++ phy_Reset(loop_phy);
++ }
++ }
++ else if ( loop_phy ) {
++ phy_Reset(loop_phy);
++
++ if ( GSpeed_sel[0] ) {
++ phy_write(20, 0x0042);//new in Rev. 1.6
++ }
++ }
++ else {
++ if ( GSpeed_sel[0] ) {
++ phy_write( 31, 0x0001 );
++ phy_write( 3, 0xff41 );
++ phy_write( 2, 0xd720 );
++ phy_write( 1, 0x0140 );
++ phy_write( 0, 0x00bb );
++ phy_write( 4, 0xb800 );
++ phy_write( 4, 0xb000 );
++
++ phy_write( 31, 0x0007 );
++ phy_write( 30, 0x0040 );
++ phy_write( 24, 0x0008 );
++
++ phy_write( 31, 0x0000 );
++ phy_write( 9, 0x0300 );
++ phy_write( 26, 0x0020 );
++ phy_write( 0, 0x0140 );
++ phy_write( 23, 0xa101 );
++ phy_write( 21, 0x0200 );
++ phy_write( 23, 0xa121 );
++ phy_write( 23, 0xa161 );
++ phy_write( 0, 0x8000 );
++ phy_Wait_Reset_Done();
++ phy_delay(200); // new in Rev. 1.6
++// }
++// else if ( GSpeed_sel[1] ) {//option
++// phy_write( 31, 0x0000 );
++// phy_write( 9, 0x0000 );
++// phy_write( 4, 0x0061 );
++// phy_write( 0, 0x1200 );
++// phy_delay(5000);
++// }
++// else if (GSpeed_sel[2]) {//option
++// phy_write( 31, 0x0000 );
++// phy_write( 9, 0x0000 );
++// phy_write( 4, 0x05e1 );
++// phy_write( 0, 0x1200 );
++// phy_delay(5000);
++ }
++ else {
++ phy_Reset(loop_phy);
++ }
++ }
++} // End void phy_realtek1 (int loop_phy)
++
++//------------------------------------------------------------
++void recov_phy_realtek2 (int loop_phy) {//RTL8211E
++ if ( BurstEnable ) {
++ if ( IEEETesting ) {
++ phy_write( 31, 0x0005 );
++ phy_write( 5, 0x8b86 );
++ phy_write( 6, 0xe201 );
++ phy_write( 31, 0x0007 );
++ phy_write( 30, 0x0020 );
++ phy_write( 21, 0x1108 );
++ phy_write( 31, 0x0000 );
++
++ if ( GSpeed_sel[0] ) {
++ phy_write( 31, 0x0000 );
++ phy_write( 9, 0x0000 );
++ }
++ else if ( GSpeed_sel[1] ) {
++ phy_write( 31, 0x0007 );
++ phy_write( 30, 0x002f );
++ phy_write( 23, 0xd88f );
++ phy_write( 30, 0x002d );
++ phy_write( 24, 0xf050 );
++ phy_write( 31, 0x0000 );
++ phy_write( 16, 0x006e );
++ }
++ else {
++ }
++ }
++ else {
++ }
++ }
++ else if (loop_phy) {
++ }
++ else {
++ if (GSpeed_sel[0]) {
++ //Rev 1.5 //not stable
++// phy_write( 31, 0x0000 );
++// phy_write( 0, 0x8000 );
++// phy_Wait_Reset_Done();
++// phy_delay(30);
++// phy_write( 23, 0x2160 );
++// phy_write( 31, 0x0007 );
++// phy_write( 30, 0x0040 );
++// phy_write( 24, 0x0004 );
++// phy_write( 24, 0x1a24 );
++// phy_write( 25, 0xfd00 );
++// phy_write( 24, 0x0000 );
++// phy_write( 31, 0x0000 );
++// phy_write( 0, 0x1140 );
++// phy_write( 26, 0x0040 );
++// phy_write( 31, 0x0007 );
++// phy_write( 30, 0x002f );
++// phy_write( 23, 0xd88f );
++// phy_write( 30, 0x0023 );
++// phy_write( 22, 0x0300 );
++// phy_write( 31, 0x0000 );
++// phy_write( 21, 0x1006 );
++// phy_write( 23, 0x2100 );
++/**/
++ //Rev 1.6
++ phy_write( 31, 0x0000 );
++ phy_write( 0, 0x8000 );
++ phy_Wait_Reset_Done();
++ phy_delay(30);
++ phy_write( 31, 0x0007 );
++ phy_write( 30, 0x0042 );
++ phy_write( 21, 0x0500 );
++ phy_write( 31, 0x0000 );
++ phy_write( 0, 0x1140 );
++ phy_write( 26, 0x0040 );
++ phy_write( 31, 0x0007 );
++ phy_write( 30, 0x002f );
++ phy_write( 23, 0xd88f );
++ phy_write( 30, 0x0023 );
++ phy_write( 22, 0x0300 );
++ phy_write( 31, 0x0000 );
++ phy_write( 21, 0x1006 );
++ phy_write( 23, 0x2100 );
++/**/
++// } else if (GSpeed_sel[1]) {//option
++// phy_write( 31, 0x0000 );
++// phy_write( 9, 0x0200 );
++// phy_write( 0, 0x1200 );
++// } else if (GSpeed_sel[2]) {//option
++// phy_write( 31, 0x0000 );
++// phy_write( 9, 0x0200 );
++// phy_write( 4, 0x05e1 );
++// phy_write( 0, 0x1200 );
++ }
++ }
++} // End void recov_phy_realtek2 (int loop_phy)
++
++//------------------------------------------------------------
++//internal loop 1G : no loopback stub
++//internal loop 100M: no loopback stub
++//internal loop 10M : no loopback stub
++void phy_realtek2 (int loop_phy) {//RTL8211E
++
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ phy_Read_Write( 0, 0x0000, 0x8000 | PHY_00h ); // clr set // Rst PHY
++ phy_Wait_Reset_Done();
++ phy_delay(30);
++
++ if ( BurstEnable ) {
++ if ( IEEETesting ) {
++ phy_write( 31, 0x0005 );
++ phy_write( 5, 0x8b86 );
++ phy_write( 6, 0xe200 );
++ phy_write( 31, 0x0007 );
++ phy_write( 30, 0x0020 );
++ phy_write( 21, 0x0108 );
++ phy_write( 31, 0x0000 );
++
++ if ( GSpeed_sel[0] ) {
++ phy_write( 31, 0x0000 );
++
++ if ( IOTimingBund_arg == 0 ) {
++ phy_write( 9, 0x2000);//Test Mode 1
++ }
++ else {
++ phy_write( 9, 0x8000);//Test Mode 4
++ }
++ }
++ else if ( GSpeed_sel[1] ) {
++ phy_write( 31, 0x0007 );
++ phy_write( 30, 0x002f );
++ phy_write( 23, 0xd818 );
++ phy_write( 30, 0x002d );
++ phy_write( 24, 0xf060 );
++ phy_write( 31, 0x0000 );
++
++ if ( IOTimingBund_arg == 0 ) {
++ phy_write(16, 0x00ae);//From Channel A
++ }
++ else {
++ phy_write(16, 0x008e);//From Channel B
++ }
++ }
++ else {
++ }
++ }
++ else {
++ phy_basic_setting(loop_phy);
++ phy_delay(30);
++ }
++ }
++ else if (loop_phy) {
++ phy_basic_setting(loop_phy);
++
++ phy_Read_Write(0, 0x0000, 0x8000 | PHY_00h);//clr set//Rst PHY
++ phy_Wait_Reset_Done();
++ phy_delay(30);
++
++ phy_basic_setting(loop_phy);
++ phy_delay(30);
++ }
++ else {
++ if ( GSpeed_sel[0] ) {
++ //Rev 1.5 //not stable
++// phy_write( 23, 0x2160 );
++// phy_write( 31, 0x0007 );
++// phy_write( 30, 0x0040 );
++// phy_write( 24, 0x0004 );
++// phy_write( 24, 0x1a24 );
++// phy_write( 25, 0x7d00 );
++// phy_write( 31, 0x0000 );
++// phy_write( 23, 0x2100 );
++// phy_write( 31, 0x0007 );
++// phy_write( 30, 0x0040 );
++// phy_write( 24, 0x0000 );
++// phy_write( 30, 0x0023 );
++// phy_write( 22, 0x0006 );
++// phy_write( 31, 0x0000 );
++// phy_write( 0, 0x0140 );
++// phy_write( 26, 0x0060 );
++// phy_write( 31, 0x0007 );
++// phy_write( 30, 0x002f );
++// phy_write( 23, 0xd820 );
++// phy_write( 31, 0x0000 );
++// phy_write( 21, 0x0206 );
++// phy_write( 23, 0x2120 );
++// phy_write( 23, 0x2160 );
++/**/
++ //Rev 1.6
++ phy_write( 31, 0x0007 );
++ phy_write( 30, 0x0042 );
++ phy_write( 21, 0x2500 );
++ phy_write( 30, 0x0023 );
++ phy_write( 22, 0x0006 );
++ phy_write( 31, 0x0000 );
++ phy_write( 0, 0x0140 );
++ phy_write( 26, 0x0060 );
++ phy_write( 31, 0x0007 );
++ phy_write( 30, 0x002f );
++ phy_write( 23, 0xd820 );
++ phy_write( 31, 0x0000 );
++ phy_write( 21, 0x0206 );
++ phy_write( 23, 0x2120 );
++ phy_write( 23, 0x2160 );
++ phy_delay(300);
++/**/
++// }
++// else if ( GSpeed_sel[1] ) {//option
++// phy_write( 31, 0x0000 );
++// phy_write( 9, 0x0000 );
++// phy_write( 4, 0x0061 );
++// phy_write( 0, 0x1200 );
++// phy_delay(5000);
++// }
++// else if ( GSpeed_sel[2] ) {//option
++// phy_write( 31, 0x0000 );
++// phy_write( 9, 0x0000 );
++// phy_write( 4, 0x05e1 );
++// phy_write( 0, 0x1200 );
++// phy_delay(5000);
++ }
++ else {
++ phy_basic_setting(loop_phy);
++ phy_delay(150);
++ }
++ }
++} // End void phy_realtek2 (int loop_phy)
++
++//------------------------------------------------------------
++void recov_phy_realtek3 (int loop_phy) {//RTL8211C
++ if ( BurstEnable ) {
++ if ( IEEETesting ) {
++ if ( GSpeed_sel[0] ) {
++ phy_write( 9, 0x0000 );
++ }
++ else if ( GSpeed_sel[1] ) {
++ phy_write( 17, PHY_11h );
++ phy_write( 14, 0x0000 );
++ phy_write( 16, 0x00a0 );
++ }
++ else {
++// phy_write( 31, 0x0006 );
++// phy_write( 0, 0x5a00 );
++// phy_write( 31, 0x0000 );
++ }
++ }
++ else {
++ }
++ }
++ else if (loop_phy) {
++ if ( GSpeed_sel[0] ) {
++ phy_write( 11, 0x0000 );
++ }
++ phy_write( 12, 0x1006 );
++ }
++ else {
++ if ( GSpeed_sel[0] ) {
++ phy_write( 31, 0x0001 );
++ phy_write( 4, 0xb000 );
++ phy_write( 3, 0xff41 );
++ phy_write( 2, 0xdf20 );
++ phy_write( 1, 0x0140 );
++ phy_write( 0, 0x00bb );
++ phy_write( 4, 0xb800 );
++ phy_write( 4, 0xb000 );
++
++ phy_write( 31, 0x0000 );
++ phy_write( 25, 0x8c00 );
++ phy_write( 26, 0x0040 );
++ phy_write( 0, 0x1140 );
++ phy_write( 14, 0x0000 );
++ phy_write( 12, 0x1006 );
++ phy_write( 23, 0x2109 );
++ }
++ }
++}
++
++//------------------------------------------------------------
++void phy_realtek3 (int loop_phy) {//RTL8211C
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ if ( BurstEnable ) {
++ if ( IEEETesting ) {
++ if ( GSpeed_sel[0] ) {
++ if ( IOTimingBund_arg == 0 ) { //Test Mode 1
++ phy_write( 9, 0x2000);
++ }
++ else if (IOTimingBund_arg == 1) {//Test Mode 2
++ phy_write( 9, 0x4000);
++ }
++ else if (IOTimingBund_arg == 2) {//Test Mode 3
++ phy_write( 9, 0x6000);
++ }
++ else { //Test Mode 4
++ phy_write( 9, 0x8000);
++ }
++ }
++ else if ( GSpeed_sel[1] ) {
++ PHY_11h = phy_read( PHY_SR );
++ phy_write( 17, PHY_11h & 0xfff7 );
++ phy_write( 14, 0x0660 );
++
++ if ( IOTimingBund_arg == 0 ) {
++ phy_write( 16, 0x00a0 );//MDI //From Channel A
++ }
++ else {
++ phy_write( 16, 0x0080 );//MDIX //From Channel B
++ }
++ }
++ else {
++// if (IOTimingBund_arg == 0) {//Pseudo-random pattern
++// phy_write( 31, 0x0006 );
++// phy_write( 0, 0x5a21 );
++// phy_write( 31, 0x0000 );
++// }
++// else if (IOTimingBund_arg == 1) {//ˇ§FFˇ¨ pattern
++// phy_write( 31, 0x0006 );
++// phy_write( 2, 0x05ee );
++// phy_write( 0, 0xff21 );
++// phy_write( 31, 0x0000 );
++// }
++// else {//ˇ§00ˇ¨ pattern
++// phy_write( 31, 0x0006 );
++// phy_write( 2, 0x05ee );
++// phy_write( 0, 0x0021 );
++// phy_write( 31, 0x0000 );
++// }
++ }
++ }
++ else {
++ phy_Reset(loop_phy);
++ }
++ }
++ else if (loop_phy) {
++ phy_write( 0, 0x9200);
++ phy_Wait_Reset_Done();
++ phy_delay(30);
++
++ phy_write( 17, 0x401c );
++ phy_write( 12, 0x0006 );
++
++ if ( GSpeed_sel[0] ) {
++ phy_write(11, 0x0002);
++ }
++ else {
++ phy_basic_setting(loop_phy);
++ }
++ }
++ else {
++ if (GSpeed_sel[0]) {
++ phy_write( 31, 0x0001 );
++ phy_write( 4, 0xb000 );
++ phy_write( 3, 0xff41 );
++ phy_write( 2, 0xd720 );
++ phy_write( 1, 0x0140 );
++ phy_write( 0, 0x00bb );
++ phy_write( 4, 0xb800 );
++ phy_write( 4, 0xb000 );
++
++ phy_write( 31, 0x0000 );
++ phy_write( 25, 0x8400 );
++ phy_write( 26, 0x0020 );
++ phy_write( 0, 0x0140 );
++ phy_write( 14, 0x0210 );
++ phy_write( 12, 0x0200 );
++ phy_write( 23, 0x2109 );
++ phy_write( 23, 0x2139 );
++ }
++ else {
++ phy_Reset(loop_phy);
++ }
++ }
++} // End void phy_realtek3 (int loop_phy)
++
++//------------------------------------------------------------
++void phy_realtek4 (int loop_phy) {//RTL8201F
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ if ( BurstEnable ) {
++ if ( IEEETesting ) {
++ phy_write( 31, 0x0004 );
++ phy_write( 16, 0x4077 );
++ phy_write( 21, 0xc5a0 );
++ phy_write( 31, 0x0000 );
++
++ if ( GSpeed_sel[1] ) {
++ phy_write( 0, 0x8000 ); // Reset PHY
++ phy_write( 24, 0x0310 ); // Disable ALDPS
++
++ if ( IOTimingBund_arg == 0 ) {
++ phy_write( 28, 0x40c2 ); //Force MDI //From Channel A (RJ45 pair 1, 2)
++ }
++ else {
++ phy_write( 28, 0x40c0 ); //Force MDIX//From Channel B (RJ45 pair 3, 6)
++ }
++ phy_write( 0, 0x2100); //Force 100M/Full Duplex)
++ }
++ } else {
++ phy_Reset(loop_phy);
++ }
++ }
++ else {
++ phy_Reset(loop_phy);
++ }
++}
++
++//------------------------------------------------------------
++void phy_smsc (int loop_phy) {//LAN8700
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)[SMSC] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ phy_Reset(loop_phy);
++}
++
++//------------------------------------------------------------
++void phy_micrel (int loop_phy) {//KSZ8041
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)[Micrel] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ phy_Reset(loop_phy);
++
++// phy_write(24, 0x0600);
++}
++
++//------------------------------------------------------------
++void phy_micrel0 (int loop_phy) {//KSZ8031/KSZ8051
++ if ( DbgPrn_PHYName ) printf ("--->(%04lx %04lx)[Micrel] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ //For KSZ8051RNL only
++ //Reg1Fh[7] = 0(default): 25MHz Mode, XI, XO(pin 9, 8) is 25MHz(crystal/oscilator).
++ //Reg1Fh[7] = 1 : 50MHz Mode, XI(pin 9) is 50MHz(oscilator).
++ PHY_1fh = phy_read(31);
++ if (PHY_1fh & 0x0080) sprintf(PHYName, "%s-50MHz Mode", PHYName);
++ else sprintf(PHYName, "%s-25MHz Mode", PHYName);
++
++ if (IEEETesting) {
++ phy_Read_Write( 0, 0x0000, 0x8000 | PHY_00h );//clr set//Rst PHY
++ phy_Wait_Reset_Done();
++
++ phy_Read_Write( 31, 0x0000, 0x2000 );//clr set//1Fh[13] = 1: Disable auto MDI/MDI-X
++ phy_basic_setting(loop_phy);
++ phy_Read_Write( 31, 0x0000, 0x0800 );//clr set//1Fh[11] = 1: Force link pass
++
++// phy_delay(2500);//2.5 sec
++ }
++ else {
++ phy_Reset(loop_phy);
++
++ //Reg16h[6] = 1 : RMII B-to-B override
++ //Reg16h[1] = 1(default): RMII override
++ phy_Read_Write( 22, 0x0000, 0x0042 );//clr set
++ }
++
++ if ( PHY_1fh & 0x0080 )
++ phy_Read_Write( 31, 0x0000, 0x0080 );//clr set//Reset PHY will clear Reg1Fh[7]
++}
++
++//------------------------------------------------------------
++void recov_phy_vitesse (int loop_phy) {//VSC8601
++ if ( BurstEnable ) {
++// if (IEEETesting) {
++// } else {
++// }
++ }
++ else if ( loop_phy ) {
++ }
++ else {
++ if ( GSpeed_sel[0] ) {
++ phy_write( 24, PHY_18h );
++ phy_write( 18, PHY_12h );
++ }
++ }
++}
++
++//------------------------------------------------------------
++void phy_vitesse (int loop_phy) {//VSC8601
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)[VITESSE] %s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ if ( BurstEnable ) {
++ if ( IEEETesting ) {
++ phy_Reset(loop_phy);
++ }
++ else {
++ phy_Reset(loop_phy);
++ }
++ }
++ else if ( loop_phy ) {
++ phy_Reset(loop_phy);
++ }
++ else {
++ if ( GSpeed_sel[0] ) {
++ PHY_18h = phy_read( 24 );
++ PHY_12h = phy_read( PHY_INER );
++
++ phy_Reset(loop_phy);
++
++ phy_write( 24, PHY_18h | 0x0001 );
++ phy_write( 18, PHY_12h | 0x0020 );
++ }
++ else {
++ phy_Reset(loop_phy);
++ }
++ }
++}
++
++//------------------------------------------------------------
++void phy_default (int loop_phy) {
++ if ( DbgPrn_PHYName )
++ printf ("--->(%04lx %04lx)%s\n", PHY_ID2, PHY_ID3, PHYName);
++
++ phy_Reset(loop_phy);
++}
++
++//------------------------------------------------------------
++// PHY Init
++//------------------------------------------------------------
++BOOLEAN find_phyadr (void) {
++ ULONG PHY_val;
++ BOOLEAN ret = FALSE;
++
++ #ifdef DbgPrn_FuncHeader
++ printf ("find_phyadr\n");
++ Debug_delay();
++ #endif
++
++ do {
++ // Check current PHY address by user setting
++ PHY_val = phy_read( PHY_REG_ID_1 );
++ if ( PHY_IS_VALID(PHY_val) ) {
++ ret = TRUE;
++ break;
++ }
++
++ if ( Enable_SkipChkPHY ) {
++ PHY_val = phy_read( PHY_REG_BMCR );
++
++ if ((PHY_val & 0x8000) & Enable_InitPHY) {
++ // PHY is reseting and need to inital PHY
++ #ifndef Enable_SearchPHYID
++ break;
++ #endif
++ }
++ else {
++ ret = TRUE;
++ break;
++ }
++ }
++
++ #ifdef Enable_SearchPHYID
++ // Scan PHY address from 0 to 31
++ printf("Search PHY address\n");
++ for ( PHY_ADR = 0; PHY_ADR < 32; PHY_ADR++ ) {
++ PHY_val = phy_read( PHY_REG_ID_1 );
++ if ( PHY_IS_VALID(PHY_val) ) {
++ ret = TRUE;
++ break;
++ }
++ }
++ // Don't find PHY address
++ PHY_ADR = PHY_ADR_arg;
++ #endif
++ } while ( 0 );
++
++ if ( ret == TRUE ) {
++ if ( PHY_ADR_arg != PHY_ADR ) {
++
++ if ( !BurstEnable )
++ phy_id( FP_LOG );
++
++ phy_id( STD_OUT );
++ }
++ }
++ else {
++
++ if ( !BurstEnable )
++ phy_id( FP_LOG );
++
++ phy_id( STD_OUT );
++ FindErr( Err_PHY_Type );
++ }
++
++ return ret;
++} // End BOOLEAN find_phyadr (void)
++
++//------------------------------------------------------------
++char phy_chk (ULONG id2, ULONG id3, ULONG id3_mask) {
++ if ((PHY_ID2 == id2) && ((PHY_ID3 & id3_mask) == (id3 & id3_mask)))
++ return(1);
++ else
++ return(0);
++}
++
++//------------------------------------------------------------
++void phy_set00h (int loop_phy) {
++ #ifdef DbgPrn_FuncHeader
++ printf ("phy_set00h\n");
++ Debug_delay();
++ #endif
++
++ if (BurstEnable) {
++ if (IEEETesting) {
++ if (GSpeed_sel[0]) PHY_00h = 0x0140;
++ else if (GSpeed_sel[1]) PHY_00h = 0x2100;
++ else PHY_00h = 0x0100;
++ }
++ else {
++ if (GSpeed_sel[0]) PHY_00h = 0x1140;
++ else if (GSpeed_sel[1]) PHY_00h = 0x3100;
++ else PHY_00h = 0x1100;
++ }
++ }
++ else if (loop_phy) {
++ if (GSpeed_sel[0]) PHY_00h = 0x4140;
++ else if (GSpeed_sel[1]) PHY_00h = 0x6100;
++ else PHY_00h = 0x4100;
++ }
++ else {
++ if (GSpeed_sel[0]) PHY_00h = 0x0140;
++ else if (GSpeed_sel[1]) PHY_00h = 0x2100;
++ else PHY_00h = 0x0100;
++ }
++}
++
++//------------------------------------------------------------
++void phy_sel (int loop_phy) {
++ #ifdef DbgPrn_FuncHeader
++ printf ("phy_sel\n");
++ Debug_delay();
++ #endif
++
++ PHY_ID2 = phy_read( PHY_REG_ID_1 );
++ PHY_ID3 = phy_read( PHY_REG_ID_2 );
++ phy_set00h(loop_phy);
++
++ if ((PHY_ID2 == 0xffff) && (PHY_ID3 == 0xffff) && !Enable_SkipChkPHY) {
++ sprintf(PHYName, "--");
++ FindErr(Err_PHY_Type);
++ }
++#ifdef Enable_CheckZeroPHYID
++ else if ((PHY_ID2 == 0x0000) && (PHY_ID3 == 0x0000) && !Enable_SkipChkPHY) {
++ sprintf(PHYName, "--"); FindErr(Err_PHY_Type);
++ }
++#endif
++
++ if (phy_chk(0x0362, 0x5e6a, 0xfff0 )) {sprintf(PHYName, "BCM54612" ); if (Enable_InitPHY) phy_broadcom0(loop_phy);}//BCM54612 1G/100/10M RGMII
++ else if (phy_chk(0x0362, 0x5d10, 0xfff0 )) {sprintf(PHYName, "BCM54616S" ); if (Enable_InitPHY) phy_broadcom0(loop_phy);}//BCM54616A 1G/100/10M RGMII
++ else if (phy_chk(0x0040, 0x61e0, PHYID3_Mask)) {sprintf(PHYName, "BCM5221" ); if (Enable_InitPHY) phy_broadcom (loop_phy);}//BCM5221 100/10M MII, RMII
++ else if (phy_chk(0x0141, 0x0dd0, 0xfff0 )) {sprintf(PHYName, "88E1512" ); if (Enable_InitPHY) phy_marvell2 (loop_phy);}//88E1512 1G/100/10M RGMII
++ else if (phy_chk(0xff00, 0x1761, 0xffff )) {sprintf(PHYName, "88E6176(IntLoop)"); if (Enable_InitPHY) phy_marvell1 (loop_phy);}//88E6176 1G/100/10M 2 RGMII Switch
++ else if (phy_chk(0x0141, 0x0e90, 0xfff0 )) {sprintf(PHYName, "88E1310" ); if (Enable_InitPHY) phy_marvell0 (loop_phy);}//88E1310 1G/100/10M RGMII
++ else if (phy_chk(0x0141, 0x0cc0, PHYID3_Mask)) {sprintf(PHYName, "88E1111" ); if (Enable_InitPHY) phy_marvell (loop_phy);}//88E1111 1G/100/10M GMII, MII, RGMII
++ else if (phy_chk(0x001c, 0xc816, 0xffff )) {sprintf(PHYName, "RTL8201F" ); if (Enable_InitPHY) phy_realtek4 (loop_phy);}//RTL8201F 100/10M MII, RMII
++ else if (phy_chk(0x001c, 0xc815, 0xfff0 )) {sprintf(PHYName, "RTL8201E" ); if (Enable_InitPHY) phy_realtek0 (loop_phy);}//RTL8201E 100/10M MII, RMII(RTL8201E(L)-VC only)
++ else if (phy_chk(0x001c, 0xc912, 0xffff )) {sprintf(PHYName, "RTL8211C" ); if (Enable_InitPHY) phy_realtek3 (loop_phy);}//RTL8211C 1G/100/10M RGMII
++ else if (phy_chk(0x001c, 0xc914, 0xffff )) {sprintf(PHYName, "RTL8211D" ); if (Enable_InitPHY) phy_realtek1 (loop_phy);}//RTL8211D 1G/100/10M GMII(RTL8211DN/RTL8211DG only), MII(RTL8211DN/RTL8211DG only), RGMII
++ else if (phy_chk(0x001c, 0xc915, 0xffff )) {sprintf(PHYName, "RTL8211E" ); if (Enable_InitPHY) phy_realtek2 (loop_phy);}//RTL8211E 1G/100/10M GMII(RTL8211EG only), RGMII
++ else if (phy_chk(0x0000, 0x8201, PHYID3_Mask)) {sprintf(PHYName, "RTL8201N" ); if (Enable_InitPHY) phy_realtek (loop_phy);}//RTL8201N 100/10M MII, RMII
++ else if (phy_chk(0x0007, 0xc0c4, PHYID3_Mask)) {sprintf(PHYName, "LAN8700" ); if (Enable_InitPHY) phy_smsc (loop_phy);}//LAN8700 100/10M MII, RMII
++ else if (phy_chk(0x0022, 0x1555, 0xfff0 )) {sprintf(PHYName, "KSZ8031/KSZ8051" ); if (Enable_InitPHY) phy_micrel0 (loop_phy);}//KSZ8051/KSZ8031 100/10M RMII
++ else if (phy_chk(0x0022, 0x1560, 0xfff0 )) {sprintf(PHYName, "KSZ8081" ); if (Enable_InitPHY) phy_micrel0 (loop_phy);}//KSZ8081 100/10M RMII
++ else if (phy_chk(0x0022, 0x1512, 0xfff0 )) {sprintf(PHYName, "KSZ8041" ); if (Enable_InitPHY) phy_micrel (loop_phy);}//KSZ8041 100/10M RMII
++ else if (phy_chk(0x0007, 0x0421, 0xfff0 )) {sprintf(PHYName, "VSC8601" ); if (Enable_InitPHY) phy_vitesse (loop_phy);}//VSC8601 1G/100/10M RGMII
++ else {sprintf(PHYName, "default" ); if (Enable_InitPHY) phy_default (loop_phy);}//
++}
++
++//------------------------------------------------------------
++void recov_phy (int loop_phy) {
++ #ifdef DbgPrn_FuncHeader
++ printf ("recov_phy\n");
++ Debug_delay();
++ #endif
++
++ if (phy_chk(0x0362, 0x5e6a, 0xfff0 )) recov_phy_broadcom0(loop_phy);//BCM54612 1G/100/10M RGMII
++ else if (phy_chk(0x0362, 0x5d10, 0xfff0 )) recov_phy_broadcom0(loop_phy);//BCM54616A 1G/100/10M RGMII
++ else if (phy_chk(0x0141, 0x0dd0, 0xfff0 )) recov_phy_marvell2 (loop_phy);//88E1512 1G/100/10M RGMII
++ else if (phy_chk(0xff00, 0x1761, 0xffff )) recov_phy_marvell1 (loop_phy);//88E6176 1G/100/10M 2 RGMII Switch
++ else if (phy_chk(0x0141, 0x0e90, 0xfff0 )) recov_phy_marvell0 (loop_phy);//88E1310 1G/100/10M RGMII
++ else if (phy_chk(0x0141, 0x0cc0, PHYID3_Mask)) recov_phy_marvell (loop_phy);//88E1111 1G/100/10M GMII, MII, RGMII
++ else if (phy_chk(0x001c, 0xc914, 0xffff )) recov_phy_realtek1 (loop_phy);//RTL8211D 1G/100/10M GMII(RTL8211DN/RTL8211DG only), MII(RTL8211DN/RTL8211DG only), RGMII
++ else if (phy_chk(0x001c, 0xc915, 0xffff )) recov_phy_realtek2 (loop_phy);//RTL8211E 1G/100/10M GMII(RTL8211EG only), RGMII
++ else if (phy_chk(0x001c, 0xc912, 0xffff )) recov_phy_realtek3 (loop_phy);//RTL8211C 1G/100/10M RGMII
++ else if (phy_chk(0x0007, 0x0421, 0xfff0 )) recov_phy_vitesse (loop_phy);//VSC8601 1G/100/10M RGMII
++}
++
++//------------------------------------------------------------
++void init_phy (int loop_phy) {
++ #ifdef DbgPrn_FuncHeader
++ printf ("init_phy\n");
++ Debug_delay();
++ #endif
++
++ sprintf( PHYID, "PHY%d", SelectMAC + 1 );
++
++ if ( DbgPrn_PHYInit )
++ phy_dump( PHYID );
++
++ if ( find_phyadr() == TRUE )
++ phy_sel( loop_phy );
++
++ if ( DbgPrn_PHYInit )
++ phy_dump( PHYID );
++}
++
++
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.H b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.H
+new file mode 100644
+index 0000000..6fa96e6
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.H
+@@ -0,0 +1,50 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef PLLTESTU_H
++#define PLLTESTU_H
++
++//PLL Mode Definition
++#define NAND_PLLMODE 0x00
++#define DELAY_PLLMODE 0x04
++#define PCI_PLLMODE 0x08
++#define DPLL_PLLMODE 0x2c
++#define MPLL_PLLMODE 0x10
++#define HPLL_PLLMODE 0x14
++#define LPC_PLLMODE 0x18
++#define VIDEOA_PLLMODE 0x1c
++#define D2PLL_PLLMODE 0x0c
++#define VIDEOB_PLLMODE 0x3c
++
++#define PCI_PLLMODE_AST1160 0x10
++#define MPLL_PLLMODE_AST1160 0x14
++#define HPLL_PLLMODE_AST1160 0x14
++#define DPLL_PLLMODE_AST1160 0x1c
++
++#define PCI_PLLMODE_AST2300 0x2c
++#define MPLL_PLLMODE_AST2300 0x10
++#define HPLL_PLLMODE_AST2300 0x30
++#define DPLL_PLLMODE_AST2300 0x08
++#define DEL0_PLLMODE_AST2300 0x00
++
++#define ERR_FATAL 0x00000001
++
++typedef struct _VGAINFO {
++ USHORT usDeviceID;
++ UCHAR jRevision;
++
++ ULONG ulMCLK;
++ ULONG ulDRAMBusWidth;
++
++ ULONG ulCPUCLK;
++ ULONG ulAHBCLK;
++} _VGAInfo;
++
++#endif // End PLLTESTU_H
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c
+new file mode 100644
+index 0000000..95958b0
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c
+@@ -0,0 +1,411 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define PLLTEST_C
++static const char ThisFile[] = "PLLTEST.c";
++
++#include "SWFUNC.H"
++
++#include <COMMINF.H>
++#include <STDUBOOT.H>
++#include <TYPEDEF.H>
++#include <IO.H>
++#include <PLLTESTU.H>
++
++/*
++ * static
++ */
++static UCHAR jVersion[] = "v.0.57.00";
++
++void print_usage( void )
++{
++ printf(" PLLTest [pll mode] [err rate]\n");
++ printf(" [pll mode] h-pll: ARM CPU Clock PLL\n");
++ printf(" m-pll: Memory Clock PLL\n");
++ printf(" [err rate] Error Rate: unit %\n");
++ printf(" default is 1%\n");
++}
++
++BOOL CompareToRing(_VGAInfo *VGAInfo, ULONG ulPLLMode, ULONG ulDCLK, ULONG ulErrRate)
++{
++ ULONG ulCounter, ulLowLimit, ulHighLimit;
++ ULONG ulData, ulValue, ulDiv;
++ ULONG ulSCUBase;
++ double del0;
++ ULONG uldel0;
++
++ if ((VGAInfo->usDeviceID == 0x1160) || (VGAInfo->usDeviceID == 0x1180))
++ ulSCUBase = 0x80fc8200;
++ else
++ ulSCUBase = 0x1e6e2000;
++
++ //Fixed AST2300 H-PLL can't Get Correct Value in VGA only mode, ycchen@081711
++ if ( (VGAInfo->jRevision >= 0x20) && (ulPLLMode == HPLL_PLLMODE_AST2300) )
++ {
++ WriteSOC_DD(ulSCUBase, 0x1688a8a8);
++ ulData = ReadSOC_DD(ulSCUBase + 0x08);
++ WriteSOC_DD(ulSCUBase + 0x08, ulData & 0xFFFFFF00);
++ }
++
++ ulCounter = (ulDCLK/1000) * 512 / 24000 - 1;
++ ulLowLimit = ulCounter * (100 - ulErrRate) / 100;
++ ulHighLimit = ulCounter * (100 + ulErrRate) / 100;
++
++ DELAY(10);
++ WriteSOC_DD(ulSCUBase, 0x1688a8a8);
++ WriteSOC_DD(ulSCUBase + 0x28, (ulHighLimit << 16) | ulLowLimit);
++ WriteSOC_DD(ulSCUBase + 0x10, ulPLLMode);
++ WriteSOC_DD(ulSCUBase + 0x10, ulPLLMode | 0x03);
++ DELAY(1);
++ do {
++ ulData = ReadSOC_DD(ulSCUBase + 0x10);
++ } while (!(ulData & 0x40));
++ ulValue = ReadSOC_DD(ulSCUBase + 0x14);
++
++ //Patch for AST1160/1180 DCLK calculate
++ if ( ((VGAInfo->usDeviceID == 0x1160) || (VGAInfo->usDeviceID == 0x1180)) && (ulPLLMode == DPLL_PLLMODE_AST1160) )
++ {
++ ulData = ReadSOC_DD(0x80fc906c);
++ ulDiv = ulData & 0x000c0000;
++ ulDiv >>= 18;
++ ulDiv++;
++ ulValue /= ulDiv;
++ }
++
++ if ( (VGAInfo->jRevision >= 0x20) && (ulPLLMode == DEL0_PLLMODE_AST2300) )
++ {
++ del0 = (double)(24.0 * (ulValue + 1) / 512.0);
++ del0 = 1000/del0/16/8;
++ uldel0 = (ULONG) (del0 * 1000000);
++ if (uldel0 < ulDCLK)
++ {
++ printf( "[PASS][DEL0] Actual DEL0:%f ns, Max. DEL0:%f ns \n", del0, (double)ulDCLK/1000000);
++ ulData |= 0x80;
++ }
++ else
++ {
++ printf( "[ERROR][DEL0] Actual DEL0:%f ns, Max. DEL0:%f ns \n", del0, (double)ulDCLK/1000000);
++ ulData == 0x00;
++ }
++ }
++ else
++ {
++ printf( "[INFO] PLL Predict Count = %x, Actual Count = %x \n", ulCounter, ulValue);
++ }
++
++ WriteSOC_DD(ulSCUBase + 0x10, 0x2C); //disable ring
++
++ if (ulData & 0x80)
++ return (TRUE);
++ else
++ return(FALSE);
++} /* CompareToRing */
++
++VOID GetDRAMInfo(_VGAInfo *VGAInfo)
++{
++ ULONG ulData, ulData2;
++ ULONG ulRefPLL, ulDeNumerator, ulNumerator, ulDivider, ulOD;
++
++ if (VGAInfo->jRevision >= 0x10)
++ {
++ WriteSOC_DD(0x1e6e2000, 0x1688A8A8);
++
++ //Get DRAM Bus Width
++ ulData = ReadSOC_DD(0x1e6e0004);
++ if (ulData & 0x40)
++ VGAInfo->ulDRAMBusWidth = 16;
++ else
++ VGAInfo->ulDRAMBusWidth = 32;
++
++ ulRefPLL = 24000;
++ if (VGAInfo->jRevision >= 0x30) //AST2400
++ {
++ ulData = ReadSOC_DD(0x1e6e2070);
++ if (ulData & 0x00800000) //D[23] = 1
++ ulRefPLL = 25000;
++ }
++
++ ulData = ReadSOC_DD(0x1e6e2020);
++ ulDeNumerator = ulData & 0x0F;
++ ulNumerator = (ulData & 0x07E0) >> 5;
++ ulOD = (ulData & 0x10) ? 1:2;
++
++ ulData = (ulData & 0x7000) >> 12;
++ switch (ulData)
++ {
++ case 0x07:
++ ulDivider = 16;
++ break;
++ case 0x06:
++ ulDivider = 8;
++ break;
++ case 0x05:
++ ulDivider = 4;
++ break;
++ case 0x04:
++ ulDivider = 2;
++ break;
++ default:
++ ulDivider = 0x01;
++ }
++
++ VGAInfo->ulMCLK = ulRefPLL * ulOD * (ulNumerator + 2) / ((ulDeNumerator + 1) * ulDivider * 1000);
++ }
++} // GetDRAMInfo
++
++VOID GetCLKInfo( _VGAInfo *VGAInfo)
++{
++ ULONG ulData, ulCPUTrap, ulAHBTrap;
++ ULONG ulRefPLL, ulDeNumerator, ulNumerator, ulDivider, ulOD;
++
++ if (VGAInfo->jRevision >= 0x30)
++ {
++ WriteSOC_DD(0x1e6e2000, 0x1688a8a8);
++ ulData = ReadSOC_DD(0x1e6e2024);
++ if (ulData & 0x40000) //from H-PLL
++ {
++ ulRefPLL = 24000;
++ ulData = ReadSOC_DD(0x1e6e2070);
++ if (ulData & 0x00800000) //D[23] = 1
++ ulRefPLL = 25000;
++
++ ulData = ReadSOC_DD(0x1e6e2024);
++
++ ulDeNumerator = ulData & 0x0F;
++ ulNumerator = (ulData & 0x07E0) >> 5;
++ ulOD = (ulData & 0x10) ? 1:2;
++
++ VGAInfo->ulCPUCLK = ulRefPLL * ulOD * (ulNumerator + 2) / ((ulDeNumerator + 1) * 1000);
++
++ }
++ else //from trapping
++ {
++ ulRefPLL = 24;
++ ulData = ReadSOC_DD(0x1e6e2070);
++ if (ulData & 0x00800000) //D[23] = 1
++ ulRefPLL = 25;
++
++ ulCPUTrap = ulData & 0x0300;
++ ulCPUTrap >>= 8;
++
++ switch (ulCPUTrap)
++ {
++ case 0x00:
++ VGAInfo->ulCPUCLK = ulRefPLL * 16;
++ break;
++ case 0x01:
++ VGAInfo->ulCPUCLK = ulRefPLL * 15;
++ break;
++ case 0x02:
++ VGAInfo->ulCPUCLK = ulRefPLL * 14;
++ break;
++ case 0x03:
++ VGAInfo->ulCPUCLK = ulRefPLL * 17;
++ break;
++ }
++
++ }
++
++ ulData = ReadSOC_DD(0x1e6e2070);
++ ulAHBTrap = ulData & 0x0c00;
++ ulAHBTrap >>= 10;
++ switch (ulAHBTrap)
++ {
++ case 0x00:
++ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK;
++ break;
++ case 0x01:
++ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 2;
++ break;
++ case 0x02:
++ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 4;
++ break;
++ case 0x03:
++ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 3;
++ break;
++ }
++
++ } //AST2400
++ else if (VGAInfo->jRevision >= 0x20)
++ {
++ WriteSOC_DD(0x1e6e2000, 0x1688a8a8);
++ ulData = ReadSOC_DD(0x1e6e2024);
++ if (ulData & 0x40000) //from H-PLL
++ {
++ ulRefPLL = 24000;
++
++ ulData = ReadSOC_DD(0x1e6e2024);
++
++ ulDeNumerator = ulData & 0x0F;
++ ulNumerator = (ulData & 0x07E0) >> 5;
++ ulOD = (ulData & 0x10) ? 1:2;
++
++ VGAInfo->ulCPUCLK = ulRefPLL * ulOD * (ulNumerator + 2) / ((ulDeNumerator + 1) * 1000);
++
++ }
++ else //from trapping
++ {
++ ulData = ReadSOC_DD(0x1e6e2070);
++ ulCPUTrap = ulData & 0x0300;
++ ulCPUTrap >>= 8;
++
++ switch (ulCPUTrap)
++ {
++ case 0x00:
++ VGAInfo->ulCPUCLK = 384;
++ break;
++ case 0x01:
++ VGAInfo->ulCPUCLK = 360;
++ break;
++ case 0x02:
++ VGAInfo->ulCPUCLK = 336;
++ break;
++ case 0x03:
++ VGAInfo->ulCPUCLK = 408;
++ break;
++ }
++
++ }
++
++ ulData = ReadSOC_DD(0x1e6e2070);
++ ulAHBTrap = ulData & 0x0c00;
++ ulAHBTrap >>= 10;
++ switch (ulAHBTrap)
++ {
++ case 0x00:
++ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK;
++ break;
++ case 0x01:
++ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 2;
++ break;
++ case 0x02:
++ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 4;
++ break;
++ case 0x03:
++ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 3;
++ break;
++ }
++
++ } //AST2300
++} // GetCLKInfo
++
++int pll_function(int argc, char *argv[])
++{
++ _VGAInfo *pVGAInfo;
++ ULONG ulErrRate = 1;
++ ULONG PLLMode;
++ ULONG RefClk;
++ CHAR *stop_at;
++ CHAR i;
++
++ printf("**************************************************** \n");
++ printf("*** ASPEED Graphics PLL Test %s Log *** \n", jVersion);
++ printf("*** for u-boot *** \n");
++ printf("**************************************************** \n");
++ printf("\n");
++
++ // Check chip type
++ switch ( ReadSOC_DD( 0x1e6e2000 + 0x7c ) ) {
++ case 0x02010303 :
++ case 0x02000303 :
++ printf("The chip is AST2400\n" );
++ pVGAInfo->usDeviceID = 0x2400;
++ pVGAInfo->jRevision = 0x30;
++ break;
++
++ case 0x02010103 :
++ case 0x02000003 :
++ printf("The chip is AST1400\n" );
++ pVGAInfo->usDeviceID = 0x1400;
++ pVGAInfo->jRevision = 0x30;
++ break;
++
++ case 0x01010303 :
++ case 0x01000003 :
++ printf("The chip is AST2300\n" );
++ pVGAInfo->usDeviceID = 0x2300;
++ pVGAInfo->jRevision = 0x20;
++ break;
++
++ case 0x01010203 :
++ printf("The chip is AST1050\n" );
++ pVGAInfo->usDeviceID = 0x1050;
++ pVGAInfo->jRevision = 0x20;
++ break;
++
++ default :
++ printf ("Error Silicon Revision ID(SCU7C) %08lx!!!\n", ReadSOC_DD( 0x1e6e2000 + 0x7c ) );
++ return(1);
++ }
++
++
++ GetDRAMInfo( pVGAInfo );
++ GetCLKInfo( pVGAInfo );
++
++ if ( ( argc <= 1 ) || ( argc >= 4 ) ){
++ print_usage();
++ return (ERR_FATAL);
++ }
++ else {
++ for ( i = 1; i < argc; i++ ) {
++ switch ( i ) {
++ case 1:
++ if (!strcmp(argv[i], "m-pll"))
++ {
++ if (pVGAInfo->jRevision >= 0x20)
++ PLLMode = MPLL_PLLMODE_AST2300;
++ else
++ PLLMode = MPLL_PLLMODE;
++
++ RefClk = pVGAInfo->ulMCLK * 1000000;
++ if (pVGAInfo->jRevision >= 0x20) //dual-edge
++ RefClk /= 2;
++ }
++ else if (!strcmp(argv[i], "h-pll"))
++ {
++ if (pVGAInfo->jRevision >= 0x20)
++ PLLMode = HPLL_PLLMODE_AST2300;
++ else
++ PLLMode = HPLL_PLLMODE;
++
++ //AST2300 only has HCLK ring test mode, ycchen@040512
++ RefClk = pVGAInfo->ulCPUCLK * 1000000; //Other : H-PLL
++ if (pVGAInfo->jRevision >= 0x20) //AST2300: HCLK
++ RefClk = pVGAInfo->ulAHBCLK * 1000000;
++ }
++ else {
++ print_usage();
++ return (ERR_FATAL);
++ }
++ break;
++ case 2:
++ ulErrRate = (ULONG) strtoul(argv[i], &stop_at, 10);
++
++ break;
++ default:
++ break;
++ } // End switch()
++ } // End for
++ }
++
++ /* Compare ring */
++ if (CompareToRing(pVGAInfo, PLLMode, RefClk, ulErrRate ) == TRUE)
++ {
++ printf("[PASS] %s PLL Check Pass!! \n", argv[1]);
++ return 0;
++ }
++ else
++ {
++ printf("[ERROR] %s PLL Check Failed!! \n", argv[1]);
++ return (ERR_FATAL);
++ }
++}
++
++
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/SPIM.c b/arch/arm/cpu/arm926ejs/aspeed/SPIM.c
+new file mode 100644
+index 0000000..e1bdd07
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/SPIM.c
+@@ -0,0 +1,63 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define SPIM_C
++static const char ThisFile[] = "SPIM.c";
++
++#include "SWFUNC.H"
++
++#ifdef SPI_BUS
++
++#include <stdio.h>
++#include <stdlib.h>
++#include <conio.h>
++#include <string.h>
++#include "TYPEDEF.H"
++#include "LIB_SPI.H"
++
++#define SPIM_CMD_WHA 0x01
++#define SPIM_CMD_RD 0x0B
++#define SPIM_CMD_DRD 0xBB
++#define SPIM_CMD_WR 0x02
++#define SPIM_CMD_DWR 0xD2
++#define SPIM_CMD_STA 0x05
++#define SPIM_CMD_ENBYTE 0x06
++#define SPIM_CMD_DISBYTE 0x04
++
++ULONG spim_cs;
++ULONG spim_base;
++ULONG spim_hadr;
++
++void spim_end()
++{
++ ULONG data;
++
++ data = MIndwm((ULONG)mmiobase, 0x1E620010 + (spim_cs << 2));
++ MOutdwm( (ULONG)mmiobase, 0x1E620010 + (spim_cs << 2), data | 0x4);
++ MOutdwm( (ULONG)mmiobase, 0x1E620010 + (spim_cs << 2), data);
++}
++
++//------------------------------------------------------------
++void spim_init(int cs)
++{
++ ULONG data;
++
++ spim_cs = cs;
++ MOutdwm( (ULONG)mmiobase, 0x1E620000, (0x2 << (cs << 1)) | (0x10000 << cs));
++ MOutdwm( (ULONG)mmiobase, 0x1E620010 + (cs << 2), 0x00000007);
++ MOutdwm( (ULONG)mmiobase, 0x1E620010 + (cs << 2), 0x00002003);
++ MOutdwm( (ULONG)mmiobase, 0x1E620004, 0x100 << cs);
++ data = MIndwm((ULONG)mmiobase, 0x1E620030 + (cs << 2));
++ spim_base = 0x20000000 | ((data & 0x007f0000) << 7);
++ MOutwm ( (ULONG)mmiobase, spim_base, SPIM_CMD_WHA);
++ spim_end();
++ spim_hadr = 0;
++}
++#endif // End SPI_BUS
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H
+new file mode 100644
+index 0000000..7fbf590
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H
+@@ -0,0 +1,18 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef STDUBOOT_H
++#define STDUBOOT_H
++
++unsigned long int strtoul(char *string, char **endPtr, int base);
++int atoi( char s[] );
++int rand(void);
++
++#endif // End STDUBOOT_H
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c
+new file mode 100644
+index 0000000..90e2997
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c
+@@ -0,0 +1,235 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define STDUBOOT_C
++static const char ThisFile[] = "STDUBOOT.c";
++
++#include "SWFUNC.H"
++
++#ifdef SLT_UBOOT
++
++int isspace ( char c )
++{
++ if ( ( c == ' ' ) || ( c == 9 ) || ( c == 13 ) )
++ return 1;
++
++ return 0;
++}
++
++/*
++ * strtoul.c --
++ *
++ * Source code for the "strtoul" library procedure.
++ *
++ * Copyright 1988 Regents of the University of California
++ * Permission to use, copy, modify, and distribute this
++ * software and its documentation for any purpose and without
++ * fee is hereby granted, provided that the above copyright
++ * notice appear in all copies. The University of California
++ * makes no representations about the suitability of this
++ * software for any purpose. It is provided "as is" without
++ * express or implied warranty.
++ */
++
++//#include <ctype.h>
++
++/*
++ * The table below is used to convert from ASCII digits to a
++ * numerical equivalent. It maps from '0' through 'z' to integers
++ * (100 for non-digit characters).
++ */
++
++static char cvtIn[] = {
++ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* '0' - '9' */
++ 100, 100, 100, 100, 100, 100, 100, /* punctuation */
++ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, /* 'A' - 'Z' */
++ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
++ 30, 31, 32, 33, 34, 35,
++ 100, 100, 100, 100, 100, 100, /* punctuation */
++ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, /* 'a' - 'z' */
++ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
++ 30, 31, 32, 33, 34, 35};
++
++/*
++ *----------------------------------------------------------------------
++ *
++ * strtoul --
++ *
++ * Convert an ASCII string into an integer.
++ *
++ * Results:
++ * The return value is the integer equivalent of string. If endPtr
++ * is non-NULL, then *endPtr is filled in with the character
++ * after the last one that was part of the integer. If string
++ * doesn't contain a valid integer value, then zero is returned
++ * and *endPtr is set to string.
++ *
++ * Side effects:
++ * None.
++ *
++ *----------------------------------------------------------------------
++ */
++
++unsigned long int
++strtoul(char *string, char **endPtr, int base)
++ /* string; String of ASCII digits, possibly
++ * preceded by white space. For bases
++ * greater than 10, either lower- or
++ * upper-case digits may be used.
++ */
++ /* **endPtr; Where to store address of terminating
++ * character, or NULL. */
++ /* base; Base for conversion. Must be less
++ * than 37. If 0, then the base is chosen
++ * from the leading characters of string:
++ * "0x" means hex, "0" means octal, anything
++ * else means decimal.
++ */
++{
++ register char *p;
++ register unsigned long int result = 0;
++ register unsigned digit;
++ int anyDigits = 0;
++
++ /*
++ * Skip any leading blanks.
++ */
++
++ p = string;
++ while (isspace(*p)) {
++ p += 1;
++ }
++
++ /*
++ * If no base was provided, pick one from the leading characters
++ * of the string.
++ */
++
++ if (base == 0)
++ {
++ if (*p == '0') {
++ p += 1;
++ if (*p == 'x') {
++ p += 1;
++ base = 16;
++ } else {
++
++ /*
++ * Must set anyDigits here, otherwise "0" produces a
++ * "no digits" error.
++ */
++
++ anyDigits = 1;
++ base = 8;
++ }
++ }
++ else base = 10;
++ } else if (base == 16) {
++
++ /*
++ * Skip a leading "0x" from hex numbers.
++ */
++
++ if ((p[0] == '0') && (p[1] == 'x')) {
++ p += 2;
++ }
++ }
++
++ /*
++ * Sorry this code is so messy, but speed seems important. Do
++ * different things for base 8, 10, 16, and other.
++ */
++
++ if (base == 8) {
++ for ( ; ; p += 1) {
++ digit = *p - '0';
++ if (digit > 7) {
++ break;
++ }
++ result = (result << 3) + digit;
++ anyDigits = 1;
++ }
++ } else if (base == 10) {
++ for ( ; ; p += 1) {
++ digit = *p - '0';
++ if (digit > 9) {
++ break;
++ }
++ result = (10*result) + digit;
++ anyDigits = 1;
++ }
++ } else if (base == 16) {
++ for ( ; ; p += 1) {
++ digit = *p - '0';
++ if (digit > ('z' - '0')) {
++ break;
++ }
++ digit = cvtIn[digit];
++ if (digit > 15) {
++ break;
++ }
++ result = (result << 4) + digit;
++ anyDigits = 1;
++ }
++ } else {
++ for ( ; ; p += 1) {
++ digit = *p - '0';
++ if (digit > ('z' - '0')) {
++ break;
++ }
++ digit = cvtIn[digit];
++ if (digit >= base) {
++ break;
++ }
++ result = result*base + digit;
++ anyDigits = 1;
++ }
++ }
++
++ /*
++ * See if there were any digits at all.
++ */
++
++ if (!anyDigits) {
++ p = string;
++ }
++
++ if (endPtr != 0) {
++ *endPtr = p;
++ }
++
++ return result;
++}
++
++// -----------------------------------------------------------------------------
++int atoi( char s[] )
++{
++
++ int i;
++ int ans = 0;
++
++ for( i = 0; s[i] >= '0' && s[i] <= '9'; ++i )
++ ans = ( 10 * ans ) + ( s[i] - '0' );
++
++ return ans;
++}
++
++// -----------------------------------------------------------------------------
++/* rand:return pseudo-random integer on 0...32767 */
++int rand(void)
++{
++ static unsigned long int next = 1;
++
++ next = next * 1103515245 + 12345;
++
++ return (unsigned int) ( next / 65536 ) % 32768;
++}
++
++#endif // End SLT_UBOOT
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/STRESS.c b/arch/arm/cpu/arm926ejs/aspeed/STRESS.c
+new file mode 100644
+index 0000000..dffd64f
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/STRESS.c
+@@ -0,0 +1,145 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define STRESS_C
++static const char ThisFile[] = "STRESS.c";
++
++#include "SWFUNC.H"
++#include <COMMINF.H>
++#include <IO.H>
++
++#define TIMEOUT_DRAM 5000000
++
++/* ------------------------------------------------------------------------- */
++int MMCTestBurst(unsigned int datagen)
++{
++ unsigned int data;
++ unsigned int timeout = 0;
++
++ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
++ WriteSOC_DD( 0x1E6E0070, (0x000000C1 | (datagen << 3)) );
++
++ do {
++ data = ReadSOC_DD( 0x1E6E0070 ) & 0x3000;
++
++ if( data & 0x2000 )
++ return(0);
++
++ if( ++timeout > TIMEOUT_DRAM ) {
++ printf("Timeout!!\n");
++ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
++
++ return(0);
++ }
++ } while( !data );
++ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
++
++ return(1);
++}
++
++/* ------------------------------------------------------------------------- */
++int MMCTestSingle(unsigned int datagen)
++{
++ unsigned int data;
++ unsigned int timeout = 0;
++
++ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
++ WriteSOC_DD( 0x1E6E0070, (0x00000085 | (datagen << 3)) );
++
++ do {
++ data = ReadSOC_DD( 0x1E6E0070 ) & 0x3000;
++
++ if( data & 0x2000 )
++ return(0);
++
++ if( ++timeout > TIMEOUT_DRAM ){
++ printf("Timeout!!\n");
++ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
++
++ return(0);
++ }
++ } while ( !data );
++ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
++
++ return(1);
++}
++
++/* ------------------------------------------------------------------------- */
++int MMCTest()
++{
++ unsigned int pattern;
++
++ pattern = ReadSOC_DD( 0x1E6E2078 );
++ printf("Pattern = %08X : ",pattern);
++
++ WriteSOC_DD(0x1E6E0074, (DRAM_MapAdr | 0x7fffff) );
++ WriteSOC_DD(0x1E6E007C, pattern );
++
++ if(!MMCTestBurst(0)) return(0);
++ if(!MMCTestBurst(1)) return(0);
++ if(!MMCTestBurst(2)) return(0);
++ if(!MMCTestBurst(3)) return(0);
++ if(!MMCTestBurst(4)) return(0);
++ if(!MMCTestBurst(5)) return(0);
++ if(!MMCTestBurst(6)) return(0);
++ if(!MMCTestBurst(7)) return(0);
++ if(!MMCTestSingle(0)) return(0);
++ if(!MMCTestSingle(1)) return(0);
++ if(!MMCTestSingle(2)) return(0);
++ if(!MMCTestSingle(3)) return(0);
++ if(!MMCTestSingle(4)) return(0);
++ if(!MMCTestSingle(5)) return(0);
++ if(!MMCTestSingle(6)) return(0);
++ if(!MMCTestSingle(7)) return(0);
++
++ return(1);
++}
++
++/* ------------------------------------------------------------------------- */
++int dram_stress_function(int argc, char *argv[])
++{
++ unsigned int Pass;
++ unsigned int PassCnt = 0;
++ unsigned int Testcounter = 0;
++ int ret = 1;
++ char *stop_at;
++
++ printf("**************************************************** \n");
++ printf("*** ASPEED Stress DRAM *** \n");
++ printf("*** 20131107 for u-boot *** \n");
++ printf("**************************************************** \n");
++ printf("\n");
++
++ if ( argc != 2 ){
++ ret = 0;
++ return ( ret );
++ }
++ else {
++ Testcounter = (unsigned int) strtoul(argv[1], &stop_at, 10);
++ }
++
++ WriteSOC_DD(0x1E6E0000, 0xFC600309);
++
++ while( ( Testcounter > PassCnt ) || ( Testcounter == 0 ) ){
++ if( !MMCTest() ) {
++ printf("FAIL...%d/%d\n", PassCnt, Testcounter);
++ ret = 0;
++
++ break;
++ }
++ else {
++ PassCnt++;
++ printf("Pass %d/%d\n", PassCnt, Testcounter);
++ }
++ } // End while()
++
++ return( ret );
++}
++
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/SWFUNC.H b/arch/arm/cpu/arm926ejs/aspeed/SWFUNC.H
+new file mode 100644
+index 0000000..0a03654
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/SWFUNC.H
+@@ -0,0 +1,137 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef SWFUNC_H
++#define SWFUNC_H
++
++
++//---------------------------------------------------------
++// Program information
++//---------------------------------------------------------
++#define VER_NAME "Ver 0.34 version @2014/03/25 0932"
++
++/* == Step 1: ====== Support OS system =================== */
++// LinuxAP
++// #define Windows
++#define SLT_UBOOT
++//#define SLT_DOS
++
++/* == Step 2:======== Support interface ================== */
++/* Choose One */
++//#define SPI_BUS
++//#define USE_LPC
++//#define USE_P2A // PCI or PCIe bus to AHB bus
++
++/* == Step 3:========== Support Chip ================== */
++//#define AST1010_CHIP
++//#define AST3200_IOMAP
++//#define FPGA
++
++#ifdef AST1010_CHIP
++ #ifdef SLT_UBOOT
++ #define AST1010_IOMAP 1
++ #endif
++ #ifdef SLT_DOS
++ #define AST1010_IOMAP 2
++
++ // AST1010 only has LPC interface
++ #undef USE_P2A
++ #undef SPI_BUS
++ #define USE_LPC
++ #endif
++#endif
++
++/* == Step 4:========== Select PHY ================== */
++//#define SUPPORT_PHY_LAN9303 // Initial PHY via I2C bus
++#define LAN9303_I2C_BUSNUM 6 // 1-based
++#define LAN9303_I2C_ADR 0x14
++
++/* ====================== Program ======================== */
++// The "PHY_NCSI" option is only for DOS compiler
++#if defined (PHY_NCSI)
++ #ifdef SLT_UBOOT
++ #error Wrong setting......
++ #endif
++#endif
++
++#if defined (PHY_NCSI)
++ #ifdef SUPPORT_PHY_LAN9303
++ #error Wrong setting (Can't support LAN9303)......
++ #endif
++#endif
++
++/* ================= Check setting ===================== */
++#ifdef SLT_UBOOT
++ #ifdef SLT_DOS
++ #error Can NOT support two OS
++ #endif
++#endif
++#ifdef SLT_DOS
++ #ifdef SLT_UBOOT
++ #error Can NOT support two OS
++ #endif
++#endif
++
++#ifdef USE_P2A
++ #ifdef SLT_UBOOT
++ #error Can NOT be set PCI bus in Uboot
++ #endif
++#endif
++#ifdef USE_LPC
++ #ifdef SLT_UBOOT
++ #error Can NOT be set LPC bus in Uboot
++ #endif
++#endif
++#ifdef SPI_BUS
++ #ifdef SLT_UBOOT
++ #error Can NOT be set SPI bus in Uboot
++ #endif
++#endif
++
++/* ======================== Program flow control ======================== */
++#define RUN_STEP 5
++// 0: read_scu
++// 1: parameter setup
++// 2: init_scu1,
++// 3: init_scu_macrst
++// 4: Data Initial
++// 5: ALL
++
++/* ====================== Switch print debug message ====================== */
++#define DbgPrn_Enable_Debug_delay 0
++//#define DbgPrn_FuncHeader 0 //1
++#define DbgPrn_ErrFlg 0
++#define DbgPrn_BufAdr 0 //1
++#define DbgPrn_Bufdat 0
++#define DbgPrn_BufdatDetail 0
++#define DbgPrn_PHYRW 0
++#define DbgPrn_PHYInit 0
++#define DbgPrn_PHYName 0
++#define DbgPrn_DumpMACCnt 0
++#define DbgPrn_Info 0 //1
++#define DbgPrn_FRAME_LEN 0
++
++
++/* ============ Enable or Disable Check item of the descriptor ============ */
++#define CheckRxOwn
++#define CheckRxErr
++//#define CheckOddNibble
++#define CheckCRC
++#define CheckRxFIFOFull
++#define CheckRxLen
++//#define CheckDataEveryTime
++
++//#define CheckRxbufUNAVA
++#define CheckRPktLost
++//#define CheckNPTxbufUNAVA
++#define CheckTPktLost
++#define CheckRxBuf
++
++#endif // SWFUNC_H
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c b/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c
+new file mode 100644
+index 0000000..72936c0
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c
+@@ -0,0 +1,151 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define PLLTEST_C
++static const char ThisFile[] = "PLLTEST.c";
++
++#include "SWFUNC.H"
++
++#include <COMMINF.H>
++#include <TYPEDEF.H>
++#include <IO.H>
++
++#define ASTCHIP_2400 0
++#define ASTCHIP_2300 1
++#define ASTCHIP_1400 2
++#define ASTCHIP_1300 3
++#define ASTCHIP_1050 4
++
++const UCHAR jVersion[] = "v.0.60.06";
++
++typedef struct _TRAPINFO {
++ USHORT CPU_clk;
++ UCHAR CPU_AHB_ratio;
++} _TrapInfo;
++
++const _TrapInfo AST_default_trap_setting[] = {
++ // CPU_clk, CPU_AHB_ratio
++ { 384, 2 }, // AST2400 or AST1250 ( ASTCHIP_2400 )
++ { 384, 2 }, // AST2300 ( ASTCHIP_2300 )
++ { 384, 0xFF }, // AST1400 ( ASTCHIP_1400 )
++ { 384, 0xFF }, // AST1300 ( ASTCHIP_1300 )
++ { 384, 2 } // AST1050 ( ASTCHIP_1050 )
++};
++
++int trap_function(int argc, char *argv[])
++{
++ UCHAR chiptype;
++ ULONG ulData, ulTemp;
++ UCHAR status = TRUE;
++ USHORT val_trap;
++
++ printf("**************************************************** \n");
++ printf("*** ASPEED Trap Test %s Log *** \n", jVersion);
++ printf("*** for u-boot *** \n");
++ printf("**************************************************** \n");
++ printf("\n");
++
++ // Check chip type
++ switch ( ReadSOC_DD( 0x1e6e2000 + 0x7c ) ) {
++ case 0x02010303 :
++ case 0x02000303 :
++ printf("The chip is AST2400 or AST1250\n" );
++ chiptype = ASTCHIP_2400;
++ break;
++
++ case 0x02010103 :
++ case 0x02000003 :
++ printf("The chip is AST1400\n" );
++ chiptype = ASTCHIP_1400;
++ break;
++
++ case 0x01010303 :
++ case 0x01000003 :
++ printf("The chip is AST2300\n" );
++ chiptype = ASTCHIP_2300;
++ break;
++
++ case 0x01010203 :
++ printf("The chip is AST1050\n" );
++ chiptype = ASTCHIP_1050;
++ break;
++
++ case 0x01010003 :
++ printf("The chip is AST1300\n" );
++ chiptype = ASTCHIP_1300;
++ break;
++
++ default :
++ printf ("Error Silicon Revision ID(SCU7C) %08lx!!!\n", ReadSOC_DD( 0x1e6e2000 + 0x7c ) );
++ return(1);
++ }
++
++ WriteSOC_DD(0x1e6e2000, 0x1688A8A8);
++ ulData = ReadSOC_DD(0x1e6e2070);
++
++ // Check CPU clock
++ ulTemp = ulData;
++ ulTemp &= 0x0300;
++ ulTemp >>= 8;
++
++ switch (ulTemp)
++ {
++ case 0x00:
++ val_trap = 384;
++ break;
++ case 0x01:
++ val_trap = 360;
++ break;
++ case 0x02:
++ val_trap = 336;
++ break;
++ case 0x03:
++ val_trap = 408;
++ break;
++ }
++
++ if (AST_default_trap_setting[chiptype].CPU_clk != val_trap)
++ {
++ printf("[ERROR] CPU CLK: Correct is %d; Real is %d \n", AST_default_trap_setting[chiptype].CPU_clk, val_trap);
++ status = FALSE;
++ }
++
++ // Check cpu_ahb_ratio
++ ulTemp = ulData;
++ ulTemp &= 0x0c00;
++ ulTemp >>= 10;
++
++ switch (ulTemp)
++ {
++ case 0x00:
++ val_trap = 1;
++ break;
++ case 0x01:
++ val_trap = 2;
++ break;
++ case 0x02:
++ val_trap = 4;
++ break;
++ case 0x03:
++ val_trap = 3;
++ break;
++ }
++
++ if (AST_default_trap_setting[chiptype].CPU_AHB_ratio != val_trap)
++ {
++ printf("[ERROR] CPU:AHB: Correct is %x:1; Real is %x:1 \n", AST_default_trap_setting[chiptype].CPU_AHB_ratio, val_trap);
++ status = FALSE;
++ }
++
++ if ( status == TRUE )
++ printf("[PASS] hardware trap for CPU clock and CPU\\AHB ratio.\n");
++
++ return status;
++}
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/TYPEDEF.H b/arch/arm/cpu/arm926ejs/aspeed/TYPEDEF.H
+new file mode 100644
+index 0000000..3053ad7
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/TYPEDEF.H
+@@ -0,0 +1,74 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef TYPEDEF_H
++#define TYPEDEF_H
++
++#include "SWFUNC.H"
++
++//
++// Define
++//
++#define PCI 1
++#define PCIE 2
++#define AGP 3
++#define ACTIVE 4
++
++#if defined(LinuxAP)
++ #ifndef FLONG
++ #define FLONG unsigned long
++ #endif
++ #ifndef ULONG
++ #define ULONG unsigned long
++ #endif
++ #ifndef LONG
++ #define LONG long
++ #endif
++ #ifndef USHORT
++ #define USHORT unsigned short
++ #endif
++ #ifndef SHORT
++ #define SHORT short
++ #endif
++ #ifndef UCHAR
++ #define UCHAR unsigned char
++ #endif
++ #ifndef CHAR
++ #define CHAR char
++ #endif
++ #ifndef BYTE
++ #define BYTE unsigned char
++ #endif
++ #ifndef VOID
++ #define VOID void
++ #endif
++ #ifndef SCHAR
++ #define SCHAR signed char
++ #endif
++#else
++/* DOS Program */
++ #define VOID void
++ #define FLONG unsigned long
++ #define ULONG unsigned long
++ #define USHORT unsigned short
++ #define UCHAR unsigned char
++ #define LONG long
++ #define SHORT short
++ #define CHAR char
++ #define BYTE UCHAR
++ #define BOOL SHORT
++ #define BOOLEAN unsigned short
++ #define PULONG ULONG *
++ #define SCHAR signed char
++#endif
++ #define TRUE 1
++ #define FALSE 0
++
++#endif // TYPEDEF_H
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/mactest.c b/arch/arm/cpu/arm926ejs/aspeed/mactest.c
+new file mode 100644
+index 0000000..95bd560
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/mactest.c
+@@ -0,0 +1,1215 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#define MACTEST_C
++static const char ThisFile[] = "MACTEST.c";
++
++#include "SWFUNC.H"
++
++#ifdef SLT_UBOOT
++ #include <common.h>
++ #include <command.h>
++ #include <post.h>
++ #include <malloc.h>
++ #include <net.h>
++ #include <COMMINF.H>
++ #include <STDUBOOT.H>
++ #include <IO.H>
++#else
++ #include <stdlib.h>
++ #include <string.h>
++ #include "LIB.H"
++ #include "COMMINF.H"
++ #include "IO.H"
++#endif
++
++const BYTE Val_Array[16] = {0,1, 2,3, 4,5, 6,7, 8,9, 10,11, 12,13, 14,15}; // AST2300-A1
++const BYTE Val_Array_A0[16] = {8,1, 10,3, 12,5, 14,7, 0,9, 2,11, 4,13, 6,15}; // AST2300-A0
++
++#ifdef SLT_UBOOT
++int main_function(int argc, char *argv[])
++#endif
++#ifdef SLT_DOS
++int main(int argc, char *argv[])
++#endif
++{
++ CHAR MAC2_Valid;
++ CHAR MAC_1GEn;
++ CHAR MAC1_RMII;
++ CHAR Enable_IntLoopPHY;
++ CHAR Disable_RecovPHY;
++ CHAR Force1G;
++ CHAR Force10M;
++ CHAR Force100M;
++ CHAR *stop_at;
++ ULONG IOStr_val;
++ ULONG IOStr_max;
++ ULONG IOStr_shf;
++ ULONG IOdly_val;
++ ULONG Err_Flag_allapeed;
++ int DES_LowNumber;
++ int index;
++ int i;
++ int j;
++ #ifdef Enable_NCSI_LOOP_INFINI
++ BYTE GSpeed_org[3];
++ #endif
++
++#ifdef SPI_BUS
++ VIDEO_ENGINE_INFO VideoEngineInfo;
++#else
++ // ( USE_P2A | USE_LPC )
++ UCHAR *ulMMIOLinearBaseAddress;
++#endif
++
++ #ifdef SLT_UBOOT
++ #else
++ time(&timestart);
++ #endif
++
++ // For DOS system
++ #if defined(PHY_NCSI)
++ // For DOS compiler OPEN WATCOM
++ ModeSwitch = MODE_NSCI;
++ #else
++ #ifdef SLT_DOS
++ ModeSwitch = MODE_DEDICATED;
++ #endif
++ #endif
++
++//------------------------------------------------------------
++// Argument Initial
++//------------------------------------------------------------
++ Err_Flag_allapeed = 0;
++ Err_Flag = 0;
++ Err_Flag_PrintEn = 1;
++ Loop_rl[0] = 0;
++ Loop_rl[1] = 0;
++ Loop_rl[2] = 0;
++
++//------------------------------------------------------------
++// Bus Initial
++//------------------------------------------------------------
++#if defined(LinuxAP)
++#else
++ //DOS system
++ #ifdef SPI_BUS
++ #endif
++ #ifdef USE_LPC
++
++ if ( findlpcport( 0x0d ) == 0) {
++ printf("Failed to find proper LPC port \n");
++
++ return(1);
++ }
++ open_aspeed_sio_password();
++ enable_aspeed_LDU( 0x0d );
++ #endif
++ #ifdef USE_P2A
++ // PCI bus
++ #ifdef DOS_PMODEW
++ if (CheckDOS()) return 1;
++ #endif
++
++ #ifdef DbgPrn_FuncHeader
++ printf ("Initial-MMIO\n");
++ Debug_delay();
++ #endif
++ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x2000, ACTIVE);
++ if ( ulPCIBaseAddress == 0 )
++ ulPCIBaseAddress = FindPCIDevice (0x1688, 0x2000, ACTIVE);
++ if ( ulPCIBaseAddress == 0 )
++ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x0200, ACTIVE);
++ if ( ulPCIBaseAddress == 0 )
++ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x3000, ACTIVE);
++ if ( ulPCIBaseAddress == 0 )
++ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x2010, ACTIVE);
++ if ( ulPCIBaseAddress == 0 ) {
++ printf ("Can't find device\n");
++
++ return(1);
++ }
++
++ WritePCIReg (ulPCIBaseAddress, 0x04, 0xFFFFFFFc, 0x3);
++ ulMMIOBaseAddress = ReadPCIReg (ulPCIBaseAddress, 0x14, 0xFFFF0000);
++ ulMMIOLinearBaseAddress = (UCHAR *)MapPhysicalToLinear (ulMMIOBaseAddress, 64 * 1024 * 1024);
++ #endif // #ifdef USE_P2A
++#endif // End defined(LinuxAP)
++
++#ifdef SPI_BUS
++ GetDevicePCIInfo (&VideoEngineInfo);
++ mmiobase = VideoEngineInfo.VGAPCIInfo.ulMMIOBaseAddress;
++ spim_init(SPI_CS);
++#else
++ // ( USE_P2A | USE_LPC )
++ mmiobase = ulMMIOLinearBaseAddress;
++#endif
++
++//------------------------------------------------------------
++// Check Chip Feature
++//------------------------------------------------------------
++ read_scu();
++
++ if (RUN_STEP >= 1) {
++ switch (SCU_7ch_old) {
++// case 0x02000003 : sprintf(ASTChipName, "[ ]AST3200-FPGA" ); ASTChipType = 6; AST1100 = 0; break;
++
++ case 0x03020003 : sprintf(ASTChipName, "[ ]AST1010-A2" ); ASTChipType = 5; AST1100 = 0; break;
++ case 0x03010003 : sprintf(ASTChipName, "[ ]AST1010-A1" ); ASTChipType = 5; AST1100 = 0; break;
++ case 0x03000003 : sprintf(ASTChipName, "[*]AST1010-A0" ); ASTChipType = 5; AST1100 = 0; break;
++
++ case 0x02010303 : sprintf(ASTChipName, "[*]AST2400-A1" ); ASTChipType = 4; AST1100 = 0; break;//AST2400-A1
++ case 0x02000303 : sprintf(ASTChipName, "[ ]AST2400-A0" ); ASTChipType = 4; AST1100 = 0; break;//AST2400-A0
++ case 0x02010103 : sprintf(ASTChipName, "[*]AST1400-A1" ); ASTChipType = 4; AST1100 = 0; break;//AST1400-A1
++ case 0x02000003 : sprintf(ASTChipName, "[ ]AST1400-A0" ); ASTChipType = 4; AST1100 = 0; break;//AST1400-A0
++
++ case 0x01010303 : sprintf(ASTChipName, "[*]AST2300-A1" ); ASTChipType = 3; AST1100 = 0; break;//AST2300-A1
++ case 0x01010203 : sprintf(ASTChipName, "[*]AST1050-A1" ); ASTChipType = 3; AST1100 = 0; break;//AST1050-A1
++ case 0x01010003 : sprintf(ASTChipName, "[*]AST1300-A1" ); ASTChipType = 3; AST1100 = 0; break;//AST1300-A1
++ case 0x01000003 : sprintf(ASTChipName, "[ ]AST2300-A0" ); ASTChipType = 3; AST1100 = 0; break;//AST2300-A0
++// case 0x01860003 : sprintf(ASTChipName, "[ ]AST2300-FPGA" ); ASTChipType = 3; AST1100 = 0; break;
++
++ case 0x00000102 : sprintf(ASTChipName, "[*]AST2200-A1" ); ASTChipType = 2; AST1100 = 0; break;//AST2200-A1/A0
++
++ case 0x00000302 : sprintf(ASTChipName, "[*]AST2100-A3" ); ASTChipType = 1; AST1100 = 0; break;//AST2100-A3/A2
++ case 0x00000301 : sprintf(ASTChipName, "[ ]AST2100-A1" ); ASTChipType = 1; AST1100 = 0; break;//AST2100-A1
++ case 0x00000300 : sprintf(ASTChipName, "[ ]AST2100-A0" ); ASTChipType = 1; AST1100 = 0; break;//AST2100-A0
++ case 0x00000202 : sprintf(ASTChipName, "[*]AST2050/AST1100-A3, AST2150-A1"); ASTChipType = 1; AST1100 = 1; break;//AST2050/AST1100-A3/A2 AST2150-A1/A0
++ case 0x00000201 : sprintf(ASTChipName, "[ ]AST2050/AST1100-A1" ); ASTChipType = 1; AST1100 = 1; break;//AST2050/AST1100-A1
++ case 0x00000200 : sprintf(ASTChipName, "[ ]AST2050/AST1100-A0" ); ASTChipType = 1; AST1100 = 1; break;//AST2050/AST1100-A0
++
++ default :
++ printf ("Error Silicon Revision ID(SCU7C) %08lx!!!\n", SCU_7ch_old);
++ return(1);
++ } // End switch (SCU_7ch_old)
++
++ switch (ASTChipType) {
++ case 6 : AST2300 = 1; AST2400 = 1; AST1010 = 0; AST3200 = 1; break;
++ case 5 : AST2300 = 1; AST2400 = 1; AST1010 = 1; AST3200 = 0; break;
++ case 4 : AST2300 = 1; AST2400 = 1; AST1010 = 0; AST3200 = 0; break;
++ case 3 : AST2300 = 1; AST2400 = 0; AST1010 = 0; AST3200 = 0; break;
++ default : AST2300 = 0; AST2400 = 0; AST1010 = 0; AST3200 = 0; break;
++ } // End switch (ASTChipType)
++
++ if (ASTChipType == 3) {
++#ifdef Force_Enable_MAC34
++ WriteSOC_DD( SCU_BASE + 0xf0, 0xAEED0001 ); //enable mac34
++ Enable_MAC34 = 1;
++#else
++ if (SCU_f0h_old & 0x00000001)
++ Enable_MAC34 = 1;
++ else
++ Enable_MAC34 = 0;
++#endif
++ }
++ else {
++ Enable_MAC34 = 0;
++ } // End if (ASTChipType == 3)
++
++ Setting_scu();
++
++//------------------------------------------------------------
++// Argument Input
++//------------------------------------------------------------
++ // Load default value
++ UserDVal = DEF_USER_DEF_PACKET_VAL;
++ IOTimingBund_arg = DEF_IOTIMINGBUND;
++ PHY_ADR_arg = DEF_PHY_ADR;
++ TestMode = DEF_TESTMODE;
++ LOOP_INFINI = 0;
++ LOOP_MAX_arg = 0;
++ GCtrl = ( DEF_MAC_LOOP_BACK << 6 ) | ( DEF_SKIP_CHECK_PHY << 5 ) | ( DEF_INIT_PHY << 3 );
++ GSpeed = DEF_SPEED;
++
++ // Get setting information by user
++ GRun_Mode = (BYTE)atoi(argv[1]);
++
++ if ( ModeSwitch == MODE_NSCI ) {
++ ARPNumCnt = DEF_ARPNUMCNT;
++ ChannelTolNum = DEF_CHANNEL2NUM;
++ PackageTolNum = DEF_PACKAGE2NUM;
++ GSpeed = SET_100MBPS; // In NCSI mode, we set to 100M bps
++ }
++
++ // Setting user's configuration
++ if (argc > 1) {
++ if ( ModeSwitch == MODE_NSCI )
++ switch (argc) {
++ case 7: ARPNumCnt = (ULONG)atoi(argv[6]);
++ case 6: IOTimingBund_arg = (BYTE)atoi(argv[5]);
++ case 5: TestMode = (BYTE)atoi(argv[4]);
++ case 4: ChannelTolNum = (BYTE)atoi(argv[3]);
++ case 3: PackageTolNum = (BYTE)atoi(argv[2]);
++ default: break;
++ }
++ else
++ switch (argc) {
++ case 9: UserDVal = strtoul (argv[8], &stop_at, 16);
++ case 8: IOTimingBund_arg = (BYTE)atoi(argv[7]);
++ case 7: PHY_ADR_arg = (BYTE)atoi(argv[6]);
++ case 6: TestMode = (BYTE)atoi(argv[5]);
++ case 5: strcpy(LOOP_Str, argv[4]);
++ if (!strcmp(LOOP_Str, "#")) LOOP_INFINI = 1;
++ else LOOP_MAX_arg = (ULONG)atoi(LOOP_Str);
++ case 4: GCtrl = (BYTE)atoi(argv[3]);
++ case 3: GSpeed = (BYTE)atoi(argv[2]);
++ default: break;
++ }
++
++ IOTimingBund = IOTimingBund_arg;
++ PHY_ADR = PHY_ADR_arg;
++ }
++ else {
++ // Wrong parameter
++ if ( ModeSwitch == MODE_NSCI ) {
++ if (AST2300)
++ printf ("\nNCSITEST.exe run_mode <package_num> <channel_num> <test_mode> <IO margin>\n\n");
++ else
++ printf ("\nNCSITEST.exe run_mode <package_num> <channel_num> <test_mode>\n\n");
++ PrintMode ();
++ PrintPakNUm();
++ PrintChlNUm();
++ PrintTest ();
++ if (AST2300)
++ PrintIOTimingBund ();
++ }
++ else {
++ if (AST2300)
++ printf ("\nMACTEST.exe run_mode <speed> <ctrl> <loop_max> <test_mode> <phy_adr> <IO margin>\n\n");
++ else
++ printf ("\nMACTEST.exe run_mode <speed> <ctrl> <loop_max> <test_mode> <phy_adr>\n\n");
++ PrintMode ();
++ PrintSpeed ();
++ PrintCtrl ();
++ PrintLoop ();
++ PrintTest ();
++ PrintPHYAdr ();
++ if (AST2300)
++ PrintIOTimingBund ();
++ }
++ Finish_Close();
++
++ return(1);
++ } // End if (argc > 1)
++
++//------------------------------------------------------------
++// Check Argument
++//------------------------------------------------------------
++ switch ( GRun_Mode ) {
++ case 0: printf ("\n[MAC1]\n"); SelectMAC = 0; H_MAC_BASE = MAC_BASE1; break;
++ case 1: printf ("\n[MAC2]\n"); SelectMAC = 1; H_MAC_BASE = MAC_BASE2; break;
++ case 2: if (Enable_MAC34) {printf ("\n[MAC3]\n"); SelectMAC = 2; H_MAC_BASE = MAC_BASE3; break;}
++ else
++ goto Error_MAC_Mode;
++ case 3: if (Enable_MAC34) {printf ("\n[MAC4]\n"); SelectMAC = 3; H_MAC_BASE = MAC_BASE4; break;}
++ else
++ goto Error_MAC_Mode;
++ default:
++Error_MAC_Mode:
++ printf ("Error run_mode!!!\n");
++ PrintMode ();
++
++ return(1);
++ } // End switch ( GRun_Mode )
++
++ H_TDES_BASE = TDES_BASE1;
++ H_RDES_BASE = RDES_BASE1;
++ MAC_PHYBASE = H_MAC_BASE;
++
++ Force1G = 0;
++ Force10M = 0;
++ Force100M = 0;
++ GSpeed_sel[0] = 0;//1G
++ GSpeed_sel[1] = 0;//100M
++ GSpeed_sel[2] = 0;//10M
++
++ switch ( GSpeed ) {
++ case SET_1GBPS : Force1G = 1; GSpeed_sel[0] = 1; break;
++ case SET_100MBPS : Force100M = 1; GSpeed_sel[1] = 1; break;
++ case SET_10MBPS : Force10M = 1; GSpeed_sel[2] = 1; break;
++ case SET_1G_100M_10MBPS : break;
++ default: printf ("Error speed!!!\n");
++ PrintSpeed ();
++ return(1);
++ } // End switch ( GSpeed )
++
++ if ( ModeSwitch == MODE_NSCI ) {
++ Enable_MACLoopback = 0; // For mactest function
++ Enable_SkipChkPHY = 0; // For mactest function
++ Enable_IntLoopPHY = 0; // For mactest function
++ Enable_InitPHY = 0; // For mactest function
++ Disable_RecovPHY = 0; // For mactest function
++ BurstEnable = 0; // For mactest function
++
++ PrintNCSIEn = (ARPNumCnt & 0x1);
++ ARPNumCnt = ARPNumCnt & 0xfffffffe;
++
++ // Check parameter
++ if ((PackageTolNum < 1) || (PackageTolNum > 8)) {
++ PrintPakNUm();
++ return(1);
++ }
++// if ((ChannelTolNum < 0) || (ChannelTolNum > 32)) {
++ if (ChannelTolNum > 32) {
++ PrintChlNUm();
++ return(1);
++ }
++
++ switch (TestMode) {
++ case 0 : NCSI_DiSChannel = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; break;
++ case 1 : NCSI_DiSChannel = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; break;
++ case 6 : if (AST2300) {NCSI_DiSChannel = 1; IOTiming = 1; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; break;}
++ else
++ goto Error_Test_Mode_NCSI;
++ case 7 : if (AST2300) {NCSI_DiSChannel = 1; IOTiming = 1; IOStrength = 1; TxDataEnable = 1; RxDataEnable = 1; break;}
++ else
++ goto Error_Test_Mode_NCSI;
++ default:
++ // Wrong parameter
++Error_Test_Mode_NCSI:
++ printf ("Error test_mode!!!\n");
++ PrintTest ();
++ return(1);
++ } // End switch (TestMode)
++ }
++ else {
++ if ( GCtrl & 0xffffff83 ) {
++ printf ("Error ctrl!!!\n");
++ PrintCtrl ();
++ return(1);
++ }
++ else {
++ Enable_MACLoopback = ( GCtrl >> 6 ) & 0x1; // ??
++ Enable_SkipChkPHY = ( GCtrl >> 5 ) & 0x1; // ??
++ Enable_IntLoopPHY = ( GCtrl >> 4 ) & 0x1;
++ Enable_InitPHY = ( GCtrl >> 3 ) & 0x1;
++ Disable_RecovPHY = ( GCtrl >> 2 ) & 0x1; // ??
++
++ if (!AST2400 && Enable_MACLoopback) {
++ printf ("Error ctrl!!!\n");
++ PrintCtrl ();
++ return(1);
++ }
++ } // End if ( GCtrl & 0xffffff83 )
++
++ if (!LOOP_MAX_arg) {
++ switch (GSpeed) {
++ case SET_1GBPS : LOOP_MAX_arg = DEF_LOOP_MAX * 200; break; // 20140325
++ case SET_100MBPS : LOOP_MAX_arg = DEF_LOOP_MAX * 20 ; break; // 20140325
++ case SET_10MBPS : LOOP_MAX_arg = DEF_LOOP_MAX * 10 ; break; // 20140325
++ case SET_1G_100M_10MBPS: LOOP_MAX_arg = DEF_LOOP_MAX * 10 ; break; // 20140325
++ }
++ } // End if (!LOOP_MAX_arg)
++
++ LOOP_MAX = LOOP_MAX_arg * 10; // 20140325
++ Calculate_LOOP_CheckNum();
++
++ switch (TestMode) {
++ case 0 : BurstEnable = 0; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; DataDelay = 0; break;
++ case 1 : BurstEnable = 1; IEEETesting = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break;
++ case 2 : BurstEnable = 1; IEEETesting = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break;
++ case 3 : BurstEnable = 1; IEEETesting = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break;
++ case 4 : BurstEnable = 1; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break; // ??
++ case 5 : BurstEnable = 1; IEEETesting = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break; // ??
++ case 6 : if (AST2300) {BurstEnable = 0; IEEETesting = 0; IOTiming = 1; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; DataDelay = 0; break;}
++ else
++ goto Error_Test_Mode;
++ case 7 : if (AST2300) {BurstEnable = 0; IEEETesting = 0; IOTiming = 1; IOStrength = 1; TxDataEnable = 1; RxDataEnable = 1; DataDelay = 0; break;}
++ else
++ goto Error_Test_Mode;
++ case 8 : BurstEnable = 0; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break; // ??
++ case 9 : BurstEnable = 0; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 0; RxDataEnable = 1; DataDelay = 0; break; // ??
++ case 10 : BurstEnable = 0; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; DataDelay = 1; break; // ??
++ default:
++Error_Test_Mode:
++ printf ("Error test_mode!!!\n");
++ PrintTest ();
++ return(1);
++ } // End switch (TestMode)
++
++ if ( PHY_ADR > 31 ) {
++ printf ("Error phy_adr!!!\n");
++ PrintPHYAdr ();
++ return(1);
++ } // End if (PHY_ADR > 31)
++ } // End if ( ModeSwitch == MODE_NSCI )
++
++ if ( BurstEnable ) {
++ IOTimingBund = 0;
++ }
++ else {
++ if ( ~DataDelay && AST2300 ) {
++ if ( !( ( (7 >= IOTimingBund) && (IOTimingBund & 0x1) ) ||
++ ( IOTimingBund == 0 ) ) ) {
++ printf ("Error IO margin!!!\n");
++ PrintIOTimingBund ();
++ return(1);
++ }
++ }
++ else {
++ IOTimingBund = 0;
++ } // End if ( ~DataDelay && AST2300 )
++
++ // Define Output file name
++ if ( ModeSwitch == MODE_NSCI )
++ sprintf(FileNameMain, "%d", SelectMAC+1);
++ else {
++ if (Enable_IntLoopPHY)
++ sprintf(FileNameMain, "%dI", SelectMAC+1);
++ else
++ sprintf(FileNameMain, "%dE", SelectMAC+1);
++ }
++
++ #ifndef SLT_UBOOT
++ if ( IOTiming ) {
++ if ( IOStrength )
++ sprintf(FileName, "MIOD%sS.log", FileNameMain);
++ else
++ sprintf(FileName, "MIOD%s.log", FileNameMain);
++
++ fp_log = fopen(FileName,"w");
++
++ if ( IOStrength )
++ sprintf(FileName, "MIO%sS.log", FileNameMain);
++ else
++ sprintf(FileName, "MIO%s.log", FileNameMain);
++
++ fp_io = fopen(FileName,"w");
++ }
++ else {
++ sprintf(FileName, "MAC%s.log", FileNameMain);
++
++ fp_log = fopen(FileName,"w");
++ }
++ #endif
++ } // End if (BurstEnable)
++
++//------------------------------------------------------------
++// Check Definition
++//------------------------------------------------------------
++ for (i = 0; i < 16; i++)
++ valary[i] = Val_Array[i];
++
++ if ( AST3200 ) {
++ MAC_Mode = (SCU_70h_old >> 6) & 0x1;
++ MAC1_1GEn = (MAC_Mode & 0x1) ? 1 : 0;//1:RGMII, 0:RMII
++ MAC2_1GEn = 0;
++
++ MAC1_RMII = !MAC1_1GEn;
++ MAC2_RMII = 0;
++ MAC2_Valid = 0;
++ }
++ else if ( AST1010 ) {
++ MAC_Mode = 0;
++ MAC1_1GEn = 0;
++ MAC2_1GEn = 0;
++
++ MAC1_RMII = 1;
++ MAC2_RMII = 0;
++ MAC2_Valid = 0;
++ }
++ else if ( AST2300 ) {
++ if (SCU_7ch_old == 0x01000003) {
++ //AST2300-A0
++ for (i = 0; i < 16; i++) {
++ valary[i] = Val_Array_A0[i];
++ }
++ }
++
++ MAC_Mode = (SCU_70h_old >> 6) & 0x3;
++ MAC1_1GEn = (MAC_Mode & 0x1) ? 1 : 0;//1:RGMII, 0:RMII
++ MAC2_1GEn = (MAC_Mode & 0x2) ? 1 : 0;//1:RGMII, 0:RMII
++
++ MAC1_RMII = !MAC1_1GEn;
++ MAC2_RMII = !MAC2_1GEn;
++ MAC2_Valid = 1;
++ }
++ else {
++ MAC_Mode = (SCU_70h_old >> 6) & 0x7;
++ MAC1_1GEn = (MAC_Mode == 0x0) ? 1 : 0;
++ MAC2_1GEn = 0;
++
++ switch ( MAC_Mode ) {
++ case 0 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 0; break; //000: Select GMII(MAC#1) only
++ case 1 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 1; break; //001: Select MII (MAC#1) and MII(MAC#2)
++ case 2 : MAC1_RMII = 1; MAC2_RMII = 0; MAC2_Valid = 1; break; //010: Select RMII(MAC#1) and MII(MAC#2)
++ case 3 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 0; break; //011: Select MII (MAC#1) only
++ case 4 : MAC1_RMII = 1; MAC2_RMII = 0; MAC2_Valid = 0; break; //100: Select RMII(MAC#1) only
++// case 5 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 0; break; //101: Reserved
++ case 6 : MAC1_RMII = 1; MAC2_RMII = 1; MAC2_Valid = 1; break; //110: Select RMII(MAC#1) and RMII(MAC#2)
++// case 7 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 0; break; //111: Disable dual MAC
++ default: return(Finish_Check(Err_MACMode));
++ }
++ } // End if ( AST3200 )
++
++ if ( SelectMAC == 0 ) {
++ Enable_RMII = MAC1_RMII;
++ MAC_1GEn = MAC1_1GEn;
++
++ if ( Force1G & !MAC1_1GEn ) {
++ printf ("\nMAC1 don't support 1Gbps !!!\n");
++ return( Finish_Check(Err_MACMode) );
++ }
++ } else if (SelectMAC == 1) {
++ Enable_RMII = MAC2_RMII;
++ MAC_1GEn = MAC2_1GEn;
++
++ if ( Force1G & !MAC2_1GEn ) {
++ printf ("\nMAC2 don't support 1Gbps !!!\n");
++ return(Finish_Check(Err_MACMode));
++ }
++ if ( !MAC2_Valid ) {
++ printf ("\nMAC2 not valid !!!\n");
++ return(Finish_Check(Err_MACMode));
++ }
++ }
++ else {
++ Enable_RMII = 1;
++ MAC_1GEn = 0;
++
++ if (Force1G) {
++ printf ("\nMAC3/MAC4 don't support 1Gbps !!!\n");
++ return(Finish_Check(Err_MACMode));
++ }
++ } // End if ( SelectMAC == 0 )
++
++ if ( ModeSwitch == MODE_NSCI ) {
++ if (!Enable_RMII) {
++ printf ("\nNCSI must be RMII interface !!!\n");
++ return(Finish_Check(Err_MACMode));
++ }
++ }
++
++ if ( GSpeed == SET_1G_100M_10MBPS ) {
++ GSpeed_sel[0] = MAC_1GEn;
++ GSpeed_sel[1] = 1;
++ GSpeed_sel[2] = 1;
++ }
++
++ if ( AST1010 ) {
++ // Check bit 13:12
++ Dat_ULONG = SCU_08h_old & 0x00003000;
++ if (Dat_ULONG != 0x00000000)
++ return(Finish_Check(Err_MHCLK_Ratio));
++ }
++ else if ( AST2300 ) {
++ Dat_ULONG = (SCU_08h_old >> 16) & 0x7;
++ if (MAC1_1GEn | MAC2_1GEn) {
++ if ( (Dat_ULONG == 0) || (Dat_ULONG > 2) )
++ return(Finish_Check(Err_MHCLK_Ratio));
++ }
++ else {
++ if (Dat_ULONG != 4)
++ return(Finish_Check(Err_MHCLK_Ratio));
++ }
++ } // End if (AST1010)
++
++ //MAC
++ MAC_08h_old = ReadSOC_DD( H_MAC_BASE + 0x08 );
++ MAC_0ch_old = ReadSOC_DD( H_MAC_BASE + 0x0c );
++ MAC_40h_old = ReadSOC_DD( H_MAC_BASE + 0x40 );
++
++ if ( ((MAC_08h_old == 0x0000) && (MAC_0ch_old == 0x00000000))
++ || ((MAC_08h_old == 0xffff) && (MAC_0ch_old == 0xffffffff))
++// || (MAC_0ch_old & 0x1)
++// || (MAC_0ch_old & 0x2)
++ )
++ {
++ // Load default for MAC address
++ SA[0] = 0x00;
++ SA[1] = 0x57;
++ SA[2] = 0x89;
++ SA[3] = 0x56;
++ SA[4] = 0x88;
++ SA[5] = 0x38;
++ }
++ else {
++ SA[0] = (MAC_08h_old >> 8) & 0xff;
++ SA[1] = (MAC_08h_old ) & 0xff;
++ SA[2] = (MAC_0ch_old >> 24) & 0xff;
++ SA[3] = (MAC_0ch_old >> 16) & 0xff;
++ SA[4] = (MAC_0ch_old >> 8) & 0xff;
++ SA[5] = (MAC_0ch_old ) & 0xff;
++ }
++ // printf ("%08x %08x: %02x %02x %02x %02x %02x %02x\n", MAC_08h_old, MAC_0ch_old, SA[0], SA[1], SA[2], SA[3], SA[4], SA[5]);
++
++ if ( AST2300 ) {
++#ifdef Force_Enable_NewMDIO
++ AST2300_NewMDIO = 1;
++ WriteSOC_DD(H_MAC_BASE+0x40, MAC_40h_old | 0x80000000)
++#else
++ AST2300_NewMDIO = (MAC_40h_old & 0x80000000) ? 1 : 0;
++#endif
++ }
++ else {
++ AST2300_NewMDIO = 0;
++ } // End if (AST2300)
++
++//------------------------------------------------------------
++// Parameter Initial
++//------------------------------------------------------------
++ if ( AST3200 ) {
++ SCU_04h = 0x0c000800; //Reset Engine
++ }
++ else if (AST1010) {
++ SCU_04h = 0x00000010; //Reset Engine
++ }
++ else if (AST2300) {
++ SCU_04h = 0x0c001800; //Reset Engine
++ }
++ else {
++ SCU_04h = 0x00001800; //Reset Engine
++ } // End if ( AST3200 )
++
++ if ( ModeSwitch == MODE_NSCI )
++ // Set to 100Mbps and Enable RX broabcast packets and CRC_APD and Full duplex
++ MAC_50h = 0x000a0500;
++ else {
++ // RX_ALLADR and CRC_APD and Full duplex
++ MAC_50h = 0x00004500;
++
++ #ifdef Enable_Runt
++ MAC_50h = MAC_50h | 0x00001000;
++ #endif
++
++ #ifdef Enable_Jumbo
++ MAC_50h = MAC_50h | 0x00002000;
++ #endif
++ } // End if ( ModeSwitch == MODE_NSCI )
++
++//------------------------------------------------------------
++// Descriptor Number
++//------------------------------------------------------------
++ if ( ModeSwitch == MODE_DEDICATED ) {
++
++ #ifdef Enable_Jumbo
++ DES_LowNumber = 1;
++ #else
++ DES_LowNumber = IOTiming;
++ #endif
++ if ( Enable_SkipChkPHY && ( TestMode == 0 ) ) {
++ DES_NUMBER = 114;//for SMSC's LAN9303 issue
++ }
++ else {
++ if ( AST1010 | AST3200 ) {
++ DES_NUMBER = (IOTimingBund) ? 100 : 256;
++ }
++ else {
++ switch ( GSpeed ) {
++ case SET_1GBPS : DES_NUMBER = (IOTimingBund) ? 10 : (DES_LowNumber) ? 50 : 400; break; // 20140325
++ case SET_100MBPS : DES_NUMBER = (IOTimingBund) ? 10 : (DES_LowNumber) ? 50 : 400; break; // 20140325
++ case SET_10MBPS : DES_NUMBER = (IOTimingBund) ? 10 : (DES_LowNumber) ? 10 : 80; break; // 20140325
++ case SET_1G_100M_10MBPS : DES_NUMBER = (IOTimingBund) ? 10 : (DES_LowNumber) ? 10 : 80; break; // 20140325
++ }
++ } // End if ( Enable_SkipChkPHY && ( TestMode == 0 ) )
++ }
++
++ #ifdef SelectDesNumber
++ DES_NUMBER = SelectDesNumber;
++ #endif
++
++ #ifdef USE_LPC
++ DES_NUMBER /= 8;
++ #endif
++
++ #ifdef ENABLE_ARP_2_WOL
++ if ( TestMode == 4 ) {
++ DES_NUMBER = 1;
++ }
++ #endif
++
++ DES_NUMBER_Org = DES_NUMBER;
++
++ if ( DbgPrn_Info ) {
++ printf ("CheckBuf_MBSize : %ld\n", CheckBuf_MBSize);
++ printf ("LOOP_CheckNum : %ld\n", LOOP_CheckNum);
++ printf ("DES_NUMBER : %ld\n", DES_NUMBER);
++ printf ("DMA_BufSize : %ld bytes\n", DMA_BufSize);
++ printf ("DMA_BufNum : %d\n", DMA_BufNum);
++ printf ("\n");
++ }
++// if (3 > DMA_BufNum)
++// return( Finish_Check(Err_DMABufNum) );
++
++ if (2 > DMA_BufNum)
++ return( Finish_Check(Err_DMABufNum) );
++ } // End if ( ModeSwitch == MODE_DEDICATED )
++ } // End if (RUN_STEP >= 1)
++
++//------------------------------------------------------------
++// SCU Initial
++//------------------------------------------------------------
++ if ( RUN_STEP >= 2 ) {
++ init_scu1();
++ }
++
++ if ( RUN_STEP >= 3 ) {
++ init_scu_macrst();
++ }
++
++//------------------------------------------------------------
++// Data Initial
++//------------------------------------------------------------
++ if (RUN_STEP >= 4) {
++ setup_arp();
++ if ( ModeSwitch == MODE_DEDICATED ) {
++
++ FRAME_LEN = (ULONG *)malloc(DES_NUMBER * sizeof( ULONG ));
++ wp_lst = (ULONG *)malloc(DES_NUMBER * sizeof( ULONG ));
++
++ if ( !FRAME_LEN )
++ return( Finish_Check( Err_MALLOC_FrmSize ) );
++
++ if ( !wp_lst )
++ return( Finish_Check( Err_MALLOC_LastWP ));
++
++ // Setup data and length
++ TestingSetup();
++ } // End if ( ModeSwitch == MODE_DEDICATED )
++
++ // Get bit (shift) of IO driving strength register
++ if ( IOStrength ) {
++ if (AST1010) {
++ IOStr_max = 1;//0~1
++ }
++ else if (AST2400) {
++ IOStr_max = 1;//0~1
++ switch (SelectMAC) {
++ case 0 : IOStr_shf = 9; break;
++ case 1 : IOStr_shf = 11; break;
++ }
++ }
++ else {
++ IOStr_max = 3;//0~3
++ switch (SelectMAC) {
++ case 0 : IOStr_shf = 8; break;
++ case 1 : IOStr_shf = 10; break;
++ case 2 : IOStr_shf = 12; break;
++ case 3 : IOStr_shf = 14; break;
++ }
++ }
++ }
++ else {
++ IOStr_max = 0;
++ IOStr_shf = 0;
++ } // End if (IOStrength)
++
++ // Get current clock delay value of TX(out) and RX(in) in the SCU48 register
++ // and setting test range
++ if ( Enable_RMII ) {
++ switch (GRun_Mode) {
++ case 0 : IOdly_out_shf = 24; IOdly_in_shf = 8; break;
++ case 1 : IOdly_out_shf = 25; IOdly_in_shf = 12; break;
++ case 2 : IOdly_out_shf = 26; IOdly_in_shf = 16; break;
++ case 3 : IOdly_out_shf = 27; IOdly_in_shf = 20; break;
++ }
++ IOdly_in_reg = (SCU_48h_old >> IOdly_in_shf ) & 0xf;
++ IOdly_out_reg = (SCU_48h_old >> IOdly_out_shf) & 0x1;
++ }
++ else {
++ switch (GRun_Mode) {
++ case 0 : IOdly_out_shf = 0; IOdly_in_shf = 8; break;
++ case 1 : IOdly_out_shf = 4; IOdly_in_shf = 12; break;
++ }
++ IOdly_in_reg = (SCU_48h_old >> IOdly_in_shf ) & 0xf;
++ IOdly_out_reg = (SCU_48h_old >> IOdly_out_shf) & 0xf;
++ } // End if ( Enable_RMII )
++
++ // Find the coordinate in X-Y axis
++ for ( index = 0; index <= 15; index++ )
++ if ( IOdly_in_reg == valary[index] ) {
++ IOdly_in_reg_idx = index;
++ break;
++ }
++ for ( index = 0; index <= 15; index++ )
++ if ( IOdly_out_reg == valary[index] ) {
++ IOdly_out_reg_idx = index;
++ break;
++ }
++
++ // Get the range for testmargin block
++ if ( IOTiming ) {
++ if ( Enable_RMII ) {
++ IOdly_incval = 1;
++ IOdly_in_str = 0;
++ IOdly_in_end = 15;
++ IOdly_out_str = 0;
++ IOdly_out_end = 1;
++ }
++ else {
++ IOdly_incval = 1;
++ IOdly_in_str = 0;
++ IOdly_in_end = 15;
++ IOdly_out_str = 0;
++ IOdly_out_end = 15;
++ }
++ }
++ else if ( IOTimingBund ) {
++ if ( Enable_RMII ) {
++ IOdly_incval = 1;
++ IOdly_in_str = IOdly_in_reg_idx - ( IOTimingBund >> 1 );
++ IOdly_in_end = IOdly_in_reg_idx + ( IOTimingBund >> 1 );
++ IOdly_out_str = IOdly_out_reg_idx;
++ IOdly_out_end = IOdly_out_reg_idx;
++ }
++ else {
++ IOdly_incval = 1;
++ IOdly_in_str = IOdly_in_reg_idx - ( IOTimingBund >> 1 );
++ IOdly_in_end = IOdly_in_reg_idx + ( IOTimingBund >> 1 );
++ IOdly_out_str = IOdly_out_reg_idx - ( IOTimingBund >> 1 );
++ IOdly_out_end = IOdly_out_reg_idx + ( IOTimingBund >> 1 );
++ }
++ if ((IOdly_in_str < 0) || (IOdly_in_end > 15))
++ return( Finish_Check( Err_IOMarginOUF ) );
++
++ if ((IOdly_out_str < 0) || (IOdly_out_end > 15))
++ return( Finish_Check( Err_IOMarginOUF ) );
++
++// if (IOdly_in_str < 0) IOdly_in_str = 0;
++// if (IOdly_in_end > 15) IOdly_in_end = 15;
++// if (IOdly_out_str < 0) IOdly_out_str = 0;
++// if (IOdly_out_end > 15) IOdly_out_end = 15;
++ }
++ else {
++ IOdly_incval = 1;
++ IOdly_in_str = 0;
++ IOdly_in_end = 0;
++ IOdly_out_str = 0;
++ IOdly_out_end = 0;
++ } // End if (IOTiming)
++ } // End if (RUN_STEP >= 4)
++
++//------------------------------------------------------------
++// main
++//------------------------------------------------------------
++ if (RUN_STEP >= 5) {
++ #ifdef DbgPrn_FuncHeader
++ printf ("GSpeed_sel: %d %d %d\n", GSpeed_sel[0], GSpeed_sel[1], GSpeed_sel[2]);
++ Debug_delay();
++ #endif
++
++ if ( ModeSwitch == MODE_NSCI ) {
++ #ifdef Enable_NCSI_LOOP_INFINI
++ for ( GSpeed_idx = 0; GSpeed_idx < 3; GSpeed_idx++ ) {
++ GSpeed_org[GSpeed_idx] = GSpeed_sel[GSpeed_idx];
++ }
++NCSI_LOOP_INFINI:;
++ for ( GSpeed_idx = 0; GSpeed_idx < 3; GSpeed_idx++ ) {
++ GSpeed_sel[GSpeed_idx] = GSpeed_org[GSpeed_idx];
++ }
++ #endif
++ } // End if ( ModeSwitch == MODE_NSCI )
++
++ for (GSpeed_idx = 0; GSpeed_idx < 3; GSpeed_idx++) {
++ Err_Flag_PrintEn = 1;
++ if ( GSpeed_sel[GSpeed_idx] ) {
++ // Setting the LAN speed
++ if ( ModeSwitch == MODE_DEDICATED ) {
++
++
++ // Test three speed of LAN, we will modify loop number
++ if (GSpeed == SET_1G_100M_10MBPS) {
++ if (GSpeed_sel[0]) LOOP_MAX = LOOP_MAX_arg;
++ else if (GSpeed_sel[1]) LOOP_MAX = LOOP_MAX_arg / 10;
++ else LOOP_MAX = LOOP_MAX_arg / 100;
++
++ if ( !LOOP_MAX )
++ LOOP_MAX = 1;
++
++ Calculate_LOOP_CheckNum();
++ }
++
++ // Setting speed of LAN
++ if (GSpeed_sel[0]) MAC_50h_Speed = 0x00000200;
++ else if (GSpeed_sel[1]) MAC_50h_Speed = 0x00080000;
++ else MAC_50h_Speed = 0x00000000;
++
++ //------------------------------------------------------------
++ // PHY Initial
++ //------------------------------------------------------------
++ if ( AST1100 )
++ init_scu2();
++
++ if ( Enable_InitPHY ) {
++#ifdef SUPPORT_PHY_LAN9303
++ LAN9303(LAN9303_I2C_BUSNUM, PHY_ADR_arg, GSpeed_idx, Enable_IntLoopPHY | (BurstEnable<<1) | IEEETesting);
++#else
++ init_phy( Enable_IntLoopPHY );
++#endif
++ DELAY( Delay_PHYRst * 10 );
++ } // End if (Enable_InitPHY)
++
++ if ( AST1100 )
++ init_scu3();
++
++ if ( Err_Flag )
++ return( Finish_Check( 0 ) );
++ } // End if ( ModeSwitch == MODE_DEDICATED )
++
++ //------------------------------------------------------------
++ // Start
++ //------------------------------------------------------------
++
++ // The loop is for different IO strength
++ for ( IOStr_i = 0; IOStr_i <= IOStr_max; IOStr_i++ ) {
++
++ // Print Header of report to monitor and log file
++ if ( IOTiming || IOTimingBund ) {
++ if ( IOStrength ) {
++ if ( AST1010 ) {
++ IOStr_val = (SCU_ach_old & 0xfff0ffff) | ((IOStr_i) ? 0xf0000 : 0x0);
++ }
++ else {
++ IOStr_val = (SCU_90h_old & 0xffff00ff) | (IOStr_i << IOStr_shf);
++ }
++ //printf("\nIOStrength_val= %08x, ", IOStr_val);
++ //printf("SCU90h: %08x ->", ReadSOC_DD(SCU_BASE+0x90));
++ WriteSOC_DD( SCU_BASE + 0x90, IOStr_val );
++ //printf(" %08x\n", ReadSOC_DD(SCU_BASE+0x90));
++
++ #ifndef SLT_UBOOT
++ if (GSpeed_sel[0]) fprintf(fp_log, "[Strength %d][1G ]========================================\n", IOStr_i);
++ else if (GSpeed_sel[1]) fprintf(fp_log, "[Strength %d][100M]========================================\n", IOStr_i);
++ else fprintf(fp_log, "[Strength %d][10M ]========================================\n", IOStr_i);
++ #endif
++ }
++ else {
++ #ifndef SLT_UBOOT
++ if (GSpeed_sel[0]) fprintf(fp_log, "[1G ]========================================\n");
++ else if (GSpeed_sel[1]) fprintf(fp_log, "[100M]========================================\n");
++ else fprintf(fp_log, "[10M ]========================================\n");
++ #endif
++ }
++
++ if ( IOTimingBund )
++ PrintIO_Header(FP_LOG);
++ if ( IOTiming )
++ PrintIO_Header(FP_IO);
++
++ PrintIO_Header(STD_OUT);
++
++ }
++ else {
++ if ( ModeSwitch == MODE_DEDICATED ) {
++
++ if (!BurstEnable)
++ Print_Header(FP_LOG);
++
++ Print_Header(STD_OUT);
++ }
++ } // End if (IOTiming || IOTimingBund)
++
++#ifdef Enable_Old_Style
++ for (IOdly_i = IOdly_in_str; IOdly_i <= IOdly_in_end; IOdly_i+=IOdly_incval) {
++ IOdly_in = valary[IOdly_i];
++#else
++ for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) {
++ IOdly_out = valary[IOdly_j];
++#endif
++
++ if (IOTiming || IOTimingBund) {
++#ifdef Enable_Fast_SCU
++ #ifdef Enable_Old_Style
++ WriteSOC_DD(SCU_BASE + 0x48, SCU_48h_mix | (IOdly_in << IOdly_in_shf));
++ #else
++ WriteSOC_DD(SCU_BASE + 0x48, SCU_48h_mix | (IOdly_out << IOdly_out_shf));
++ #endif
++#endif
++
++ if ( IOTimingBund )
++ PrintIO_LineS(FP_LOG);
++ if ( IOTiming )
++ PrintIO_LineS(FP_IO);
++
++ PrintIO_LineS(STD_OUT);
++ } // End if (IOTiming || IOTimingBund)
++
++ //------------------------------------------------------------
++ // SCU Initial
++ //------------------------------------------------------------
++#ifdef Enable_Fast_SCU
++ init_scu_macrst();
++#endif
++#ifdef Enable_Old_Style
++ for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) {
++ IOdly_out = valary[IOdly_j];
++#else
++ for (IOdly_i = IOdly_in_str; IOdly_i <= IOdly_in_end; IOdly_i+=IOdly_incval) {
++ IOdly_in = valary[IOdly_i];
++#endif
++ if ( IOTiming || IOTimingBund ) {
++ IOdly_val = (IOdly_in << IOdly_in_shf) | (IOdly_out << IOdly_out_shf);
++
++//printf("\nIOdly_val= %08x, ", IOdly_val);
++//printf("SCU48h: %08x ->", ReadSOC_DD( SCU_BASE + 0x48 ) );
++ WriteSOC_DD( SCU_BASE + 0x48, SCU_48h_mix | IOdly_val );
++//printf(" %08x\n", ReadSOC_DD(SCU_BASE+0x48));
++ } // End if (IOTiming || IOTimingBund)
++
++ //------------------------------------------------------------
++ // SCU Initial
++ //------------------------------------------------------------
++#ifdef Enable_Fast_SCU
++#else
++ init_scu_macrst();
++#endif
++
++ //------------------------------------------------------------
++ // MAC Initial
++ //------------------------------------------------------------
++ init_mac(H_MAC_BASE, H_TDES_BASE, H_RDES_BASE);
++ if ( Err_Flag )
++ return( Finish_Check(0) );
++
++ // Testing
++ if ( ModeSwitch == MODE_NSCI )
++ dlymap[IOdly_i][IOdly_j] = phy_ncsi();
++ else
++ dlymap[IOdly_i][IOdly_j] = TestingLoop(LOOP_CheckNum);
++
++
++ // Display to Log file and monitor
++ if ( IOTiming || IOTimingBund ) {
++
++ if ( IOTimingBund )
++ PrintIO_Line(FP_LOG);
++
++ if ( IOTiming )
++ PrintIO_Line(FP_IO);
++
++ PrintIO_Line(STD_OUT);
++
++ // Find the range of current setting
++ if ( ( IOdly_in_reg == IOdly_in ) && ( IOdly_out_reg == IOdly_out ) ) {
++ IOdly_i_min = IOdly_i - ( IOTimingBund >> 1 );
++ IOdly_i_max = IOdly_i + ( IOTimingBund >> 1 );
++
++ if ( Enable_RMII ) {
++ IOdly_j_min = IOdly_j;
++ IOdly_j_max = IOdly_j;
++ }
++ else {
++ IOdly_j_min = IOdly_j - (IOTimingBund >> 1 );
++ IOdly_j_max = IOdly_j + (IOTimingBund >> 1 );
++ }
++ }
++
++ PrintIO_Line_LOG();
++ FPri_ErrFlag(FP_LOG);
++
++// Err_Flag_allapeed = Err_Flag_allapeed | Err_Flag;
++ Err_Flag = 0;
++ }
++ }// End for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval)
++#ifndef SLT_UBOOT
++ if ( IOTiming || IOTimingBund ) {
++ if ( IOTimingBund )
++ fprintf(fp_log, "\n");
++ if (IOTiming )
++ fprintf(fp_io, "\n");
++ }
++#endif
++ printf("\n");
++ } // End for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval)
++
++ //------------------------------------------------------------
++ // End
++ //------------------------------------------------------------
++
++ if ( IOTiming || IOTimingBund ) {
++ if ( ( IOdly_i_min < 0 ) || ( IOdly_i_max > 15 ) )
++ FindErr(Err_IOMarginOUF);
++ if ( ( IOdly_j_min < 0 ) || ( IOdly_j_max > 15 ) )
++ FindErr(Err_IOMarginOUF);
++
++ if ( IOdly_i_min < 0 ) IOdly_i_min = 0;
++ if ( IOdly_i_max > 15 ) IOdly_i_max = 15;
++ if ( IOdly_j_min < 0 ) IOdly_j_min = 0;
++ if ( IOdly_j_max > 15 ) IOdly_j_max = 15;
++
++#ifdef Enable_Old_Style
++ for (IOdly_i = IOdly_i_min; IOdly_i <= IOdly_i_max; IOdly_i++)
++ for (IOdly_j = IOdly_j_min; IOdly_j <= IOdly_j_max; IOdly_j++)
++#else
++ for (IOdly_j = IOdly_j_min; IOdly_j <= IOdly_j_max; IOdly_j++)
++ for (IOdly_i = IOdly_i_min; IOdly_i <= IOdly_i_max; IOdly_i++)
++#endif
++ {
++ if ( dlymap[IOdly_i][IOdly_j] ) {
++#ifdef SLT_DOS
++ if ( IOTiming ) {
++#ifdef Enable_Old_Style
++ for (i = IOdly_i_min; i <= IOdly_i_max; i++)
++#else
++ for (j = IOdly_j_min; j <= IOdly_j_max; j++)
++#endif
++ {
++#ifdef Enable_Old_Style
++ for (j = IOdly_j_min; j <= IOdly_j_max; j++)
++#else
++ for (i = IOdly_i_min; i <= IOdly_i_max; i++)
++#endif
++ {
++ if (dlymap[i][j]) fprintf(fp_io, "x ");
++ else fprintf(fp_io, "o ");
++ }
++ fprintf(fp_io, "\n");
++ }
++ } // End if ( IOTiming )
++#endif // End SLT_DOS
++ FindErr(Err_IOMargin);
++ goto Find_Err_IOMargin;
++ } // End if ( dlymap[IOdly_i][IOdly_j] )
++ }
++ } // End if ( IOTiming || IOTimingBund )
++
++Find_Err_IOMargin:;
++ if ( !BurstEnable )
++ FPri_ErrFlag(FP_LOG);
++ if ( IOTiming )
++ FPri_ErrFlag(FP_IO);
++
++ FPri_ErrFlag(STD_OUT);
++
++ Err_Flag_allapeed = Err_Flag_allapeed | Err_Flag;
++ Err_Flag = 0;
++ } // End for (IOStr_i = 0; IOStr_i <= IOStr_max; IOStr_i++)
++
++ if ( ModeSwitch == MODE_DEDICATED ) {
++ if ( Enable_InitPHY & !Disable_RecovPHY )
++ recov_phy(Enable_IntLoopPHY);
++ }
++
++ GSpeed_sel[GSpeed_idx] = 0;
++ } // End if (GSpeed_sel[GSpeed_idx])
++
++ Err_Flag_PrintEn = 0;
++ } // End for (GSpeed_idx = 0; GSpeed_idx < 3; GSpeed_idx++)
++
++ Err_Flag = Err_Flag_allapeed;
++
++ if ( ModeSwitch == MODE_NSCI ) {
++ #ifdef Enable_NCSI_LOOP_INFINI
++ if (Err_Flag == 0) {
++ if (fp_log) {
++ fclose(fp_log);
++ fp_log = fopen(FileName,"w");
++ }
++ goto NCSI_LOOP_INFINI;
++ }
++ #endif
++ }
++
++ } // End if (RUN_STEP >= 5)
++
++ return(Finish_Check(0));
++
++}
++
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/reset.c b/arch/arm/cpu/arm926ejs/aspeed/reset.c
+new file mode 100644
+index 0000000..e0a57f9
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/reset.c
+@@ -0,0 +1,24 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#include <common.h>
++#include <asm/io.h>
++
++#define AST_WDT_BASE 0x1e785000
++void reset_cpu(ulong addr)
++{
++ __raw_writel(0x10 , AST_WDT_BASE+0x04);
++ __raw_writel(0x4755, AST_WDT_BASE+0x08);
++ __raw_writel(0x3, AST_WDT_BASE+0x0c);
++
++ while (1)
++ /*nothing*/;
++}
+diff --git a/arch/arm/cpu/arm926ejs/aspeed/timer.c b/arch/arm/cpu/arm926ejs/aspeed/timer.c
+new file mode 100644
+index 0000000..4bba5c5
+--- /dev/null
++++ b/arch/arm/cpu/arm926ejs/aspeed/timer.c
+@@ -0,0 +1,153 @@
++/*
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <arm926ejs.h>
++
++#define TIMER_LOAD_VAL 0xffffffff
++
++/* macro to read the 32 bit timer */
++#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+0))
++
++static ulong timestamp;
++static ulong lastdec;
++
++int timer_init (void)
++{
++ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 4) = TIMER_LOAD_VAL;
++ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x30) = 0x3; /* enable timer1 */
++
++ /* init the timestamp and lastdec value */
++ reset_timer_masked();
++
++ return 0;
++}
++
++/*
++ * timer without interrupts
++ */
++
++void reset_timer (void)
++{
++ reset_timer_masked ();
++}
++
++ulong get_timer (ulong base)
++{
++ return get_timer_masked () - base;
++}
++
++void set_timer (ulong t)
++{
++ timestamp = t;
++}
++
++/* delay x useconds AND perserve advance timstamp value */
++void udelay (unsigned long usec)
++{
++ ulong tmo, tmp;
++
++ if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
++ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
++ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
++ tmo /= 1000; /* finish normalize. */
++ }else{ /* else small number, don't kill it prior to HZ multiply */
++ tmo = usec * CONFIG_SYS_HZ;
++ tmo /= (1000*1000);
++ }
++
++ tmp = get_timer (0); /* get current timestamp */
++ if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */
++ reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */
++ else
++ tmo += tmp; /* else, set advancing stamp wake up time */
++
++ while (get_timer_masked () < tmo)/* loop till event */
++ /*NOP*/;
++}
++
++void reset_timer_masked (void)
++{
++ /* reset time */
++ lastdec = READ_TIMER; /* capure current decrementer value time */
++ timestamp = 0; /* start "advancing" time stamp from 0 */
++}
++
++ulong get_timer_masked (void)
++{
++ ulong now = READ_TIMER; /* current tick value */
++
++ if (lastdec >= now) { /* normal mode (non roll) */
++ /* normal mode */
++ timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
++ } else { /* we have overflow of the count down timer */
++ /* nts = ts + ld + (TLV - now)
++ * ts=old stamp, ld=time that passed before passing through -1
++ * (TLV-now) amount of time after passing though -1
++ * nts = new "advancing time stamp"...it could also roll and cause problems.
++ */
++ timestamp += lastdec + TIMER_LOAD_VAL - now;
++ }
++ lastdec = now;
++
++ return timestamp;
++}
++
++/* waits specified delay value and resets timestamp */
++void udelay_masked (unsigned long usec)
++{
++ ulong tmo;
++ ulong endtime;
++ signed long diff;
++
++ if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
++ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
++ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
++ tmo /= 1000; /* finish normalize. */
++ } else { /* else small number, don't kill it prior to HZ multiply */
++ tmo = usec * CONFIG_SYS_HZ;
++ tmo /= (1000*1000);
++ }
++
++ endtime = get_timer_masked () + tmo;
++
++ do {
++ ulong now = get_timer_masked ();
++ diff = endtime - now;
++ } while (diff >= 0);
++}
++
++/*
++ * This function is derived from PowerPC code (read timebase as long long).
++ * On ARM it just returns the timer value.
++ */
++unsigned long long get_ticks(void)
++{
++ return get_timer(0);
++}
++
++/*
++ * This function is derived from PowerPC code (timebase clock frequency).
++ * On ARM it returns the number of timer ticks per second.
++ */
++ulong get_tbclk (void)
++{
++ ulong tbclk;
++
++ tbclk = CONFIG_SYS_HZ;
++ return tbclk;
++}
+diff --git a/arch/arm/include/asm/arch-aspeed/aspeed_i2c.h b/arch/arm/include/asm/arch-aspeed/aspeed_i2c.h
+new file mode 100644
+index 0000000..5419fca
+--- /dev/null
++++ b/arch/arm/include/asm/arch-aspeed/aspeed_i2c.h
+@@ -0,0 +1,69 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#if defined(CONFIG_AST1300)
++#define SCU_BASE CONFIG_SCUREG_BASE
++#define I2C_BASE CONFIG_I2CREG_BASE
++#define I2C_CHANNEL CONFIG_I2C_CHANNEL
++#else
++#define SCU_BASE 0x1E6E2000
++#define I2C_BASE 0x1E78A000
++/* Cause U-boot i2c command limitation, it can't assign channel number. Our EEPROM is at channel 3 now*/
++/* AST2200's EEPROM is at channel 4 */
++#if defined(CONFIG_AST2200) || defined(CONFIG_AST2300) || defined(CONFIG_AST2400)
++#define I2C_CHANNEL 4
++#else
++#define I2C_CHANNEL 3
++#endif
++#endif
++
++/* Fix timing for EEPROM 100Khz*/
++#define AC_TIMING 0x77743335
++#define ALL_CLEAR 0xFFFFFFFF
++#define MASTER_ENABLE 0x01
++#define SLAVE_ENABLE 0x02
++#define LOOP_COUNT 0x100000
++#define SCU_RESET_CONTROL 0x04
++#define SCU_MULTIFUNCTION_PIN_CTL5_REG 0x90
++
++/* I2C Register */
++#define I2C_FUNCTION_CONTROL_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x00)
++#define I2C_AC_TIMING_REGISTER_1 (I2C_BASE + I2C_CHANNEL * 0x40 + 0x04)
++#define I2C_AC_TIMING_REGISTER_2 (I2C_BASE + I2C_CHANNEL * 0x40 + 0x08)
++#define I2C_INTERRUPT_CONTROL_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x0c)
++#define I2C_INTERRUPT_STATUS_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x10)
++#define I2C_COMMAND_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x14)
++#define I2C_DEVICE_ADDRESS_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x18)
++#define I2C_BUFFER_CONTROL_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x1c)
++#define I2C_BYTE_BUFFER_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x20)
++#define I2C_DMA_CONTROL_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x24)
++#define I2C_DMA_STATUS_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x28)
++
++/* Command Bit */
++#define MASTER_START_COMMAND (1 << 0)
++#define MASTER_TX_COMMAND (1 << 1)
++#define MASTER_RX_COMMAND (1 << 3)
++#define RX_COMMAND_LIST (1 << 4)
++#define MASTER_STOP_COMMAND (1 << 5)
++
++/* Interrupt Status Bit */
++#define TX_ACK (1 << 0)
++#define TX_NACK (1 << 1)
++#define RX_DONE (1 << 2)
++#define STOP_DONE (1 << 4)
++
++/* Macros to access registers */
++#define outb(v,p) *(volatile u8 *) (p) = v
++#define outw(v,p) *(volatile u16 *) (p) = v
++#define outl(v,p) *(volatile u32 *) (p) = v
++
++#define inb(p) *(volatile u8 *) (p)
++#define inw(p) *(volatile u16 *) (p)
++#define inl(p) *(volatile u32 *) (p)
+diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
+index 440b041..48fcf2b 100644
+--- a/arch/arm/include/asm/mach-types.h
++++ b/arch/arm/include/asm/mach-types.h
+@@ -175,6 +175,16 @@ extern unsigned int __machine_arch_type;
+ #define MACH_TYPE_PALMTX 885
+ #define MACH_TYPE_S3C2413 887
+ #define MACH_TYPE_WG302V2 890
++#define MACH_TYPE_AST1100 903
++#define MACH_TYPE_AST2000 900
++#define MACH_TYPE_AST2100 902
++#define MACH_TYPE_AST2150 907
++#define MACH_TYPE_AST2200 906
++#define MACH_TYPE_AST2300_FPGA_1 901
++#define MACH_TYPE_AST2300_FPGA_2 901
++#define MACH_TYPE_AST2300 901
++#define MACH_TYPE_AST3100 901
++#define MACH_TYPE_ASPEED 8888
+ #define MACH_TYPE_OMAP_2430SDP 900
+ #define MACH_TYPE_DAVINCI_EVM 901
+ #define MACH_TYPE_PALMZ72 904
+@@ -840,7 +850,6 @@ extern unsigned int __machine_arch_type;
+ #define MACH_TYPE_NV1000 3218
+ #define MACH_TYPE_NUC950TS 3219
+ #define MACH_TYPE_NOKIA_RM680 3220
+-#define MACH_TYPE_AST2200 3221
+ #define MACH_TYPE_LEAD 3222
+ #define MACH_TYPE_UNINO1 3223
+ #define MACH_TYPE_GREECO 3224
+@@ -3063,6 +3072,126 @@ extern unsigned int __machine_arch_type;
+ # define machine_is_wg302v2() (0)
+ #endif
+
++#ifdef CONFIG_MACH_AST1100
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_AST1100
++# endif
++# define machine_is_ast1100() (machine_arch_type == MACH_TYPE_AST1100)
++#else
++# define machine_is_ast1100() (0)
++#endif
++
++#ifdef CONFIG_MACH_AST2000
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_AST2000
++# endif
++# define machine_is_ast2000() (machine_arch_type == MACH_TYPE_AST2000)
++#else
++# define machine_is_ast2000() (0)
++#endif
++
++#ifdef CONFIG_MACH_AST2100
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_AST2100
++# endif
++# define machine_is_ast2100() (machine_arch_type == MACH_TYPE_AST2100)
++#else
++# define machine_is_ast2100() (0)
++#endif
++
++#ifdef CONFIG_MACH_AST2150
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_AST2150
++# endif
++# define machine_is_ast2150() (machine_arch_type == MACH_TYPE_AST2150)
++#else
++# define machine_is_ast2150() (0)
++#endif
++
++#ifdef CONFIG_MACH_AST2200
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_AST2200
++# endif
++# define machine_is_ast2200() (machine_arch_type == MACH_TYPE_AST2200)
++#else
++# define machine_is_ast2200() (0)
++#endif
++
++#ifdef CONFIG_MACH_AST2300_FPGA_1
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_AST2300_FPGA_1
++# endif
++# define machine_is_ast2300_fpga_1() (machine_arch_type == MACH_TYPE_AST2300_FPGA_1)
++#else
++# define machine_is_ast2300_fpga_1() (0)
++#endif
++
++#ifdef CONFIG_MACH_AST2300_FPGA_2
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_AST2300_FPGA_2
++# endif
++# define machine_is_ast2300_fpga_2() (machine_arch_type == MACH_TYPE_AST2300_FPGA_2)
++#else
++# define machine_is_ast2300_fpga_2() (0)
++#endif
++
++#ifdef CONFIG_MACH_AST3100
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_AST3100
++# endif
++# define machine_is_ast3100() (machine_arch_type == MACH_TYPE_AST3100)
++#else
++# define machine_is_ast3100() (0)
++#endif
++
++#ifdef CONFIG_MACH_ASPEED
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_ASPEED
++# endif
++# define machine_is_aspeed() (machine_arch_type == MACH_TYPE_ASPEED)
++#else
++# define machine_is_aspeed() (0)
++#endif
++
++#ifdef CONFIG_MACH_AST2300
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_AST2300
++# endif
++# define machine_is_ast2300() (machine_arch_type == MACH_TYPE_AST2300)
++#else
++# define machine_is_ast2300() (0)
++#endif
++
+ #ifdef CONFIG_MACH_OMAP_2430SDP
+ # ifdef machine_arch_type
+ # undef machine_arch_type
+@@ -11043,18 +11172,6 @@ extern unsigned int __machine_arch_type;
+ # define machine_is_nokia_rm680() (0)
+ #endif
+
+-#ifdef CONFIG_MACH_AST2200
+-# ifdef machine_arch_type
+-# undef machine_arch_type
+-# define machine_arch_type __machine_arch_type
+-# else
+-# define machine_arch_type MACH_TYPE_AST2200
+-# endif
+-# define machine_is_ast2200() (machine_arch_type == MACH_TYPE_AST2200)
+-#else
+-# define machine_is_ast2200() (0)
+-#endif
+-
+ #ifdef CONFIG_MACH_LEAD
+ # ifdef machine_arch_type
+ # undef machine_arch_type
+diff --git a/board/aspeed/ast2300/Makefile b/board/aspeed/ast2300/Makefile
+new file mode 100644
+index 0000000..d5300e6
+--- /dev/null
++++ b/board/aspeed/ast2300/Makefile
+@@ -0,0 +1,42 @@
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).a
++
++COBJS = ast2300.o flash.o flash_spi.o pci.o crc32.o slt.o regtest.o vfun.o vhace.o crt.o videotest.o mactest.o hactest.o mictest.o
++
++ifdef CONFIG_FPGA_ASPEED
++SOBJS := platform_fpga.o
++else
++SOBJS := platform.o
++endif
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS)
++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak $(obj).depend
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude .depend
++
++#########################################################################
+diff --git a/board/aspeed/ast2300/aes.c b/board/aspeed/ast2300/aes.c
+new file mode 100755
+index 0000000..f30ab99
+--- /dev/null
++++ b/board/aspeed/ast2300/aes.c
+@@ -0,0 +1,573 @@
++/*
++ * AES implementation
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++/* uncomment the following line to run the test suite */
++
++/* #define TEST */
++
++/* uncomment the following line to use pre-computed tables */
++/* otherwise the tables will be generated at the first run */
++
++#define FIXED_TABLES
++
++#ifndef FIXED_TABLES
++
++/* forward S-box & tables */
++
++uint32 FSb[256];
++uint32 FT0[256];
++uint32 FT1[256];
++uint32 FT2[256];
++uint32 FT3[256];
++
++/* reverse S-box & tables */
++
++uint32 RSb[256];
++uint32 RT0[256];
++uint32 RT1[256];
++uint32 RT2[256];
++uint32 RT3[256];
++
++/* round constants */
++
++uint32 RCON[10];
++
++/* tables generation flag */
++
++int do_init = 1;
++
++/* tables generation routine */
++
++#define ROTR8(x) ( ( ( x << 24 ) & 0xFFFFFFFF ) | \
++ ( ( x & 0xFFFFFFFF ) >> 8 ) )
++
++#define XTIME(x) ( ( x << 1 ) ^ ( ( x & 0x80 ) ? 0x1B : 0x00 ) )
++#define MUL(x,y) ( ( x && y ) ? pow[(log[x] + log[y]) % 255] : 0 )
++
++void aes_gen_tables( void )
++{
++ int i;
++ uint8 x, y;
++ uint8 pow[256];
++ uint8 log[256];
++
++ /* compute pow and log tables over GF(2^8) */
++
++ for( i = 0, x = 1; i < 256; i++, x ^= XTIME( x ) )
++ {
++ pow[i] = x;
++ log[x] = i;
++ }
++
++ /* calculate the round constants */
++
++ for( i = 0, x = 1; i < 10; i++, x = XTIME( x ) )
++ {
++ RCON[i] = (uint32) x << 24;
++ }
++
++ /* generate the forward and reverse S-boxes */
++
++ FSb[0x00] = 0x63;
++ RSb[0x63] = 0x00;
++
++ for( i = 1; i < 256; i++ )
++ {
++ x = pow[255 - log[i]];
++
++ y = x; y = ( y << 1 ) | ( y >> 7 );
++ x ^= y; y = ( y << 1 ) | ( y >> 7 );
++ x ^= y; y = ( y << 1 ) | ( y >> 7 );
++ x ^= y; y = ( y << 1 ) | ( y >> 7 );
++ x ^= y ^ 0x63;
++
++ FSb[i] = x;
++ RSb[x] = i;
++ }
++
++ /* generate the forward and reverse tables */
++
++ for( i = 0; i < 256; i++ )
++ {
++ x = (unsigned char) FSb[i]; y = XTIME( x );
++
++ FT0[i] = (uint32) ( x ^ y ) ^
++ ( (uint32) x << 8 ) ^
++ ( (uint32) x << 16 ) ^
++ ( (uint32) y << 24 );
++
++ FT0[i] &= 0xFFFFFFFF;
++
++ FT1[i] = ROTR8( FT0[i] );
++ FT2[i] = ROTR8( FT1[i] );
++ FT3[i] = ROTR8( FT2[i] );
++
++ y = (unsigned char) RSb[i];
++
++ RT0[i] = ( (uint32) MUL( 0x0B, y ) ) ^
++ ( (uint32) MUL( 0x0D, y ) << 8 ) ^
++ ( (uint32) MUL( 0x09, y ) << 16 ) ^
++ ( (uint32) MUL( 0x0E, y ) << 24 );
++
++ RT0[i] &= 0xFFFFFFFF;
++
++ RT1[i] = ROTR8( RT0[i] );
++ RT2[i] = ROTR8( RT1[i] );
++ RT3[i] = ROTR8( RT2[i] );
++ }
++}
++
++#else
++
++/* forward S-box */
++
++static const uint32 FSb[256] =
++{
++ 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5,
++ 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
++ 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0,
++ 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,
++ 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC,
++ 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
++ 0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A,
++ 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75,
++ 0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0,
++ 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84,
++ 0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B,
++ 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
++ 0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85,
++ 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8,
++ 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5,
++ 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2,
++ 0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17,
++ 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
++ 0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88,
++ 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB,
++ 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C,
++ 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79,
++ 0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9,
++ 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
++ 0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6,
++ 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A,
++ 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E,
++ 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E,
++ 0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94,
++ 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
++ 0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68,
++ 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16
++};
++
++/* forward tables */
++
++#define FT \
++\
++ V(C6,63,63,A5), V(F8,7C,7C,84), V(EE,77,77,99), V(F6,7B,7B,8D), \
++ V(FF,F2,F2,0D), V(D6,6B,6B,BD), V(DE,6F,6F,B1), V(91,C5,C5,54), \
++ V(60,30,30,50), V(02,01,01,03), V(CE,67,67,A9), V(56,2B,2B,7D), \
++ V(E7,FE,FE,19), V(B5,D7,D7,62), V(4D,AB,AB,E6), V(EC,76,76,9A), \
++ V(8F,CA,CA,45), V(1F,82,82,9D), V(89,C9,C9,40), V(FA,7D,7D,87), \
++ V(EF,FA,FA,15), V(B2,59,59,EB), V(8E,47,47,C9), V(FB,F0,F0,0B), \
++ V(41,AD,AD,EC), V(B3,D4,D4,67), V(5F,A2,A2,FD), V(45,AF,AF,EA), \
++ V(23,9C,9C,BF), V(53,A4,A4,F7), V(E4,72,72,96), V(9B,C0,C0,5B), \
++ V(75,B7,B7,C2), V(E1,FD,FD,1C), V(3D,93,93,AE), V(4C,26,26,6A), \
++ V(6C,36,36,5A), V(7E,3F,3F,41), V(F5,F7,F7,02), V(83,CC,CC,4F), \
++ V(68,34,34,5C), V(51,A5,A5,F4), V(D1,E5,E5,34), V(F9,F1,F1,08), \
++ V(E2,71,71,93), V(AB,D8,D8,73), V(62,31,31,53), V(2A,15,15,3F), \
++ V(08,04,04,0C), V(95,C7,C7,52), V(46,23,23,65), V(9D,C3,C3,5E), \
++ V(30,18,18,28), V(37,96,96,A1), V(0A,05,05,0F), V(2F,9A,9A,B5), \
++ V(0E,07,07,09), V(24,12,12,36), V(1B,80,80,9B), V(DF,E2,E2,3D), \
++ V(CD,EB,EB,26), V(4E,27,27,69), V(7F,B2,B2,CD), V(EA,75,75,9F), \
++ V(12,09,09,1B), V(1D,83,83,9E), V(58,2C,2C,74), V(34,1A,1A,2E), \
++ V(36,1B,1B,2D), V(DC,6E,6E,B2), V(B4,5A,5A,EE), V(5B,A0,A0,FB), \
++ V(A4,52,52,F6), V(76,3B,3B,4D), V(B7,D6,D6,61), V(7D,B3,B3,CE), \
++ V(52,29,29,7B), V(DD,E3,E3,3E), V(5E,2F,2F,71), V(13,84,84,97), \
++ V(A6,53,53,F5), V(B9,D1,D1,68), V(00,00,00,00), V(C1,ED,ED,2C), \
++ V(40,20,20,60), V(E3,FC,FC,1F), V(79,B1,B1,C8), V(B6,5B,5B,ED), \
++ V(D4,6A,6A,BE), V(8D,CB,CB,46), V(67,BE,BE,D9), V(72,39,39,4B), \
++ V(94,4A,4A,DE), V(98,4C,4C,D4), V(B0,58,58,E8), V(85,CF,CF,4A), \
++ V(BB,D0,D0,6B), V(C5,EF,EF,2A), V(4F,AA,AA,E5), V(ED,FB,FB,16), \
++ V(86,43,43,C5), V(9A,4D,4D,D7), V(66,33,33,55), V(11,85,85,94), \
++ V(8A,45,45,CF), V(E9,F9,F9,10), V(04,02,02,06), V(FE,7F,7F,81), \
++ V(A0,50,50,F0), V(78,3C,3C,44), V(25,9F,9F,BA), V(4B,A8,A8,E3), \
++ V(A2,51,51,F3), V(5D,A3,A3,FE), V(80,40,40,C0), V(05,8F,8F,8A), \
++ V(3F,92,92,AD), V(21,9D,9D,BC), V(70,38,38,48), V(F1,F5,F5,04), \
++ V(63,BC,BC,DF), V(77,B6,B6,C1), V(AF,DA,DA,75), V(42,21,21,63), \
++ V(20,10,10,30), V(E5,FF,FF,1A), V(FD,F3,F3,0E), V(BF,D2,D2,6D), \
++ V(81,CD,CD,4C), V(18,0C,0C,14), V(26,13,13,35), V(C3,EC,EC,2F), \
++ V(BE,5F,5F,E1), V(35,97,97,A2), V(88,44,44,CC), V(2E,17,17,39), \
++ V(93,C4,C4,57), V(55,A7,A7,F2), V(FC,7E,7E,82), V(7A,3D,3D,47), \
++ V(C8,64,64,AC), V(BA,5D,5D,E7), V(32,19,19,2B), V(E6,73,73,95), \
++ V(C0,60,60,A0), V(19,81,81,98), V(9E,4F,4F,D1), V(A3,DC,DC,7F), \
++ V(44,22,22,66), V(54,2A,2A,7E), V(3B,90,90,AB), V(0B,88,88,83), \
++ V(8C,46,46,CA), V(C7,EE,EE,29), V(6B,B8,B8,D3), V(28,14,14,3C), \
++ V(A7,DE,DE,79), V(BC,5E,5E,E2), V(16,0B,0B,1D), V(AD,DB,DB,76), \
++ V(DB,E0,E0,3B), V(64,32,32,56), V(74,3A,3A,4E), V(14,0A,0A,1E), \
++ V(92,49,49,DB), V(0C,06,06,0A), V(48,24,24,6C), V(B8,5C,5C,E4), \
++ V(9F,C2,C2,5D), V(BD,D3,D3,6E), V(43,AC,AC,EF), V(C4,62,62,A6), \
++ V(39,91,91,A8), V(31,95,95,A4), V(D3,E4,E4,37), V(F2,79,79,8B), \
++ V(D5,E7,E7,32), V(8B,C8,C8,43), V(6E,37,37,59), V(DA,6D,6D,B7), \
++ V(01,8D,8D,8C), V(B1,D5,D5,64), V(9C,4E,4E,D2), V(49,A9,A9,E0), \
++ V(D8,6C,6C,B4), V(AC,56,56,FA), V(F3,F4,F4,07), V(CF,EA,EA,25), \
++ V(CA,65,65,AF), V(F4,7A,7A,8E), V(47,AE,AE,E9), V(10,08,08,18), \
++ V(6F,BA,BA,D5), V(F0,78,78,88), V(4A,25,25,6F), V(5C,2E,2E,72), \
++ V(38,1C,1C,24), V(57,A6,A6,F1), V(73,B4,B4,C7), V(97,C6,C6,51), \
++ V(CB,E8,E8,23), V(A1,DD,DD,7C), V(E8,74,74,9C), V(3E,1F,1F,21), \
++ V(96,4B,4B,DD), V(61,BD,BD,DC), V(0D,8B,8B,86), V(0F,8A,8A,85), \
++ V(E0,70,70,90), V(7C,3E,3E,42), V(71,B5,B5,C4), V(CC,66,66,AA), \
++ V(90,48,48,D8), V(06,03,03,05), V(F7,F6,F6,01), V(1C,0E,0E,12), \
++ V(C2,61,61,A3), V(6A,35,35,5F), V(AE,57,57,F9), V(69,B9,B9,D0), \
++ V(17,86,86,91), V(99,C1,C1,58), V(3A,1D,1D,27), V(27,9E,9E,B9), \
++ V(D9,E1,E1,38), V(EB,F8,F8,13), V(2B,98,98,B3), V(22,11,11,33), \
++ V(D2,69,69,BB), V(A9,D9,D9,70), V(07,8E,8E,89), V(33,94,94,A7), \
++ V(2D,9B,9B,B6), V(3C,1E,1E,22), V(15,87,87,92), V(C9,E9,E9,20), \
++ V(87,CE,CE,49), V(AA,55,55,FF), V(50,28,28,78), V(A5,DF,DF,7A), \
++ V(03,8C,8C,8F), V(59,A1,A1,F8), V(09,89,89,80), V(1A,0D,0D,17), \
++ V(65,BF,BF,DA), V(D7,E6,E6,31), V(84,42,42,C6), V(D0,68,68,B8), \
++ V(82,41,41,C3), V(29,99,99,B0), V(5A,2D,2D,77), V(1E,0F,0F,11), \
++ V(7B,B0,B0,CB), V(A8,54,54,FC), V(6D,BB,BB,D6), V(2C,16,16,3A)
++
++#define V(a,b,c,d) 0x##a##b##c##d
++static const uint32 FT0[256] = { FT };
++#undef V
++
++#define V(a,b,c,d) 0x##d##a##b##c
++static const uint32 FT1[256] = { FT };
++#undef V
++
++#define V(a,b,c,d) 0x##c##d##a##b
++static const uint32 FT2[256] = { FT };
++#undef V
++
++#define V(a,b,c,d) 0x##b##c##d##a
++static const uint32 FT3[256] = { FT };
++#undef V
++
++#undef FT
++
++/* reverse S-box */
++
++static const uint32 RSb[256] =
++{
++ 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38,
++ 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB,
++ 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87,
++ 0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB,
++ 0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D,
++ 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E,
++ 0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2,
++ 0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25,
++ 0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16,
++ 0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92,
++ 0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA,
++ 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84,
++ 0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A,
++ 0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06,
++ 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02,
++ 0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B,
++ 0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA,
++ 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73,
++ 0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85,
++ 0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E,
++ 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89,
++ 0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B,
++ 0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20,
++ 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4,
++ 0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31,
++ 0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F,
++ 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D,
++ 0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF,
++ 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0,
++ 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61,
++ 0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26,
++ 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D
++};
++
++/* reverse tables */
++
++#define RT \
++\
++ V(51,F4,A7,50), V(7E,41,65,53), V(1A,17,A4,C3), V(3A,27,5E,96), \
++ V(3B,AB,6B,CB), V(1F,9D,45,F1), V(AC,FA,58,AB), V(4B,E3,03,93), \
++ V(20,30,FA,55), V(AD,76,6D,F6), V(88,CC,76,91), V(F5,02,4C,25), \
++ V(4F,E5,D7,FC), V(C5,2A,CB,D7), V(26,35,44,80), V(B5,62,A3,8F), \
++ V(DE,B1,5A,49), V(25,BA,1B,67), V(45,EA,0E,98), V(5D,FE,C0,E1), \
++ V(C3,2F,75,02), V(81,4C,F0,12), V(8D,46,97,A3), V(6B,D3,F9,C6), \
++ V(03,8F,5F,E7), V(15,92,9C,95), V(BF,6D,7A,EB), V(95,52,59,DA), \
++ V(D4,BE,83,2D), V(58,74,21,D3), V(49,E0,69,29), V(8E,C9,C8,44), \
++ V(75,C2,89,6A), V(F4,8E,79,78), V(99,58,3E,6B), V(27,B9,71,DD), \
++ V(BE,E1,4F,B6), V(F0,88,AD,17), V(C9,20,AC,66), V(7D,CE,3A,B4), \
++ V(63,DF,4A,18), V(E5,1A,31,82), V(97,51,33,60), V(62,53,7F,45), \
++ V(B1,64,77,E0), V(BB,6B,AE,84), V(FE,81,A0,1C), V(F9,08,2B,94), \
++ V(70,48,68,58), V(8F,45,FD,19), V(94,DE,6C,87), V(52,7B,F8,B7), \
++ V(AB,73,D3,23), V(72,4B,02,E2), V(E3,1F,8F,57), V(66,55,AB,2A), \
++ V(B2,EB,28,07), V(2F,B5,C2,03), V(86,C5,7B,9A), V(D3,37,08,A5), \
++ V(30,28,87,F2), V(23,BF,A5,B2), V(02,03,6A,BA), V(ED,16,82,5C), \
++ V(8A,CF,1C,2B), V(A7,79,B4,92), V(F3,07,F2,F0), V(4E,69,E2,A1), \
++ V(65,DA,F4,CD), V(06,05,BE,D5), V(D1,34,62,1F), V(C4,A6,FE,8A), \
++ V(34,2E,53,9D), V(A2,F3,55,A0), V(05,8A,E1,32), V(A4,F6,EB,75), \
++ V(0B,83,EC,39), V(40,60,EF,AA), V(5E,71,9F,06), V(BD,6E,10,51), \
++ V(3E,21,8A,F9), V(96,DD,06,3D), V(DD,3E,05,AE), V(4D,E6,BD,46), \
++ V(91,54,8D,B5), V(71,C4,5D,05), V(04,06,D4,6F), V(60,50,15,FF), \
++ V(19,98,FB,24), V(D6,BD,E9,97), V(89,40,43,CC), V(67,D9,9E,77), \
++ V(B0,E8,42,BD), V(07,89,8B,88), V(E7,19,5B,38), V(79,C8,EE,DB), \
++ V(A1,7C,0A,47), V(7C,42,0F,E9), V(F8,84,1E,C9), V(00,00,00,00), \
++ V(09,80,86,83), V(32,2B,ED,48), V(1E,11,70,AC), V(6C,5A,72,4E), \
++ V(FD,0E,FF,FB), V(0F,85,38,56), V(3D,AE,D5,1E), V(36,2D,39,27), \
++ V(0A,0F,D9,64), V(68,5C,A6,21), V(9B,5B,54,D1), V(24,36,2E,3A), \
++ V(0C,0A,67,B1), V(93,57,E7,0F), V(B4,EE,96,D2), V(1B,9B,91,9E), \
++ V(80,C0,C5,4F), V(61,DC,20,A2), V(5A,77,4B,69), V(1C,12,1A,16), \
++ V(E2,93,BA,0A), V(C0,A0,2A,E5), V(3C,22,E0,43), V(12,1B,17,1D), \
++ V(0E,09,0D,0B), V(F2,8B,C7,AD), V(2D,B6,A8,B9), V(14,1E,A9,C8), \
++ V(57,F1,19,85), V(AF,75,07,4C), V(EE,99,DD,BB), V(A3,7F,60,FD), \
++ V(F7,01,26,9F), V(5C,72,F5,BC), V(44,66,3B,C5), V(5B,FB,7E,34), \
++ V(8B,43,29,76), V(CB,23,C6,DC), V(B6,ED,FC,68), V(B8,E4,F1,63), \
++ V(D7,31,DC,CA), V(42,63,85,10), V(13,97,22,40), V(84,C6,11,20), \
++ V(85,4A,24,7D), V(D2,BB,3D,F8), V(AE,F9,32,11), V(C7,29,A1,6D), \
++ V(1D,9E,2F,4B), V(DC,B2,30,F3), V(0D,86,52,EC), V(77,C1,E3,D0), \
++ V(2B,B3,16,6C), V(A9,70,B9,99), V(11,94,48,FA), V(47,E9,64,22), \
++ V(A8,FC,8C,C4), V(A0,F0,3F,1A), V(56,7D,2C,D8), V(22,33,90,EF), \
++ V(87,49,4E,C7), V(D9,38,D1,C1), V(8C,CA,A2,FE), V(98,D4,0B,36), \
++ V(A6,F5,81,CF), V(A5,7A,DE,28), V(DA,B7,8E,26), V(3F,AD,BF,A4), \
++ V(2C,3A,9D,E4), V(50,78,92,0D), V(6A,5F,CC,9B), V(54,7E,46,62), \
++ V(F6,8D,13,C2), V(90,D8,B8,E8), V(2E,39,F7,5E), V(82,C3,AF,F5), \
++ V(9F,5D,80,BE), V(69,D0,93,7C), V(6F,D5,2D,A9), V(CF,25,12,B3), \
++ V(C8,AC,99,3B), V(10,18,7D,A7), V(E8,9C,63,6E), V(DB,3B,BB,7B), \
++ V(CD,26,78,09), V(6E,59,18,F4), V(EC,9A,B7,01), V(83,4F,9A,A8), \
++ V(E6,95,6E,65), V(AA,FF,E6,7E), V(21,BC,CF,08), V(EF,15,E8,E6), \
++ V(BA,E7,9B,D9), V(4A,6F,36,CE), V(EA,9F,09,D4), V(29,B0,7C,D6), \
++ V(31,A4,B2,AF), V(2A,3F,23,31), V(C6,A5,94,30), V(35,A2,66,C0), \
++ V(74,4E,BC,37), V(FC,82,CA,A6), V(E0,90,D0,B0), V(33,A7,D8,15), \
++ V(F1,04,98,4A), V(41,EC,DA,F7), V(7F,CD,50,0E), V(17,91,F6,2F), \
++ V(76,4D,D6,8D), V(43,EF,B0,4D), V(CC,AA,4D,54), V(E4,96,04,DF), \
++ V(9E,D1,B5,E3), V(4C,6A,88,1B), V(C1,2C,1F,B8), V(46,65,51,7F), \
++ V(9D,5E,EA,04), V(01,8C,35,5D), V(FA,87,74,73), V(FB,0B,41,2E), \
++ V(B3,67,1D,5A), V(92,DB,D2,52), V(E9,10,56,33), V(6D,D6,47,13), \
++ V(9A,D7,61,8C), V(37,A1,0C,7A), V(59,F8,14,8E), V(EB,13,3C,89), \
++ V(CE,A9,27,EE), V(B7,61,C9,35), V(E1,1C,E5,ED), V(7A,47,B1,3C), \
++ V(9C,D2,DF,59), V(55,F2,73,3F), V(18,14,CE,79), V(73,C7,37,BF), \
++ V(53,F7,CD,EA), V(5F,FD,AA,5B), V(DF,3D,6F,14), V(78,44,DB,86), \
++ V(CA,AF,F3,81), V(B9,68,C4,3E), V(38,24,34,2C), V(C2,A3,40,5F), \
++ V(16,1D,C3,72), V(BC,E2,25,0C), V(28,3C,49,8B), V(FF,0D,95,41), \
++ V(39,A8,01,71), V(08,0C,B3,DE), V(D8,B4,E4,9C), V(64,56,C1,90), \
++ V(7B,CB,84,61), V(D5,32,B6,70), V(48,6C,5C,74), V(D0,B8,57,42)
++
++#define V(a,b,c,d) 0x##a##b##c##d
++static const uint32 RT0[256] = { RT };
++#undef V
++
++#define V(a,b,c,d) 0x##d##a##b##c
++static const uint32 RT1[256] = { RT };
++#undef V
++
++#define V(a,b,c,d) 0x##c##d##a##b
++static const uint32 RT2[256] = { RT };
++#undef V
++
++#define V(a,b,c,d) 0x##b##c##d##a
++static const uint32 RT3[256] = { RT };
++#undef V
++
++#undef RT
++
++/* round constants */
++
++static const uint32 RCON[10] =
++{
++ 0x01000000, 0x02000000, 0x04000000, 0x08000000,
++ 0x10000000, 0x20000000, 0x40000000, 0x80000000,
++ 0x1B000000, 0x36000000
++};
++
++int do_init = 0;
++
++void aes_gen_tables( void )
++{
++}
++
++#endif
++
++/* platform-independant 32-bit integer manipulation macros */
++
++#define GET_UINT32_aes(n,b,i) \
++{ \
++ (n) = ( (uint32) (b)[(i) ] << 24 ) \
++ | ( (uint32) (b)[(i) + 1] << 16 ) \
++ | ( (uint32) (b)[(i) + 2] << 8 ) \
++ | ( (uint32) (b)[(i) + 3] ); \
++}
++
++#define PUT_UINT32_aes(n,b,i) \
++{ \
++ (b)[(i) ] = (uint8) ( (n) >> 24 ); \
++ (b)[(i) + 1] = (uint8) ( (n) >> 16 ); \
++ (b)[(i) + 2] = (uint8) ( (n) >> 8 ); \
++ (b)[(i) + 3] = (uint8) ( (n) ); \
++}
++
++/* decryption key schedule tables */
++
++int KT_init = 1;
++
++uint32 KT0[256];
++uint32 KT1[256];
++uint32 KT2[256];
++uint32 KT3[256];
++
++/* AES key scheduling routine */
++int aes_set_key( aes_context *ctx, uint8 *key, int nbits )
++{
++ int i;
++ uint32 *RK, *SK;
++
++ if( do_init )
++ {
++ aes_gen_tables();
++
++ do_init = 0;
++ }
++
++ switch( nbits )
++ {
++ case 128: ctx->nr = 10; break;
++ case 192: ctx->nr = 12; break;
++ case 256: ctx->nr = 14; break;
++ default : return( 1 );
++ }
++
++ RK = ctx->erk;
++
++ for( i = 0; i < (nbits >> 5); i++ )
++ {
++ GET_UINT32_aes( RK[i], key, i * 4 );
++ }
++
++ /* setup encryption round keys */
++
++ switch( nbits )
++ {
++ case 128:
++
++ for( i = 0; i < 10; i++, RK += 4 )
++ {
++ RK[4] = RK[0] ^ RCON[i] ^
++ ( FSb[ (uint8) ( RK[3] >> 16 ) ] << 24 ) ^
++ ( FSb[ (uint8) ( RK[3] >> 8 ) ] << 16 ) ^
++ ( FSb[ (uint8) ( RK[3] ) ] << 8 ) ^
++ ( FSb[ (uint8) ( RK[3] >> 24 ) ] );
++
++ RK[5] = RK[1] ^ RK[4];
++ RK[6] = RK[2] ^ RK[5];
++ RK[7] = RK[3] ^ RK[6];
++ }
++ break;
++
++ case 192:
++
++ for( i = 0; i < 8; i++, RK += 6 )
++ {
++ RK[6] = RK[0] ^ RCON[i] ^
++ ( FSb[ (uint8) ( RK[5] >> 16 ) ] << 24 ) ^
++ ( FSb[ (uint8) ( RK[5] >> 8 ) ] << 16 ) ^
++ ( FSb[ (uint8) ( RK[5] ) ] << 8 ) ^
++ ( FSb[ (uint8) ( RK[5] >> 24 ) ] );
++
++ RK[7] = RK[1] ^ RK[6];
++ RK[8] = RK[2] ^ RK[7];
++ RK[9] = RK[3] ^ RK[8];
++ RK[10] = RK[4] ^ RK[9];
++ RK[11] = RK[5] ^ RK[10];
++ }
++ break;
++
++ case 256:
++
++ for( i = 0; i < 7; i++, RK += 8 )
++ {
++ RK[8] = RK[0] ^ RCON[i] ^
++ ( FSb[ (uint8) ( RK[7] >> 16 ) ] << 24 ) ^
++ ( FSb[ (uint8) ( RK[7] >> 8 ) ] << 16 ) ^
++ ( FSb[ (uint8) ( RK[7] ) ] << 8 ) ^
++ ( FSb[ (uint8) ( RK[7] >> 24 ) ] );
++
++ RK[9] = RK[1] ^ RK[8];
++ RK[10] = RK[2] ^ RK[9];
++ RK[11] = RK[3] ^ RK[10];
++
++ RK[12] = RK[4] ^
++ ( FSb[ (uint8) ( RK[11] >> 24 ) ] << 24 ) ^
++ ( FSb[ (uint8) ( RK[11] >> 16 ) ] << 16 ) ^
++ ( FSb[ (uint8) ( RK[11] >> 8 ) ] << 8 ) ^
++ ( FSb[ (uint8) ( RK[11] ) ] );
++
++ RK[13] = RK[5] ^ RK[12];
++ RK[14] = RK[6] ^ RK[13];
++ RK[15] = RK[7] ^ RK[14];
++ }
++ break;
++ }
++
++ /* setup decryption round keys */
++
++ if( KT_init )
++ {
++ for( i = 0; i < 256; i++ )
++ {
++ KT0[i] = RT0[ FSb[i] ];
++ KT1[i] = RT1[ FSb[i] ];
++ KT2[i] = RT2[ FSb[i] ];
++ KT3[i] = RT3[ FSb[i] ];
++ }
++
++ KT_init = 0;
++ }
++
++ SK = ctx->drk;
++
++ *SK++ = *RK++;
++ *SK++ = *RK++;
++ *SK++ = *RK++;
++ *SK++ = *RK++;
++
++ for( i = 1; i < ctx->nr; i++ )
++ {
++ RK -= 8;
++
++ *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
++ KT1[ (uint8) ( *RK >> 16 ) ] ^
++ KT2[ (uint8) ( *RK >> 8 ) ] ^
++ KT3[ (uint8) ( *RK ) ]; RK++;
++
++ *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
++ KT1[ (uint8) ( *RK >> 16 ) ] ^
++ KT2[ (uint8) ( *RK >> 8 ) ] ^
++ KT3[ (uint8) ( *RK ) ]; RK++;
++
++ *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
++ KT1[ (uint8) ( *RK >> 16 ) ] ^
++ KT2[ (uint8) ( *RK >> 8 ) ] ^
++ KT3[ (uint8) ( *RK ) ]; RK++;
++
++ *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
++ KT1[ (uint8) ( *RK >> 16 ) ] ^
++ KT2[ (uint8) ( *RK >> 8 ) ] ^
++ KT3[ (uint8) ( *RK ) ]; RK++;
++ }
++
++ RK -= 8;
++
++ *SK++ = *RK++;
++ *SK++ = *RK++;
++ *SK++ = *RK++;
++ *SK++ = *RK++;
++
++ return( 0 );
++}
+diff --git a/board/aspeed/ast2300/ast2300.c b/board/aspeed/ast2300/ast2300.c
+new file mode 100644
+index 0000000..b317786
+--- /dev/null
++++ b/board/aspeed/ast2300/ast2300.c
+@@ -0,0 +1,171 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <command.h>
++#include <pci.h>
++
++int board_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++ unsigned char data;
++ unsigned long reg;
++
++ /* AHB Controller */
++ *((volatile ulong*) 0x1E600000) = 0xAEED1A03; /* unlock AHB controller */
++ *((volatile ulong*) 0x1E60008C) |= 0x01; /* map DRAM to 0x00000000 */
++#ifdef CONFIG_PCI
++ *((volatile ulong*) 0x1E60008C) |= 0x30; /* map PCI */
++#endif
++
++ /* Flash Controller */
++#ifdef CONFIG_FLASH_AST2300
++ *((volatile ulong*) 0x1e620000) |= 0x800f0000; /* enable Flash Write */
++#else
++ *((volatile ulong*) 0x16000000) |= 0x00001c00; /* enable Flash Write */
++#endif
++
++ /* SCU */
++ *((volatile ulong*) 0x1e6e2000) = 0x1688A8A8; /* unlock SCU */
++ reg = *((volatile ulong*) 0x1e6e2008);
++ reg &= 0x1c0fffff;
++ reg |= 0x61800000; /* PCLK = HPLL/8 */
++#ifdef CONFIG_AST1070
++ reg |= 0x300000; /* LHCLK = HPLL/8 */
++ reg |= 0x80000; /* LPC Host Clock */
++#endif
++ *((volatile ulong*) 0x1e6e2008) = reg;
++ reg = *((volatile ulong*) 0x1e6e200c); /* enable 2D Clk */
++ *((volatile ulong*) 0x1e6e200c) &= 0xFFFFFFFD;
++/* enable wide screen. If your video driver does not support wide screen, don't
++enable this bit 0x1e6e2040 D[0]*/
++ reg = *((volatile ulong*) 0x1e6e2040);
++ *((volatile ulong*) 0x1e6e2040) |= 0x01;
++#ifdef CONFIG_AST1070
++/*set VPPL1 */
++
++ *((volatile ulong*) 0x1e6e201c) = 0x6420;
++
++// set d2-pll & enable d2-pll D[21:20], D[4]
++ reg = *((volatile ulong*) 0x1e6e202c);
++ reg &= 0xffcfffef;
++ reg |= 0x00200010;
++ *((volatile ulong*) 0x1e6e202c) = reg;
++
++// set OSCCLK = VPLL1
++ *((volatile ulong*) 0x1e6e2010) = 0x8;
++
++// enable OSCCLK
++ reg = *((volatile ulong*) 0x1e6e202c);
++ reg &= 0xfffffffd;
++ reg |= 0x00000002;
++ *((volatile ulong*) 0x1e6e202c) = reg;
++
++// enable AST1050's LPC master
++ reg = *((volatile ulong*) 0x1e7890a0);
++ *((volatile ulong*) 0x1e7890a0) |= 0x11;
++#endif
++ /* arch number */
++ gd->bd->bi_arch_number = MACH_TYPE_ASPEED;
++
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = 0x40000100;
++
++ return 0;
++}
++
++int dram_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
++/*
++SCU7C: Silicon Revision ID Register
++D[31:24]: Chip ID
++0: AST2050/AST2100/AST2150/AST2200/AST3000
++1: AST2300
++
++D[23:16] Silicon revision ID for AST2300 generation and later
++0: A0
++1: A1
++2: A2
++.
++.
++.
++FPGA revision starts from 0x80
++
++
++D[11:8] Bounding option
++
++D[7:0] Silicon revision ID for AST2050/AST2100 generation (for software compatible)
++0: A0
++1: A1
++2: A2
++3: A3
++.
++.
++FPGA revision starts from 0x08, 8~10 means A0, 11+ means A1, AST2300 should be assigned to 3
++*/
++int misc_init_r(void)
++{
++ unsigned int reg1, revision, chip_id;
++
++ /* Show H/W Version */
++ reg1 = (unsigned int) (*((ulong*) 0x1e6e207c));
++ chip_id = (reg1 & 0xff000000) >> 24;
++ revision = (reg1 & 0xff0000) >> 16;
++
++ puts ("H/W: ");
++ if (chip_id == 1) {
++ if (revision >= 0x80) {
++ printf("AST2300 series FPGA Rev. %02x \n", revision);
++ }
++ else {
++ printf("AST2300 series chip Rev. %02x \n", revision);
++ }
++ }
++ else if (chip_id == 0) {
++ printf("AST2050/AST2150 series chip\n");
++ }
++
++#ifdef CONFIG_AST1070
++ puts ("C/C: ");
++ revision = (unsigned int) (*((ulong*) 0x60002034));
++ printf("AST1070 ID [%08x] \n", revision);
++#endif
++
++#ifdef CONFIG_PCI
++ pci_init ();
++#endif
++
++ if (getenv ("verify") == NULL) {
++ setenv ("verify", "n");
++ }
++ if (getenv ("eeprom") == NULL) {
++ setenv ("eeprom", "y");
++ }
++}
++
++#ifdef CONFIG_PCI
++static struct pci_controller hose;
++
++extern void aspeed_init_pci (struct pci_controller *hose);
++
++void pci_init_board(void)
++{
++ aspeed_init_pci(&hose);
++}
++#endif
+diff --git a/board/aspeed/ast2300/config.mk b/board/aspeed/ast2300/config.mk
+new file mode 100755
+index 0000000..24ca09b
+--- /dev/null
++++ b/board/aspeed/ast2300/config.mk
+@@ -0,0 +1,18 @@
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++# ROM version
++#TEXT_BASE = 0xBFC00000
++
++# RAM version
++TEXT_BASE = 0x40500000
++#TEXT_BASE = 0x00000000
++#TEXT_BASE = 0x00400000
+diff --git a/board/aspeed/ast2300/crc32.c b/board/aspeed/ast2300/crc32.c
+new file mode 100755
+index 0000000..cc8d2ac
+--- /dev/null
++++ b/board/aspeed/ast2300/crc32.c
+@@ -0,0 +1,127 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#include <common.h>
++#include <asm/processor.h>
++#include <asm/byteorder.h>
++#include <environment.h>
++
++#ifdef CONFIG_2SPIFLASH
++
++extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
++
++/* ========================================================================
++ * Table of CRC-32's of all single-byte values (made by make_aspeed_crc_table)
++ */
++unsigned long aspeed_crc_table[256] = {
++ 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
++ 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
++ 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
++ 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
++ 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
++ 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
++ 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
++ 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
++ 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
++ 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
++ 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
++ 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
++ 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
++ 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
++ 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
++ 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
++ 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
++ 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
++ 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
++ 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
++ 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
++ 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
++ 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
++ 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
++ 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
++ 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
++ 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
++ 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
++ 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
++ 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
++ 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
++ 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
++ 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
++ 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
++ 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
++ 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
++ 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
++ 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
++ 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
++ 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
++ 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
++ 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
++ 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
++ 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
++ 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
++ 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
++ 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
++ 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
++ 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
++ 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
++ 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
++ 0x2d02ef8dL
++};
++
++/* ========================================================================= */
++#define ASPEED_DO1(buf) crc = aspeed_crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8);
++#define ASPEED_DO2(buf) ASPEED_DO1(buf); ASPEED_DO1(buf);
++#define ASPEED_DO4(buf) ASPEED_DO2(buf); ASPEED_DO2(buf);
++#define ASPEED_DO8(buf) ASPEED_DO4(buf); ASPEED_DO4(buf);
++
++/* ========================================================================= */
++unsigned long spi2_crc32(crc, buf, len)
++ unsigned long crc;
++ unsigned char *buf;
++ unsigned long len;
++{
++
++ size_t len1, len2;
++ char *s;
++
++ len1 = len2 = 0;
++ if ( (ulong)(buf) <= (flash_info[0].start[0] + flash_info[0].size) )
++ len1 = (flash_info[0].start[0] + flash_info[0].size) - (ulong)(buf);
++
++ len1 = (len < len1) ? len:len1;
++ len2 = (len < len1) ? 0: (len - len1);
++
++ crc = crc ^ 0xffffffffL;
++ while (len1 >= 8)
++ {
++ ASPEED_DO8(buf);
++ len1 -= 8;
++ }
++ if (len1) do {
++ ASPEED_DO1(buf);
++ } while (--len1);
++
++ //s = (char *) flash_info[1].start[0];
++ s= (char *) flash_make_addr (&flash_info[1], 0, 0);
++ while (len2 >= 8)
++ {
++ ASPEED_DO8(s);
++ len2 -= 8;
++ }
++ if (len2) do {
++ ASPEED_DO1(s);
++ } while (--len2);
++
++ return crc ^ 0xffffffffL;
++
++}
++
++#endif /* CONFIG_2SPIFLASH */
++
+diff --git a/board/aspeed/ast2300/crt.c b/board/aspeed/ast2300/crt.c
+new file mode 100755
+index 0000000..b67f669
+--- /dev/null
++++ b/board/aspeed/ast2300/crt.c
+@@ -0,0 +1,322 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#include <common.h>
++#include <command.h>
++
++#include "type.h"
++#include "vesa.h"
++#include "vdef.h"
++#include "vfun.h"
++#include "vreg.h"
++#include "crt.h"
++
++ULONG AST3000DCLKTableV [] = {
++ 0x00046515, /* 00: VCLK25_175 */
++ 0x00047255, /* 01: VCLK28_322 */
++ 0x0004682a, /* 02: VCLK31_5 */
++ 0x0004672a, /* 03: VCLK36 */
++ 0x00046c50, /* 04: VCLK40 */
++ 0x00046842, /* 05: VCLK49_5 */
++ 0x00006c32, /* 06: VCLK50 */
++ 0x00006a2f, /* 07: VCLK56_25 */
++ 0x00006c41, /* 08: VCLK65 */
++ 0x00006832, /* 09: VCLK75 */
++ 0x0000672e, /* 0A: VCLK78_75 */
++ 0x0000683f, /* 0B: VCLK94_5 */
++ 0x00004824, /* 0C: VCLK108 */
++ 0x00004723, /* 0D: VCLK119 */
++ 0x0000482d, /* 0E: VCLK135 */
++ 0x00004B37, /* 0F: VCLK146_25 */
++ 0x0000472e, /* 10: VCLK157_5 */
++ 0x00004836, /* 11: VCLK162 */
++
++};
++
++BOOL CheckDAC(int nCRTIndex)
++{
++ BYTE btValue;
++ BOOL bValue;
++
++ BYTE btDeviceSelect;
++
++ switch (nCRTIndex)
++ {
++ case CRT_1:
++ btDeviceSelect = DEVICE_ADDRESS_CH7301_CRT1;
++ break;
++ case CRT_2:
++ btDeviceSelect = DEVICE_ADDRESS_CH7301_CRT2;
++ break;
++ default:
++ printf("CRTIndex is not 1 or 2");
++ return FALSE;
++ break;
++ }
++
++ //Enable all DAC's and set register 21h[0] = '0'
++ //DVIP and DVIL disable for DAC
++ SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_PM_REG, 0x00);
++
++ btValue = GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_DC_REG);
++ btValue = btValue & 0xFE;
++ SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_DC_REG, btValue);
++
++ //Set SENSE bit to 1
++ btValue = GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG);
++ btValue = btValue | 0x01;
++ SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG, btValue);
++
++ //Reset SENSE bit to 0
++ btValue = GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG);
++ btValue = btValue & 0xFE;
++ SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG, btValue);
++
++ bValue = (GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG) & CD_DACT) ? TRUE : FALSE;
++
++ return bValue;
++}
++
++VOID SetCH7301C(ULONG MMIOBase,
++ int nCRTIndex,
++ int inFreqRange,
++ int inOperating)
++{
++ BYTE btDeviceSelect;
++ BYTE btValue;
++
++//#ifdef EVB_CLIENT
++ //output RGB doesn't need to set CH7301
++ //if (1 == inOperating)
++ // return;
++//#endif
++
++ switch (nCRTIndex)
++ {
++ case CRT_1:
++ btDeviceSelect = 0xEA;
++
++ break;
++ case CRT_2:
++ btDeviceSelect = 0xEC;
++
++ break;
++ default:
++ printf("CRTIndex is not 1 or 2");
++ return;
++ break;
++ }
++
++ if (inFreqRange <= VCLK65)
++ {
++ printf("ch7301: low f \n");
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x33, 0x08);
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x34, 0x16);
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x36, 0x60);
++ }
++ else
++ {
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x33, 0x06);
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x34, 0x26);
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x36, 0xA0);
++ }
++
++ switch (inOperating)
++ {
++ case 0:
++ //DVI is normal function
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x49, 0xC0);
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x1D, 0x47);
++ break;
++ case 1:
++ //RGB
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x48, 0x18);
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x49, 0x0);
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x56, 0x0);
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x21, 0x9);
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x1D, 0x48);
++ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x1C, 0x00);
++ break;
++ default:
++ break;
++ };
++}
++
++void SetASTModeTiming (ULONG MMIOBase, int nCRTIndex, BYTE ModeIndex, BYTE ColorDepth)
++{
++ ULONG temp, RetraceStart, RetraceEnd, DisplayOffset, TerminalCount, bpp;
++
++// Access CRT Engine
++ // SetPolarity
++ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, ((vModeTable[ModeIndex].HorPolarity << HOR_SYNC_SELECT_BIT) | (vModeTable[ModeIndex].VerPolarity << VER_SYNC_SELECT_BIT)), (HOR_SYNC_SELECT_MASK|VER_SYNC_SELECT_MASK));
++
++#if CONFIG_AST3000
++ WriteMemoryLongClient(SCU_BASE, CRT1_CONTROL2_REG + nCRTIndex*0x60, 0xc0);
++#else
++ //2100 is single edge
++ WriteMemoryLongClient(SCU_BASE, CRT1_CONTROL2_REG + nCRTIndex*0x60, 0x80);
++#endif
++ // Horizontal Timing
++ temp = 0;
++ temp = ((vModeTable[ModeIndex].HorizontalActive - 1) << HOR_ENABLE_END_BIT) | ((vModeTable[ModeIndex].HorizontalTotal - 1) << HOR_TOTAL_BIT);
++ WriteMemoryLongClient(SCU_BASE, CRT1_HOR_TOTAL_END_REG + nCRTIndex*0x60, temp);
++
++ RetraceStart = vModeTable[ModeIndex].HorizontalTotal - vModeTable[ModeIndex].HBackPorch - vModeTable[ModeIndex].HSyncTime - vModeTable[ModeIndex].HLeftBorder - 1;
++ RetraceEnd = (RetraceStart + vModeTable[ModeIndex].HSyncTime);
++ temp = 0;
++ temp = (RetraceEnd << HOR_RETRACE_END_BIT) | (RetraceStart << HOR_RETRACE_START_BIT);
++ WriteMemoryLongClient(SCU_BASE, CRT1_HOR_RETRACE_REG + nCRTIndex*0x60, temp);
++
++ // Vertical Timing
++ temp = 0;
++ temp = ((vModeTable[ModeIndex].VerticalActive - 1) << VER_ENABLE_END_BIT) | ((vModeTable[ModeIndex].VerticalTotal - 1) << VER_TOTAL_BIT);
++ WriteMemoryLongClient(SCU_BASE, CRT1_VER_TOTAL_END_REG + nCRTIndex*0x60, temp);
++
++ temp = 0;
++ RetraceStart = vModeTable[ModeIndex].VerticalTotal - vModeTable[ModeIndex].VBackPorch - vModeTable[ModeIndex].VSyncTime - vModeTable[ModeIndex].VTopBorder - 1;
++ RetraceEnd = (RetraceStart + vModeTable[ModeIndex].VSyncTime);
++ temp = (RetraceEnd << VER_RETRACE_END_BIT) | (RetraceStart << VER_RETRACE_START_BIT);
++ WriteMemoryLongClient(SCU_BASE, CRT1_VER_RETRACE_REG + nCRTIndex*0x60, temp);
++
++ // Set CRT Display Offset and Terminal Count
++ if (ColorDepth == RGB_565) {
++ bpp = 16;
++ }
++ else {
++ bpp = 32;
++ }
++
++ DisplayOffset = vModeTable[ModeIndex].HorizontalActive * bpp / 8;
++ TerminalCount = vModeTable[ModeIndex].HorizontalActive * bpp / 64;
++ if (ColorDepth == YUV_444) {
++ TerminalCount = TerminalCount * 3 / 4;
++ }
++ if (((vModeTable[ModeIndex].HorizontalActive * bpp) % 64) != 0) {
++ TerminalCount++;
++ }
++
++ WriteMemoryLongClient(SCU_BASE, CRT1_DISPLAY_OFFSET + nCRTIndex*0x60, ((TerminalCount << TERMINAL_COUNT_BIT) | DisplayOffset));
++
++ // Set Color Format
++ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, (ColorDepth << FORMAT_SELECT_BIT), FORMAT_SELECT_MASK);
++
++ // Set Threshold
++ temp = 0;
++ temp = (CRT_HIGH_THRESHOLD_VALUE << THRES_HIGHT_BIT) | (CRT_LOW_THRESHOLD_VALUE << THRES_LOW_BIT);
++ WriteMemoryLongClient(SCU_BASE, CRT1_THRESHOLD_REG + nCRTIndex*0x60, temp);
++
++ WriteMemoryLongClient(SCU_BASE, CRT1_VIDEO_PLL_REG + nCRTIndex*0x60, AST3000DCLKTableV[vModeTable[ModeIndex].PixelClock]);
++}
++
++void SetASTCenter1024ModeTiming (ULONG MMIOBase, int nCRTIndex, BYTE ModeIndex, BYTE ColorDepth)
++{
++ ULONG temp, RetraceStart, RetraceEnd, DisplayOffset, TerminalCount, bpp;
++
++ // Access CRT Engine
++ // SetPolarity
++ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, (HOR_NEGATIVE << HOR_SYNC_SELECT_BIT) | (VER_NEGATIVE << VER_SYNC_SELECT_BIT), HOR_SYNC_SELECT_MASK|VER_SYNC_SELECT_MASK);
++
++ WriteMemoryLongClient(SCU_BASE, CRT1_CONTROL2_REG + nCRTIndex*0x60, 0xC0);
++
++ // Horizontal Timing
++ temp = 0;
++ temp = ((vModeTable[ModeIndex].HorizontalActive - 1) << HOR_ENABLE_END_BIT) | ((vModeTable[10].HorizontalTotal - 1) << HOR_TOTAL_BIT);
++ WriteMemoryLongClient(SCU_BASE, CRT1_HOR_TOTAL_END_REG + nCRTIndex*0x60, temp);
++
++ RetraceStart = vModeTable[10].HorizontalTotal - vModeTable[10].HBackPorch - vModeTable[10].HSyncTime - vModeTable[10].HLeftBorder - 1;
++ RetraceStart = RetraceStart - (vModeTable[10].HorizontalActive - vModeTable[ModeIndex].HorizontalActive) / 2 - 1;
++ RetraceEnd = (RetraceStart + vModeTable[10].HSyncTime);
++ temp = 0;
++ temp = (RetraceEnd << HOR_RETRACE_END_BIT) | (RetraceStart << HOR_RETRACE_START_BIT);
++ WriteMemoryLongClient(SCU_BASE, CRT1_HOR_RETRACE_REG + nCRTIndex*0x60, temp);
++
++ // Vertical Timing
++ temp = 0;
++ temp = ((vModeTable[ModeIndex].VerticalActive - 1) << VER_ENABLE_END_BIT) | ((vModeTable[10].VerticalTotal - 1) << VER_TOTAL_BIT);
++ WriteMemoryLongClient(SCU_BASE, CRT1_VER_TOTAL_END_REG + nCRTIndex*0x60, temp);
++
++ RetraceStart = vModeTable[10].VerticalTotal - vModeTable[10].VBackPorch - vModeTable[10].VSyncTime - vModeTable[10].VTopBorder - 1;
++ RetraceStart = RetraceStart - (vModeTable[10].VerticalActive - vModeTable[ModeIndex].VerticalActive) / 2 - 1;
++ RetraceEnd = (RetraceStart + vModeTable[10].VSyncTime);
++ temp = (RetraceEnd << VER_RETRACE_END_BIT) | (RetraceStart << VER_RETRACE_START_BIT);
++ WriteMemoryLongClient(SCU_BASE, CRT1_VER_RETRACE_REG + nCRTIndex*0x60, temp);
++
++ // Set CRT Display Offset and Terminal Count
++ if (ColorDepth == RGB_565) {
++ bpp = 16;
++ }
++ else {
++ bpp = 32;
++ }
++ DisplayOffset = vModeTable[ModeIndex].HorizontalActive * bpp / 8;
++ TerminalCount = vModeTable[ModeIndex].HorizontalActive * bpp / 64;
++ if (ColorDepth == YUV_444) {
++ TerminalCount = TerminalCount * 3 / 4;
++ }
++ if (((vModeTable[ModeIndex].HorizontalActive * bpp) % 64) != 0) {
++ TerminalCount++;
++ }
++
++ WriteMemoryLongClient(SCU_BASE, CRT1_DISPLAY_OFFSET + nCRTIndex*0x60, (TerminalCount << TERMINAL_COUNT_BIT) | DisplayOffset);
++
++ // Set Color Format
++ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, (ColorDepth << FORMAT_SELECT_BIT), FORMAT_SELECT_MASK);
++
++ // Set Threshold
++ temp = 0;
++ temp = (CRT_HIGH_THRESHOLD_VALUE << THRES_HIGHT_BIT) | (CRT_LOW_THRESHOLD_VALUE << THRES_LOW_BIT);
++ WriteMemoryLongClient(SCU_BASE, CRT1_THRESHOLD_REG + nCRTIndex*0x60, temp);
++
++ // Set DCLK
++ WriteMemoryLongClient(SCU_BASE, CRT1_VIDEO_PLL_REG + nCRTIndex*0x60, AST3000DCLKTableV[vModeTable[ModeIndex].PixelClock]);
++
++}
++
++BOOL ASTSetModeV (ULONG MMIOBase, int nCRTIndex, ULONG VGABaseAddr, USHORT Horizontal, USHORT Vertical, BYTE ColorFormat, BYTE CenterMode)
++{
++ BYTE i, ModeIndex;
++ BOOL bDAC;
++ ULONG ulTemp;
++
++ // Access CRT Engine
++ //Enable CRT1 graph
++ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + 0x60*nCRTIndex, GRAPH_DISPLAY_ON, GRAPH_DISPLAY_MASK);
++
++ // Set CRT Display Start Address
++ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_DISPLAY_ADDRESS + 0x60*nCRTIndex, VGABaseAddr, DISPLAY_ADDRESS_MASK);
++
++ for (i = 0; i < Mode60HZCount; i++) {
++ if ((vModeTable[i].HorizontalActive == Horizontal) && (vModeTable[i].VerticalActive == Vertical)) {
++
++ ModeIndex = i;
++
++ if (CenterMode != 1) {
++ SetASTModeTiming(MMIOBase, nCRTIndex, i, ColorFormat);
++ }
++ else {
++ SetASTCenter1024ModeTiming (MMIOBase, nCRTIndex, i, ColorFormat);
++ }
++
++ //use internal video out sigal and don't need use 7301
++ /*
++ bDAC = CheckDAC(nCRTIndex);
++
++ SetCH7301C(0,
++ nCRTIndex,
++ vModeTable[ModeIndex].PixelClock,
++ bDAC); //For RGB
++ */
++ return TRUE;
++ }
++ }
++
++ return FALSE;
++}
++
+diff --git a/board/aspeed/ast2300/crt.h b/board/aspeed/ast2300/crt.h
+new file mode 100755
+index 0000000..e7483be
+--- /dev/null
++++ b/board/aspeed/ast2300/crt.h
+@@ -0,0 +1,121 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifndef _CRT_H_
++#define _CRT_H_
++
++#ifdef Watcom
++#define CRT_REMAP_OFFSET 0x10000
++#else
++#define CRT_REMAP_OFFSET 0x0
++#endif
++
++/********************************************************/
++/* CRT register */
++/********************************************************/
++#define CRT_BASE_OFFSET 0x6000+CRT_REMAP_OFFSET
++
++#define CRT1_CONTROL_REG 0x00 + CRT_BASE_OFFSET
++ #define GRAPH_DISPLAY_BIT 0
++ #define GRAPH_DISPLAY_MASK (1<<0)
++ #define GRAPH_DISPLAY_ON 1
++ #define GRAPH_DISPLAY_OFF 0
++ #define FORMAT_SELECT_BIT 8
++ #define FORMAT_SELECT_MASK (3<<8)
++ #define HOR_SYNC_SELECT_BIT 16
++ #define HOR_SYNC_SELECT_MASK (1<<16)
++ #define HOR_NEGATIVE 1
++ #define HOR_POSITIVE 0
++ #define VER_SYNC_SELECT_BIT 17
++ #define VER_SYNC_SELECT_MASK (1<<17)
++ #define VER_NEGATIVE 1
++ #define VER_POSITIVE 0
++
++#define CRT1_CONTROL2_REG 0x04 + CRT_BASE_OFFSET
++
++#define CRT1_VIDEO_PLL_REG 0x0C + CRT_BASE_OFFSET
++ #define POST_DIV_BIT 18
++ #define POST_DIV_MASK 3<<18
++ #define DIV_1_1 0
++ //#define DIV_1_2 1
++ #define DIV_1_2 2
++ #define DIV_1_4 3
++
++#define CRT1_HOR_TOTAL_END_REG 0x10 + CRT_BASE_OFFSET
++ #define HOR_TOTAL_BIT 0
++ #define HOR_ENABLE_END_BIT 16
++
++#define CRT1_HOR_RETRACE_REG 0x14 + CRT_BASE_OFFSET
++ #define HOR_RETRACE_START_BIT 0
++ #define HOR_RETRACE_END_BIT 16
++
++#define CRT1_VER_TOTAL_END_REG 0x18 + CRT_BASE_OFFSET
++ #define VER_TOTAL_BIT 0
++ #define VER_ENABLE_END_BIT 16
++
++#define CRT1_VER_RETRACE_REG 0x1C + CRT_BASE_OFFSET
++ #define VER_RETRACE_START_BIT 0
++ #define VER_RETRACE_END_BIT 16
++
++#define CRT1_DISPLAY_ADDRESS 0x20 + CRT_BASE_OFFSET
++ #define DISPLAY_ADDRESS_MASK 0x0FFFFFFF
++
++#define CRT1_DISPLAY_OFFSET 0x24 + CRT_BASE_OFFSET
++ #define DISPLAY_OFFSET_ALIGN 7 /* 8 byte alignment*/
++ #define TERMINAL_COUNT_BIT 16
++
++#define CRT1_THRESHOLD_REG 0x28 + CRT_BASE_OFFSET
++ #define THRES_LOW_BIT 0
++ #define THRES_HIGHT_BIT 8
++
++#define CURSOR_POSITION 0x30 + OFFSET
++#define CURSOR_OFFSET 0x34 + OFFSET
++#define CURSOR_PATTERN 0x38 + OFFSET
++#define OSD_HORIZONTAL 0x40 + OFFSET
++#define OSD_VERTICAL 0x44 + OFFSET
++#define OSD_PATTERN 0x48 + OFFSET
++#define OSD_OFFSET 0x4C + OFFSET
++#define OSD_THRESHOLD 0x50 + OFFSET
++
++//Ch7301c
++#define DEVICE_ADDRESS_CH7301_CRT1 0xEA
++#define DEVICE_ADDRESS_CH7301_CRT2 0xEC
++
++
++#define DEVICE_SELECT_CH7301 0x3
++
++/* CH7301 Register Definition */
++#define CH7301_CD_REG 0x20
++ #define CD_DACT 0x0E
++ #define CD_DVIT 1 << 5
++#define CH7301_DC_REG 0x21
++#define CH7301_PM_REG 0x49
++
++BOOL CheckHotPlug(int nCRTIndex);
++BOOL CheckDAC(int nCRTIndex);
++
++BOOL ASTSetModeV (ULONG MMIOBase,
++ int nCRTIndex,
++ ULONG VGABaseAddr,
++ USHORT Horizontal,
++ USHORT Vertical,
++ BYTE ColorFormat,
++ BYTE CenterMode);
++
++BOOL SelCRTClock(ULONG MMIOBase,
++ int nCRTIndex,
++ USHORT Horizontal,
++ USHORT Vertical);
++
++void DisableCRT(ULONG MMIOBase, int nCRTIndex);
++void ClearCRTWithBlack(ULONG ulCRTAddr, int iWidth, int iHeight);
++
++#endif /* _CRT_H_ */
++
+diff --git a/board/aspeed/ast2300/flash.c b/board/aspeed/ast2300/flash.c
+new file mode 100755
+index 0000000..d611d0d
+--- /dev/null
++++ b/board/aspeed/ast2300/flash.c
+@@ -0,0 +1,1651 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * History
++ * 01/20/2004 - combined variants of original driver.
++ * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
++ * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
++ * 01/27/2004 - Little endian support Ed Okerson
++ *
++ * Tested Architectures
++ * Port Width Chip Width # of banks Flash Chip Board
++ * 32 16 1 28F128J3 seranoa/eagle
++ * 64 16 1 28F128J3 seranoa/falcon
++ */
++// (Sun) This CFI driver is written for fixed-width flash chips.
++// It was not designed for flexible 8-bit/16-bit chips, which are the norm.
++// When those chips are connected to a bus in 8-bit mode, the address wires
++// right-shifted by 1.
++//FIXME: Fix the driver to auto-detect "16-bit flash wired in 8-bit mode".
++// Left-shift CFI offsets by 1 bit instead of doubling the #define values.
++
++/* The DEBUG define must be before common to enable debugging */
++// (Sun) Changed to DEBUG_FLASH because flash debug()s are too numerous.
++// #define DEBUG
++
++#include <common.h>
++#include <asm/processor.h>
++#include <asm/byteorder.h>
++#include <environment.h>
++#ifdef CONFIG_SYS_FLASH_CFI
++
++/*
++ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
++ * The width of the port and the width of the chips are determined at initialization.
++ * These widths are used to calculate the address for access CFI data structures.
++ * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
++ *
++ * References
++ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
++ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
++ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
++ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
++ *
++ * TODO
++ *
++ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
++ * Table (ALT) to determine if protection is available
++ *
++ * Add support for other command sets Use the PRI and ALT to determine command set
++ * Verify erase and program timeouts.
++ */
++
++#ifndef CONFIG_FLASH_BANKS_LIST
++#define CONFIG_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
++#endif
++
++#define FLASH_CMD_CFI 0x98
++#define FLASH_CMD_READ_ID 0x90
++#define FLASH_CMD_RESET 0xff
++#define FLASH_CMD_BLOCK_ERASE 0x20
++#define FLASH_CMD_ERASE_CONFIRM 0xD0
++#define FLASH_CMD_WRITE 0x40
++#define FLASH_CMD_PROTECT 0x60
++#define FLASH_CMD_PROTECT_SET 0x01
++#define FLASH_CMD_PROTECT_CLEAR 0xD0
++#define FLASH_CMD_CLEAR_STATUS 0x50
++#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
++#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
++
++#define FLASH_STATUS_DONE 0x80
++#define FLASH_STATUS_ESS 0x40
++#define FLASH_STATUS_ECLBS 0x20
++#define FLASH_STATUS_PSLBS 0x10
++#define FLASH_STATUS_VPENS 0x08
++#define FLASH_STATUS_PSS 0x04
++#define FLASH_STATUS_DPS 0x02
++#define FLASH_STATUS_R 0x01
++#define FLASH_STATUS_PROTECT 0x01
++
++#define AMD_CMD_RESET 0xF0
++#define AMD_CMD_WRITE 0xA0
++#define AMD_CMD_ERASE_START 0x80
++#define AMD_CMD_ERASE_SECTOR 0x30
++#define AMD_CMD_UNLOCK_START 0xAA
++#define AMD_CMD_UNLOCK_ACK 0x55
++#define AMD_CMD_WRITE_TO_BUFFER 0x25
++#define AMD_CMD_BUFFER_TO_FLASH 0x29
++
++#define AMD_STATUS_TOGGLE 0x40
++#define AMD_STATUS_ERROR 0x20
++//FIXME: These 3 were also changed for 8-bit/16-bit flash chips.
++#define AMD_ADDR_ERASE_START (0xAAA/info->portwidth)
++#define AMD_ADDR_START (0xAAA/info->portwidth)
++#define AMD_ADDR_ACK (0x555/info->portwidth)
++
++//FIXME: Fix the driver to auto-detect "16-bit flash wired in 8-bit mode".
++// Left-shift CFI offsets by 1 bit instead of doubling the #define values.
++#define FLASH_OFFSET_CFI (0xAA/info->portwidth)
++#define FLASH_OFFSET_CFI_RESP (0x20/info->portwidth)
++#define FLASH_OFFSET_CFI_RESP1 (0x22/info->portwidth)
++#define FLASH_OFFSET_CFI_RESP2 (0x24/info->portwidth)
++#define FLASH_OFFSET_PRIMARY_VENDOR (0x26/info->portwidth)
++#define FLASH_OFFSET_WTOUT (0x3E/info->portwidth)
++#define FLASH_OFFSET_WBTOUT (0x40/info->portwidth)
++#define FLASH_OFFSET_ETOUT (0x42/info->portwidth)
++#define FLASH_OFFSET_CETOUT (0x44/info->portwidth)
++#define FLASH_OFFSET_WMAX_TOUT (0x46/info->portwidth)
++#define FLASH_OFFSET_WBMAX_TOUT (0x48/info->portwidth)
++#define FLASH_OFFSET_EMAX_TOUT (0x4A/info->portwidth)
++#define FLASH_OFFSET_CEMAX_TOUT (0x4C/info->portwidth)
++#define FLASH_OFFSET_SIZE (0x4E/info->portwidth)
++#define FLASH_OFFSET_INTERFACE (0x50/info->portwidth)
++#define FLASH_OFFSET_BUFFER_SIZE (0x54/info->portwidth)
++#define FLASH_OFFSET_NUM_ERASE_REGIONS (0x58/info->portwidth)
++#define FLASH_OFFSET_ERASE_REGIONS (0x5A/info->portwidth)
++#define FLASH_OFFSET_PROTECT (0x02/info->portwidth)
++#define FLASH_OFFSET_USER_PROTECTION (0x85/info->portwidth)
++#define FLASH_OFFSET_INTEL_PROTECTION (0x81/info->portwidth)
++
++#define MAX_NUM_ERASE_REGIONS 4
++
++#define FLASH_MAN_CFI 0x01000000
++
++#define CFI_CMDSET_NONE 0
++#define CFI_CMDSET_INTEL_EXTENDED 1
++#define CFI_CMDSET_AMD_STANDARD 2
++#define CFI_CMDSET_INTEL_STANDARD 3
++#define CFI_CMDSET_AMD_EXTENDED 4
++#define CFI_CMDSET_MITSU_STANDARD 256
++#define CFI_CMDSET_MITSU_EXTENDED 257
++#define CFI_CMDSET_SST 258
++
++
++#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
++# undef FLASH_CMD_RESET
++# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
++#endif
++
++
++typedef union {
++ unsigned char c;
++ unsigned short w;
++ unsigned long l;
++ unsigned long long ll;
++} cfiword_t;
++
++typedef union {
++ volatile unsigned char *cp;
++ volatile unsigned short *wp;
++ volatile unsigned long *lp;
++ volatile unsigned long long *llp;
++} cfiptr_t;
++
++/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
++#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
++static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS_DETECT] = CONFIG_FLASH_BANKS_LIST;
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
++#else
++static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_FLASH_BANKS_LIST;
++flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
++#endif
++
++
++/*-----------------------------------------------------------------------
++ * Functions
++ */
++static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
++static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
++static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
++static void flash_write_cmd_nodbg (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
++static void flash_write_cmd_int (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd, int noDebug);
++static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
++static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
++static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
++static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
++static int flash_detect_cfi (flash_info_t * info);
++ulong flash_get_size (ulong base, int banknum);
++static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
++static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
++ ulong tout, char *prompt);
++static void write_buffer_abort_reset(flash_info_t * info, flash_sect_t sector);
++#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
++static flash_info_t *flash_get_info(ulong base);
++#endif
++#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
++static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
++static int flash_write_cfibuffer_amd (flash_info_t * info, ulong dest, uchar * cp, int len);
++#endif
++
++/*-----------------------------------------------------------------------
++ * create an address based on the offset and the port width
++ */
++inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
++{
++ return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
++}
++
++/*-----------------------------------------------------------------------
++ * Debug support
++ */
++#ifdef DEBUG_FLASH
++static void print_longlong (char *str, unsigned long long data)
++{
++ int i;
++ char *cp;
++
++ cp = (unsigned char *) &data;
++ for (i = 0; i < 8; i++)
++ sprintf (&str[i * 2], "%2.2x", *cp++);
++}
++#endif
++
++#if defined(DEBUG_FLASH)
++static void flash_printqry (flash_info_t * info, flash_sect_t sect)
++{
++ cfiptr_t cptr;
++ int x, y;
++
++ for (x = 0; x < 0x40; x += 16U / info->portwidth) {
++ cptr.cp =
++ flash_make_addr (info, sect,
++ x + FLASH_OFFSET_CFI_RESP);
++ debug ("%p : ", cptr.cp);
++ for (y = 0; y < 16; y++) {
++ debug ("%2.2x ", cptr.cp[y]);
++ }
++ debug (" ");
++ for (y = 0; y < 16; y++) {
++ if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
++ debug ("%c", cptr.cp[y]);
++ } else {
++ debug (".");
++ }
++ }
++ debug ("\n");
++ }
++}
++#endif
++
++/*-----------------------------------------------------------------------
++ * read a character at a port width address
++ */
++inline uchar flash_read_uchar (flash_info_t * info, uint offset)
++{
++ uchar *cp;
++
++ cp = flash_make_addr (info, 0, offset);
++#if defined(__LITTLE_ENDIAN)
++ return (cp[0]);
++#else
++ return (cp[info->portwidth - 1]);
++#endif
++}
++
++/*-----------------------------------------------------------------------
++ * read a short word by swapping for ppc format.
++ */
++#if 0
++static ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
++{
++ uchar *addr;
++ ushort retval;
++
++#ifdef DEBUG_FLASH
++ int x;
++#endif
++ addr = flash_make_addr (info, sect, offset);
++
++#ifdef DEBUG_FLASH
++ debug ("ushort addr is at %p info->portwidth = %d\n", addr,
++ info->portwidth);
++ for (x = 0; x < 2 * info->portwidth; x++) {
++ debug ("addr[%x] = 0x%x\n", x, addr[x]);
++ }
++#endif
++#if defined(__LITTLE_ENDIAN)
++ if (info->interface == FLASH_CFI_X8X16) {
++ retval = (addr[0] | (addr[2] << 8));
++ } else {
++ retval = (addr[0] | (addr[(info->portwidth)] << 8));
++ }
++#else
++ retval = ((addr[(2 * info->portwidth) - 1] << 8) |
++ addr[info->portwidth - 1]);
++#endif
++
++ debug ("retval = 0x%x\n", retval);
++ return retval;
++}
++#endif
++
++/*-----------------------------------------------------------------------
++ * read a long word by picking the least significant byte of each maximum
++ * port size word. Swap for ppc format.
++ */
++static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
++{
++ uchar *addr;
++ ulong retval;
++#ifdef DEBUG_FLASH
++ int x;
++#endif
++#if 0
++ switch (info->interface) {
++ case FLASH_CFI_X8:
++ case FLASH_CFI_X16:
++ break;
++ case FLASH_CFI_X8X16:
++ offset <<= 1;
++ }
++#endif
++ // flash_make_addr() multiplies offset by info->portwidth.
++ addr = flash_make_addr (info, sect, offset);
++
++#ifdef DEBUG_FLASH
++ debug ("long addr is at %p info->portwidth = %d\n", addr,
++ info->portwidth);
++ for (x = 0; x < 4 * info->portwidth; x++) {
++ debug ("addr[%x] = 0x%x\n", x, addr[x]);
++ }
++#endif
++#if defined(__LITTLE_ENDIAN)
++ if (info->interface == FLASH_CFI_X8X16) {
++ retval = (addr[0] | (addr[2] << 8) | (addr[4] << 16) | (addr[6] << 24));
++ } else {
++ retval = (addr[0] | (addr[(info->portwidth)] << 8) |
++ (addr[(2 * info->portwidth)] << 16) |
++ (addr[(3 * info->portwidth)] << 24));
++ }
++#else
++ //FIXME: This undocumented code appears to match broken bus wiring.
++ retval = (addr[(2 * info->portwidth) - 1] << 24) |
++ (addr[(info->portwidth) - 1] << 16) |
++ (addr[(4 * info->portwidth) - 1] << 8) |
++ addr[(3 * info->portwidth) - 1];
++#endif
++ return retval;
++}
++
++/*-----------------------------------------------------------------------
++ */
++unsigned long flash_init (void)
++{
++ unsigned long size = 0;
++ int i;
++
++ /* Init: no FLASHes known */
++ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
++ flash_info[i].flash_id = FLASH_UNKNOWN;
++ size += flash_info[i].size = flash_get_size (bank_base[i], i);
++ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
++#ifndef CFG_FLASH_QUIET_TEST
++ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
++ i, flash_info[i].size, flash_info[i].size << 20);
++#endif /* CFG_FLASH_QUIET_TEST */
++ }
++ }
++
++ /* Monitor protection ON by default */
++#if (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
++ flash_protect (FLAG_PROTECT_SET,
++ CONFIG_MONITOR_BASE,
++ CONFIG_MONITOR_BASE + monitor_flash_len - 1,
++ flash_get_info(CONFIG_MONITOR_BASE));
++#endif
++
++ /* Environment protection ON by default */
++#ifdef CONFIG_ENV_IS_IN_FLASH
++ flash_protect (FLAG_PROTECT_SET,
++ CONFIG_ENV_ADDR,
++ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
++ flash_get_info(CONFIG_ENV_ADDR));
++#endif
++
++ /* Redundant environment protection ON by default */
++#ifdef CONFIG_ENV_ADDR_REDUND
++ flash_protect (FLAG_PROTECT_SET,
++ CONFIG_ENV_ADDR_REDUND,
++ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
++ flash_get_info(CONFIG_ENV_ADDR_REDUND));
++#endif
++ return (size);
++}
++
++/*-----------------------------------------------------------------------
++ */
++#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
++static flash_info_t *flash_get_info(ulong base)
++{
++ int i;
++ flash_info_t * info = 0;
++
++ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
++ info = & flash_info[i];
++ if (info->size && info->start[0] <= base &&
++ base <= info->start[0] + info->size - 1)
++ break;
++ }
++
++ return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
++}
++#endif
++
++/*-----------------------------------------------------------------------
++ */
++int flash_erase (flash_info_t * info, int s_first, int s_last)
++{
++ int rcode = 0;
++ int prot;
++ flash_sect_t sect;
++ uchar ch;
++ uchar *addr;
++
++ if (info->flash_id != FLASH_MAN_CFI) {
++ puts ("Can't erase unknown flash type - aborted\n");
++ return 1;
++ }
++ if ((s_first < 0) || (s_first > s_last)) {
++ puts ("- no sectors to erase\n");
++ return 1;
++ }
++
++ prot = 0;
++ for (sect = s_first; sect <= s_last; ++sect) {
++ if (info->protect[sect]) {
++ prot++;
++ }
++ }
++ if (prot) {
++ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
++ } else {
++ putc ('\n');
++ }
++
++
++ for (sect = s_first; sect <= s_last; sect++) {
++ if (info->protect[sect] == 0) { /* not protected */
++ switch (info->vendor) {
++ case CFI_CMDSET_INTEL_STANDARD:
++ case CFI_CMDSET_INTEL_EXTENDED:
++ flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS);
++ flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE);
++ flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
++ break;
++ case CFI_CMDSET_AMD_STANDARD:
++ case CFI_CMDSET_AMD_EXTENDED:
++ flash_unlock_seq (info, sect);
++ flash_write_cmd (info, sect, AMD_ADDR_ERASE_START,
++ AMD_CMD_ERASE_START);
++ flash_unlock_seq (info, sect);
++ flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
++
++ /* toggle */
++ addr = flash_make_addr (info, sect, 0);
++ do {
++ ch = *(volatile uchar *)(addr);
++ } while ( ((ch & 0x80) == 0) || (ch != 0xFF) );
++ break;
++ default:
++ debug ("Unkown flash vendor %d\n",
++ info->vendor);
++ break;
++ }
++
++ if (flash_full_status_check
++ (info, sect, info->erase_blk_tout, "erase")) {
++ rcode = 1;
++ } else
++ putc ('.');
++ }
++ }
++ puts (" done\n");
++ return rcode;
++}
++
++/*-----------------------------------------------------------------------
++ */
++void flash_print_info (flash_info_t * info)
++{
++ int i;
++
++ if (info->flash_id != FLASH_MAN_CFI) {
++ puts ("missing or unknown FLASH type\n");
++ return;
++ }
++
++ printf ("CFI conformant FLASH (%d x %d)",
++ (info->portwidth << 3), (info->chipwidth << 3));
++ printf (" Size: %ld MB in %d Sectors\n",
++ info->size >> 20, info->sector_count);
++ printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
++ info->erase_blk_tout,
++ info->write_tout,
++ info->buffer_write_tout,
++ info->buffer_size);
++
++ puts (" Sector Start Addresses:");
++ for (i = 0; i < info->sector_count; ++i) {
++#ifdef CFG_FLASH_EMPTY_INFO
++ int k;
++ int size;
++ int erased;
++ volatile unsigned long *flash;
++
++ /*
++ * Check if whole sector is erased
++ */
++ if (i != (info->sector_count - 1))
++ size = info->start[i + 1] - info->start[i];
++ else
++ size = info->start[0] + info->size - info->start[i];
++ erased = 1;
++ flash = (volatile unsigned long *) info->start[i];
++ size = size >> 2; /* divide by 4 for longword access */
++ for (k = 0; k < size; k++) {
++ if (*flash++ != 0xffffffff) {
++ erased = 0;
++ break;
++ }
++ }
++
++ if ((i % 5) == 0)
++ printf ("\n");
++ /* print empty and read-only info */
++ printf (" %08lX%s%s",
++ info->start[i],
++ erased ? " E" : " ",
++ info->protect[i] ? "RO " : " ");
++#else /* ! CFG_FLASH_EMPTY_INFO */
++ if ((i % 5) == 0)
++ printf ("\n ");
++ printf (" %08lX%s",
++ info->start[i], info->protect[i] ? " (RO)" : " ");
++#endif
++ }
++ putc ('\n');
++ return;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
++{
++ ulong wp;
++ ulong cp;
++ int aln;
++ cfiword_t cword;
++ int i, rc;
++
++#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
++ unsigned char pat[] = {'|', '-', '/', '\\'};
++ int patcnt = 0;
++ int buffered_size;
++#endif
++ /* get lower aligned address */
++ /* get lower aligned address */
++ wp = (addr & ~(info->portwidth - 1));
++
++ /* handle unaligned start */
++ if ((aln = addr - wp) != 0) {
++ cword.l = 0;
++ cp = wp;
++ for (i = 0; i < aln; ++i, ++cp)
++ flash_add_byte (info, &cword, (*(uchar *) cp));
++
++ for (; (i < info->portwidth) && (cnt > 0); i++) {
++ flash_add_byte (info, &cword, *src++);
++ cnt--;
++ cp++;
++ }
++ for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
++ flash_add_byte (info, &cword, (*(uchar *) cp));
++ if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
++ return rc;
++ wp = cp;
++ }
++
++ /* handle the aligned part */
++#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
++ buffered_size = (info->portwidth / info->chipwidth);
++ buffered_size *= info->buffer_size;
++ while (cnt >= info->portwidth) {
++ /* Show processing */
++ if ((++patcnt % 256) == 0)
++ printf("%c\b", pat[(patcnt / 256) & 0x03]);
++
++ i = buffered_size > cnt ? cnt : buffered_size;
++ if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
++ return rc;
++ i -= i & (info->portwidth - 1);
++ wp += i;
++ src += i;
++ cnt -= i;
++ }
++#else
++ while (cnt >= info->portwidth) {
++ cword.l = 0;
++ for (i = 0; i < info->portwidth; i++) {
++ flash_add_byte (info, &cword, *src++);
++ }
++ if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
++ return rc;
++ wp += info->portwidth;
++ cnt -= info->portwidth;
++ }
++#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
++ if (cnt == 0) {
++ return (0);
++ }
++
++ /*
++ * handle unaligned tail bytes
++ */
++ cword.l = 0;
++ for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
++ flash_add_byte (info, &cword, *src++);
++ --cnt;
++ }
++ for (; i < info->portwidth; ++i, ++cp) {
++ flash_add_byte (info, &cword, (*(uchar *) cp));
++ }
++
++ return flash_write_cfiword (info, wp, cword);
++}
++
++/*-----------------------------------------------------------------------
++ */
++#ifdef CFG_FLASH_PROTECTION
++
++int flash_real_protect (flash_info_t * info, long sector, int prot)
++{
++ int retcode = 0;
++
++ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
++ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
++ if (prot)
++ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
++ else
++ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
++
++ if ((retcode =
++ flash_full_status_check (info, sector, info->erase_blk_tout,
++ prot ? "protect" : "unprotect")) == 0) {
++
++ info->protect[sector] = prot;
++ /* Intel's unprotect unprotects all locking */
++ if (prot == 0) {
++ flash_sect_t i;
++
++ for (i = 0; i < info->sector_count; i++) {
++ if (info->protect[i])
++ flash_real_protect (info, i, 1);
++ }
++ }
++ }
++ return retcode;
++}
++
++/*-----------------------------------------------------------------------
++ * flash_read_user_serial - read the OneTimeProgramming cells
++ */
++void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
++ int len)
++{
++ uchar *src;
++ uchar *dst;
++
++ dst = buffer;
++ src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
++ flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
++ memcpy (dst, src + offset, len);
++ flash_write_cmd (info, 0, 0, info->cmd_reset);
++}
++
++/*
++ * flash_read_factory_serial - read the device Id from the protection area
++ */
++void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
++ int len)
++{
++ uchar *src;
++
++ src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
++ flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
++ memcpy (buffer, src + offset, len);
++ flash_write_cmd (info, 0, 0, info->cmd_reset);
++}
++
++#endif /* CFG_FLASH_PROTECTION */
++
++/*
++ * flash_is_busy - check to see if the flash is busy
++ * This routine checks the status of the chip and returns true if the chip is busy
++ */
++static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
++{
++ int retval;
++
++ switch (info->vendor) {
++ case CFI_CMDSET_INTEL_STANDARD:
++ case CFI_CMDSET_INTEL_EXTENDED:
++ retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
++ break;
++ case CFI_CMDSET_AMD_STANDARD:
++ case CFI_CMDSET_AMD_EXTENDED:
++ retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
++ break;
++ default:
++ retval = 0;
++ }
++#ifdef DEBUG_FLASH
++ if (retval)
++ debug ("flash_is_busy: %d\n", retval);
++#endif
++ return retval;
++}
++
++/*-----------------------------------------------------------------------
++ * wait for XSR.7 to be set. Time out with an error if it does not.
++ * This routine does not set the flash to read-array mode.
++ */
++static int flash_status_check (flash_info_t * info, flash_sect_t sector,
++ ulong tout, char *prompt)
++{
++ ulong start, now;
++
++ /* Wait for command completion */
++ // (Sun) Fix order of checking time so it works when the CPU is very
++ // slow, e.g., single-stepping or emulation.
++ start = get_timer (0);
++ while (now = get_timer(start),
++ flash_is_busy (info, sector))
++ {
++ if (now > info->erase_blk_tout) {
++ printf ("Flash %s timeout at address %lx data %lx\n",
++ prompt, info->start[sector],
++ flash_read_long (info, sector, 0));
++ flash_write_cmd (info, sector, 0, info->cmd_reset);
++ return ERR_TIMOUT;
++ }
++ }
++ return ERR_OK;
++}
++
++/*-----------------------------------------------------------------------
++ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
++ * This routine sets the flash to read-array mode.
++ */
++static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
++ ulong tout, char *prompt)
++{
++ int retcode;
++
++ retcode = flash_status_check (info, sector, tout, prompt);
++ switch (info->vendor) {
++ case CFI_CMDSET_INTEL_EXTENDED:
++ case CFI_CMDSET_INTEL_STANDARD:
++ if ((retcode != ERR_OK)
++ && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
++ retcode = ERR_INVAL;
++ printf ("Flash %s error at address %lx\n", prompt,
++ info->start[sector]);
++ if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
++ puts ("Command Sequence Error.\n");
++ } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
++ puts ("Block Erase Error.\n");
++ retcode = ERR_NOT_ERASED;
++ } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
++ puts ("Locking Error\n");
++ }
++ if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
++ puts ("Block locked.\n");
++ retcode = ERR_PROTECTED;
++ }
++ if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
++ puts ("Vpp Low Error.\n");
++ }
++ flash_write_cmd (info, sector, 0, info->cmd_reset);
++ break;
++ default:
++ break;
++ }
++ return retcode;
++}
++
++static void write_buffer_abort_reset(flash_info_t * info, flash_sect_t sector)
++{
++ flash_write_cmd (info, sector, 0xaaa, 0xaa);
++ flash_write_cmd (info, sector, 0x555, 0x55);
++ flash_write_cmd (info, sector, 0xaaa, 0xf0);
++}
++
++/*-----------------------------------------------------------------------
++ */
++static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
++{
++#if defined(__LITTLE_ENDIAN)
++ unsigned short w;
++ unsigned int l;
++ unsigned long long ll;
++#endif
++
++ switch (info->portwidth) {
++ case FLASH_CFI_8BIT:
++ cword->c = c;
++ break;
++ case FLASH_CFI_16BIT:
++#if defined(__LITTLE_ENDIAN)
++ w = c;
++ w <<= 8;
++ cword->w = (cword->w >> 8) | w;
++#else
++ cword->w = (cword->w << 8) | c;
++#endif
++ break;
++ case FLASH_CFI_32BIT:
++#if defined(__LITTLE_ENDIAN)
++ l = c;
++ l <<= 24;
++ cword->l = (cword->l >> 8) | l;
++#else
++ cword->l = (cword->l << 8) | c;
++#endif
++ break;
++ case FLASH_CFI_64BIT:
++#if defined(__LITTLE_ENDIAN)
++ ll = c;
++ ll <<= 56;
++ cword->ll = (cword->ll >> 8) | ll;
++#else
++ cword->ll = (cword->ll << 8) | c;
++#endif
++ break;
++ }
++}
++
++
++/*-----------------------------------------------------------------------
++ * make a proper sized command based on the port and chip widths
++ */
++static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
++{
++ int i;
++ uchar *cp = (uchar *) cmdbuf;
++
++#if defined(__LITTLE_ENDIAN)
++ for (i = info->portwidth; i > 0; i--)
++#else
++ for (i = 1; i <= info->portwidth; i++)
++#endif
++ *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd;
++}
++
++/*
++ * Write a proper sized command to the correct address
++ */
++static void
++flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset,
++ uchar cmd)
++{
++#ifdef DEBUG_FLASH
++ const int noDebug = 0;
++#else
++ const int noDebug = 1;
++#endif
++ return flash_write_cmd_int(info, sect, offset, cmd, noDebug);
++}
++static void
++flash_write_cmd_nodbg (flash_info_t * info, flash_sect_t sect, uint offset,
++ uchar cmd)
++{
++ return flash_write_cmd_int(info, sect, offset, cmd, 1);
++}
++
++static void
++flash_write_cmd_int (flash_info_t * info, flash_sect_t sect, uint offset,
++ uchar cmd, int noDebug)
++{
++
++ volatile cfiptr_t addr;
++ cfiword_t cword;
++
++ addr.cp = flash_make_addr (info, sect, offset);
++ flash_make_cmd (info, cmd, &cword);
++ switch (info->portwidth) {
++ case FLASH_CFI_8BIT:
++ if (noDebug == 0)
++ debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
++ cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
++ *addr.cp = cword.c;
++ break;
++ case FLASH_CFI_16BIT:
++ if (noDebug == 0)
++ debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
++ cmd, cword.w,
++ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
++ *addr.wp = cword.w;
++ break;
++ case FLASH_CFI_32BIT:
++ if (noDebug == 0)
++ debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
++ cmd, cword.l,
++ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
++ *addr.lp = cword.l;
++ break;
++ case FLASH_CFI_64BIT:
++#ifdef DEBUG_FLASH
++ if (noDebug == 0)
++ {
++ char str[20];
++
++ print_longlong (str, cword.ll);
++
++ debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
++ addr.llp, cmd, str,
++ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
++ }
++#endif
++ *addr.llp = cword.ll;
++ break;
++ }
++}
++
++static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
++{
++ flash_write_cmd_nodbg (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START);
++ flash_write_cmd_nodbg (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
++}
++
++/*-----------------------------------------------------------------------
++ */
++static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
++{
++ cfiptr_t cptr;
++ cfiword_t cword;
++ int retval;
++#ifdef DEBUG_FLASH
++ const int dbg = 1;
++#else
++ const int dbg = 0;
++#endif
++ cptr.cp = flash_make_addr (info, sect, offset);
++ flash_make_cmd (info, cmd, &cword);
++
++ if (dbg)
++ debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
++ switch (info->portwidth) {
++ case FLASH_CFI_8BIT:
++ if (dbg)
++ debug ("is= %x %x\n", cptr.cp[0], cword.c);
++ retval = (cptr.cp[0] == cword.c);
++ break;
++ case FLASH_CFI_16BIT:
++ if (dbg)
++ debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
++ retval = (cptr.wp[0] == cword.w);
++ break;
++ case FLASH_CFI_32BIT:
++ if (dbg)
++ debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
++ retval = (cptr.lp[0] == cword.l);
++ break;
++ case FLASH_CFI_64BIT:
++#ifdef DEBUG_FLASH
++ {
++ char str1[20];
++ char str2[20];
++
++ print_longlong (str1, cptr.llp[0]);
++ print_longlong (str2, cword.ll);
++ debug ("is= %s %s\n", str1, str2);
++ }
++#endif
++ retval = (cptr.llp[0] == cword.ll);
++ break;
++ default:
++ retval = 0;
++ break;
++ }
++ return retval;
++}
++
++/*-----------------------------------------------------------------------
++ */
++static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
++{
++ cfiptr_t cptr;
++ cfiword_t cword;
++ int retval;
++
++ cptr.cp = flash_make_addr (info, sect, offset);
++ flash_make_cmd (info, cmd, &cword);
++ switch (info->portwidth) {
++ case FLASH_CFI_8BIT:
++ retval = ((cptr.cp[0] & cword.c) == cword.c);
++ break;
++ case FLASH_CFI_16BIT:
++ retval = ((cptr.wp[0] & cword.w) == cword.w);
++ break;
++ case FLASH_CFI_32BIT:
++ retval = ((cptr.lp[0] & cword.l) == cword.l);
++ break;
++ case FLASH_CFI_64BIT:
++ retval = ((cptr.llp[0] & cword.ll) == cword.ll);
++ break;
++ default:
++ retval = 0;
++ break;
++ }
++ return retval;
++}
++
++/*-----------------------------------------------------------------------
++ */
++static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
++{
++ cfiptr_t cptr;
++ cfiword_t cword;
++ int retval;
++
++ cptr.cp = flash_make_addr (info, sect, offset);
++ flash_make_cmd (info, cmd, &cword);
++ switch (info->portwidth) {
++ case FLASH_CFI_8BIT:
++ retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
++ break;
++ case FLASH_CFI_16BIT:
++ retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
++ break;
++ case FLASH_CFI_32BIT:
++ retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
++ break;
++ case FLASH_CFI_64BIT:
++ retval = ((cptr.llp[0] & cword.ll) !=
++ (cptr.llp[0] & cword.ll));
++ break;
++ default:
++ retval = 0;
++ break;
++ }
++ return retval;
++}
++
++/*-----------------------------------------------------------------------
++ * detect if flash is compatible with the Common Flash Interface (CFI)
++ * http://www.jedec.org/download/search/jesd68.pdf
++ *
++*/
++static int flash_detect_cfi (flash_info_t * info)
++{
++ ulong data;
++
++ debug ("flash_detect_cfi()... ");
++
++#if defined(CONFIG_FLASH_AST2300)
++ data = *(ulong *)(0x1e6e2070); /* hardware traping */
++ if (data & 0x10) /* D[4]: 0/1 (8/16) */
++ info->portwidth = FLASH_CFI_16BIT;
++ else
++ info->portwidth = FLASH_CFI_8BIT;
++#else
++ info->portwidth = FLASH_CFI_8BIT;
++#endif
++
++ {
++ for (info->chipwidth = FLASH_CFI_BY8;
++ info->chipwidth <= info->portwidth;
++ info->chipwidth <<= 1) {
++ flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
++ flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
++ if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
++ //FIXME: Next 3 lines were changed for 8-bit/16-bit flash chips.
++ && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP1, 'R')
++ && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP2, 'Y')) {
++ info->interface = flash_read_uchar (info, FLASH_OFFSET_INTERFACE);
++ debug ("device interface is %d\n",
++ info->interface);
++ debug ("found port %d chip %d ",
++ info->portwidth, info->chipwidth);
++ debug ("port %d bits chip %d bits\n",
++ info->portwidth << CFI_FLASH_SHIFT_WIDTH,
++ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
++ return 1;
++ }
++ }
++ }
++ debug ("not found\n");
++ return 0;
++}
++
++/*
++ * The following code cannot be run from FLASH!
++ *
++ */
++ulong flash_get_size (ulong base, int banknum)
++{
++ flash_info_t *info = &flash_info[banknum];
++ int i, j;
++ flash_sect_t sect_cnt;
++ unsigned long sector;
++ unsigned long tmp;
++ int size_ratio;
++ uchar num_erase_regions;
++ int erase_region_size;
++ int erase_region_count;
++
++ info->start[0] = base;
++
++ if (flash_detect_cfi (info)) {
++ info->vendor = flash_read_uchar (info, FLASH_OFFSET_PRIMARY_VENDOR);
++#if defined(DEBUG_FLASH)
++ flash_printqry (info, 0);
++#endif
++ switch (info->vendor) {
++ case CFI_CMDSET_INTEL_STANDARD:
++ case CFI_CMDSET_INTEL_EXTENDED:
++ default:
++ info->cmd_reset = FLASH_CMD_RESET;
++ break;
++ case CFI_CMDSET_AMD_STANDARD:
++ case CFI_CMDSET_AMD_EXTENDED:
++ info->cmd_reset = AMD_CMD_RESET;
++ break;
++ }
++
++ debugX(2, "manufacturer is %d\n", info->vendor);
++ size_ratio = info->portwidth / info->chipwidth;
++ /* if the chip is x8/x16 reduce the ratio by half */
++#if 0
++ if ((info->interface == FLASH_CFI_X8X16)
++ && (info->chipwidth == FLASH_CFI_BY8)) {
++ size_ratio >>= 1;
++ }
++#endif
++ num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS);
++ debugX(2, "size_ratio %d port %d bits chip %d bits\n",
++ size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
++ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
++ debugX(2, "found %d erase regions\n", num_erase_regions);
++ sect_cnt = 0;
++ sector = base;
++ for (i = 0; i < num_erase_regions; i++) {
++ if (i > MAX_NUM_ERASE_REGIONS) {
++ printf ("%d erase regions found, only %d used\n",
++ num_erase_regions, MAX_NUM_ERASE_REGIONS);
++ break;
++ }
++ // CFI Erase Block Region Information:
++ // Bits[31:16] = sect_size/256, 0 means 128-byte
++ // Bits[15:0] = num_sectors - 1
++ tmp = flash_read_long(info, 0,
++ FLASH_OFFSET_ERASE_REGIONS + i * 4);
++ debug("CFI erase block region info[%d]: 0x%08x, ",
++ i, tmp);
++ erase_region_count = (tmp & 0xffff) + 1;
++ tmp >>= 16;
++ erase_region_size = (tmp ? tmp * 256 : 128);
++ debug ("erase_region_count=%d erase_region_size=%d\n",
++ erase_region_count, erase_region_size);
++#if 0
++ erase_region_size = CFG_FLASH_SECTOR_SIZE; // Commented out
++ erase_region_count = CFG_FLASH_SECTOR_COUNT; // Commented out
++#endif
++ if (sect_cnt + erase_region_count > CONFIG_SYS_MAX_FLASH_SECT) {
++ printf("Warning: Erase region %d adds too many flash sectors"
++ " %d+%d; reducing to fit total limit of %d\n",
++ i, sect_cnt, erase_region_count, CONFIG_SYS_MAX_FLASH_SECT);
++ erase_region_count = CONFIG_SYS_MAX_FLASH_SECT - sect_cnt;
++ }
++ for (j = 0; j < erase_region_count; j++) {
++ info->start[sect_cnt] = sector;
++ sector += (erase_region_size * size_ratio);
++
++ /*
++ * Only read protection status from supported devices (intel...)
++ */
++ switch (info->vendor) {
++ case CFI_CMDSET_INTEL_EXTENDED:
++ case CFI_CMDSET_INTEL_STANDARD:
++ info->protect[sect_cnt] =
++ flash_isset (info, sect_cnt,
++ FLASH_OFFSET_PROTECT,
++ FLASH_STATUS_PROTECT);
++ break;
++ default:
++ info->protect[sect_cnt] = 0; /* default: not protected */
++ }
++
++ sect_cnt++;
++ }
++ }
++
++ info->sector_count = sect_cnt;
++ /* multiply the size by the number of chips */
++ // info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio;
++ // Use only the sectors that fit within the flash_info array size.
++ info->size = sector - base;
++ printf("Flash bank %d at %08x has 0x%x bytes in %d sectors"
++ " (chipSize 1<<%d, size_ratio %d).\n",
++ banknum, base, info->size, info->sector_count,
++ flash_read_uchar(info, FLASH_OFFSET_SIZE), size_ratio);
++
++ info->buffer_size = (1 << flash_read_uchar (info, FLASH_OFFSET_BUFFER_SIZE));
++ /* Limit the buffer size to 32bytes to meet most of AMD-styles flash's minimum requirement */
++ if (info->buffer_size > 32)
++ info->buffer_size = 32;
++ tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
++ info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
++ tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
++ info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
++ tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
++ info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
++ info->flash_id = FLASH_MAN_CFI;
++#if 0
++ if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
++ info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */
++ }
++#endif
++ }
++
++ flash_write_cmd (info, 0, 0, info->cmd_reset);
++ return (info->size);
++}
++
++
++/*-----------------------------------------------------------------------
++ */
++static int flash_write_cfiword (flash_info_t * info, ulong dest,
++ cfiword_t cword)
++{
++
++ cfiptr_t ctladdr;
++ cfiptr_t cptr;
++ int flag;
++
++ ctladdr.cp = flash_make_addr (info, 0, 0);
++ cptr.cp = (uchar *) dest;
++
++
++ /* Check if Flash is (sufficiently) erased */
++ switch (info->portwidth) {
++ case FLASH_CFI_8BIT:
++ flag = ((cptr.cp[0] & cword.c) == cword.c);
++ break;
++ case FLASH_CFI_16BIT:
++ flag = ((cptr.wp[0] & cword.w) == cword.w);
++ break;
++ case FLASH_CFI_32BIT:
++ flag = ((cptr.lp[0] & cword.l) == cword.l);
++ break;
++ case FLASH_CFI_64BIT:
++ flag = ((cptr.llp[0] & cword.ll) == cword.ll);
++ break;
++ default:
++ return 2;
++ }
++ if (!flag)
++ return 2;
++
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts ();
++
++ switch (info->vendor) {
++ case CFI_CMDSET_INTEL_EXTENDED:
++ case CFI_CMDSET_INTEL_STANDARD:
++ flash_write_cmd_nodbg (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
++ flash_write_cmd_nodbg (info, 0, 0, FLASH_CMD_WRITE);
++ break;
++ case CFI_CMDSET_AMD_EXTENDED:
++ case CFI_CMDSET_AMD_STANDARD:
++ flash_unlock_seq (info, 0);
++ flash_write_cmd_nodbg (info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
++ break;
++ }
++
++ switch (info->portwidth) {
++ case FLASH_CFI_8BIT:
++ cptr.cp[0] = cword.c;
++ break;
++ case FLASH_CFI_16BIT:
++ cptr.wp[0] = cword.w;
++ break;
++ case FLASH_CFI_32BIT:
++ cptr.lp[0] = cword.l;
++ break;
++ case FLASH_CFI_64BIT:
++ cptr.llp[0] = cword.ll;
++ break;
++ }
++
++ /* re-enable interrupts if necessary */
++ if (flag)
++ enable_interrupts ();
++
++ return flash_full_status_check (info, 0, info->write_tout, "write");
++}
++
++#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
++
++/* loop through the sectors from the highest address
++ * when the passed address is greater or equal to the sector address
++ * we have a match
++ */
++static flash_sect_t find_sector (flash_info_t * info, ulong addr)
++{
++ flash_sect_t sector;
++
++ for (sector = info->sector_count - 1; sector >= 0; sector--) {
++ if (addr >= info->start[sector])
++ break;
++ }
++ return sector;
++}
++
++static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
++ int len)
++{
++ flash_sect_t sector;
++ int cnt;
++ int retcode;
++ volatile cfiptr_t src;
++ volatile cfiptr_t dst;
++
++/* Add AMD write buffer mode support, ycchen@102006 */
++#if 0
++ /* buffered writes in the AMD chip set is not supported yet */
++ if((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
++ (info->vendor == CFI_CMDSET_AMD_EXTENDED))
++ return ERR_INVAL;
++#endif
++ if((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
++ (info->vendor == CFI_CMDSET_AMD_EXTENDED))
++ {
++ retcode = flash_write_cfibuffer_amd(info, dest, cp, len);
++ return retcode;
++ }
++
++ src.cp = cp;
++ dst.cp = (uchar *) dest;
++ sector = find_sector (info, dest);
++ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
++ flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
++ if ((retcode =
++ flash_status_check (info, sector, info->buffer_write_tout,
++ "write to buffer")) == ERR_OK) {
++ /* reduce the number of loops by the width of the port */
++ switch (info->portwidth) {
++ case FLASH_CFI_8BIT:
++ cnt = len;
++ break;
++ case FLASH_CFI_16BIT:
++ cnt = len >> 1;
++ break;
++ case FLASH_CFI_32BIT:
++ cnt = len >> 2;
++ break;
++ case FLASH_CFI_64BIT:
++ cnt = len >> 3;
++ break;
++ default:
++ return ERR_INVAL;
++ break;
++ }
++ flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
++ while (cnt-- > 0) {
++ switch (info->portwidth) {
++ case FLASH_CFI_8BIT:
++ *dst.cp++ = *src.cp++;
++ break;
++ case FLASH_CFI_16BIT:
++ *dst.wp++ = *src.wp++;
++ break;
++ case FLASH_CFI_32BIT:
++ *dst.lp++ = *src.lp++;
++ break;
++ case FLASH_CFI_64BIT:
++ *dst.llp++ = *src.llp++;
++ break;
++ default:
++ return ERR_INVAL;
++ break;
++ }
++ }
++ flash_write_cmd (info, sector, 0,
++ FLASH_CMD_WRITE_BUFFER_CONFIRM);
++ retcode =
++ flash_full_status_check (info, sector,
++ info->buffer_write_tout,
++ "buffer write");
++ }
++ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
++ return retcode;
++}
++
++
++static int flash_write_cfibuffer_amd (flash_info_t * info, ulong dest, uchar * cp,
++ int len)
++{
++ flash_sect_t sector;
++ int cnt;
++ int retcode;
++ volatile cfiptr_t src;
++ volatile cfiptr_t dst;
++ volatile cfiword_t tmpsrc, tmpdst;
++
++ src.cp = cp;
++ dst.cp = (uchar *) dest;
++ sector = find_sector (info, dest);
++ flash_unlock_seq (info, 0);
++ if ((retcode =
++ flash_status_check (info, sector, info->buffer_write_tout,
++ "write to buffer")) == ERR_OK) {
++ /* reduce the number of loops by the width of the port */
++ switch (info->portwidth) {
++ case FLASH_CFI_8BIT:
++ cnt = len;
++ *dst.cp = (uchar) (AMD_CMD_WRITE_TO_BUFFER);
++ *dst.cp = (uchar) (cnt -1);
++ break;
++ case FLASH_CFI_16BIT:
++ cnt = len >> 1;
++ *dst.wp = (unsigned short) (AMD_CMD_WRITE_TO_BUFFER);
++ *dst.wp = (unsigned short) (cnt -1);
++ break;
++ case FLASH_CFI_32BIT:
++ cnt = len >> 2;
++ *dst.lp = (unsigned long) (AMD_CMD_WRITE_TO_BUFFER);
++ *dst.lp = (unsigned long) (cnt -1);
++ break;
++ case FLASH_CFI_64BIT:
++ cnt = len >> 3;
++ *dst.llp = (unsigned long long) (AMD_CMD_WRITE_TO_BUFFER);
++ *dst.llp = (unsigned long long) (cnt -1);
++ break;
++ default:
++ return ERR_INVAL;
++ break;
++ }
++ while (cnt-- > 0) {
++ switch (info->portwidth) {
++ case FLASH_CFI_8BIT:
++ *dst.cp++ = *src.cp++;
++ break;
++ case FLASH_CFI_16BIT:
++ *dst.wp++ = *src.wp++;
++ break;
++ case FLASH_CFI_32BIT:
++ *dst.lp++ = *src.lp++;
++ break;
++ case FLASH_CFI_64BIT:
++ *dst.llp++ = *src.llp++;
++ break;
++ default:
++ return ERR_INVAL;
++ break;
++ }
++ }
++ switch (info->portwidth) {
++ case FLASH_CFI_8BIT:
++ src.cp--;
++ dst.cp--;
++ *dst.cp = (unsigned char) (AMD_CMD_BUFFER_TO_FLASH);
++ tmpsrc.c = *src.cp & 0x80;
++
++ do {
++ tmpdst.c = *(volatile uchar *)(dst.cp);
++
++ if (tmpdst.c & 0x20) { /* toggle DQ5 */
++ tmpdst.c = *(volatile uchar *)(dst.cp);
++ if ((tmpdst.c & 0x80) != tmpsrc.c)
++ {
++ printf("program error occurred\n");
++ flash_write_cmd (info, sector, 0, info->cmd_reset);
++ return ERR_PROG_ERROR;
++ }
++ }
++ else if (tmpdst.c & 0x02) { /* toggle DQ1 */
++ tmpdst.c = *(volatile uchar *)(dst.cp);
++ if ((tmpdst.c & 0x80) != tmpsrc.c)
++ {
++ printf("write buffer error occurred \n");
++ write_buffer_abort_reset(info, sector);
++ return ERR_PROG_ERROR;
++ }
++ }
++
++ } while ((tmpdst.c & 0x80) != tmpsrc.c);
++
++ break;
++ case FLASH_CFI_16BIT:
++ src.wp--;
++ dst.wp--;
++ *dst.wp = (unsigned short) (AMD_CMD_BUFFER_TO_FLASH);
++ tmpsrc.w = *src.wp & 0x80;
++
++ do {
++ tmpdst.w = *(volatile short *)(dst.wp);
++
++ if (tmpdst.w & 0x20) { /* toggle DQ5 */
++ tmpdst.w = *(volatile ushort *)(dst.wp);
++ if ((tmpdst.w & 0x80) != tmpsrc.w)
++ {
++ printf("program error occurred\n");
++ flash_write_cmd (info, sector, 0, info->cmd_reset);
++ return ERR_PROG_ERROR;
++ }
++ }
++ else if (tmpdst.w & 0x02) { /* toggle DQ1 */
++ tmpdst.w = *(volatile ushort *)(dst.wp);
++ if ((tmpdst.w & 0x80) != tmpsrc.w)
++ {
++ printf("write buffer error occurred \n");
++ write_buffer_abort_reset(info, sector);
++ return ERR_PROG_ERROR;
++ }
++ }
++
++ } while ((tmpdst.w & 0x80) != tmpsrc.w);
++
++ break;
++ case FLASH_CFI_32BIT:
++ src.lp--;
++ dst.lp--;
++ *dst.lp = (unsigned long) (AMD_CMD_BUFFER_TO_FLASH);
++ tmpsrc.l = *src.lp & 0x80;
++
++ do {
++ tmpdst.l = *(volatile ulong *)(dst.lp);
++
++ if (tmpdst.l & 0x20) { /* toggle DQ5 */
++ tmpdst.l = *(volatile ulong *)(dst.lp);
++ if ((tmpdst.l & 0x80) != tmpsrc.l)
++ {
++ printf("program error occurred\n");
++ flash_write_cmd (info, sector, 0, info->cmd_reset);
++ return ERR_PROG_ERROR;
++ }
++ }
++ else if (tmpdst.l & 0x02) { /* toggle DQ1 */
++ tmpdst.l = *(volatile ulong *)(dst.lp);
++ if ((tmpdst.l & 0x80) != tmpsrc.l)
++ {
++ printf("write buffer error occurred \n");
++ write_buffer_abort_reset(info, sector);
++ return ERR_PROG_ERROR;
++ }
++ }
++
++ } while ((tmpdst.l & 0x80) != tmpsrc.l);
++
++ break;
++ case FLASH_CFI_64BIT:
++ src.llp--;
++ dst.llp--;
++ *dst.llp = (unsigned long long) (AMD_CMD_BUFFER_TO_FLASH);
++ tmpsrc.ll = *src.llp & 0x80;
++
++ do {
++ tmpdst.ll = *(volatile unsigned long long *)(dst.llp);
++
++ if (tmpdst.ll & 0x20) { /* toggle DQ5 */
++ tmpdst.ll = *(volatile unsigned long long *)(dst.llp);
++ if ((tmpdst.ll & 0x80) != tmpsrc.ll)
++ {
++ printf("program error occurred\n");
++ flash_write_cmd (info, sector, 0, info->cmd_reset);
++ return ERR_PROG_ERROR;
++ }
++ }
++ else if (tmpdst.ll & 0x02) { /* toggle DQ1 */
++ tmpdst.ll = *(volatile unsigned long long *)(dst.llp);
++ if ((tmpdst.ll & 0x80) != tmpsrc.ll)
++ {
++ printf("write buffer error occurred \n");
++ write_buffer_abort_reset(info, sector);
++ return ERR_PROG_ERROR;
++ }
++ }
++
++ } while ((tmpdst.ll & 0x80) != tmpsrc.ll);
++
++ break;
++ default:
++ return ERR_INVAL;
++ break;
++ }
++
++ retcode =
++ flash_full_status_check (info, sector,
++ info->buffer_write_tout,
++ "buffer write");
++ }
++
++ return retcode;
++}
++#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
++
++#ifdef CONFIG_FLASH_AST2300_DMA
++#define STCBaseAddress 0x1e620000
++
++/* for DMA */
++#define REG_FLASH_INTERRUPT_STATUS 0x08
++#define REG_FLASH_DMA_CONTROL 0x80
++#define REG_FLASH_DMA_FLASH_BASE 0x84
++#define REG_FLASH_DMA_DRAM_BASE 0x88
++#define REG_FLASH_DMA_LENGTH 0x8c
++
++#define FLASH_STATUS_DMA_BUSY 0x0000
++#define FLASH_STATUS_DMA_READY 0x0800
++#define FLASH_STATUS_DMA_CLEAR 0x0800
++
++#define FLASH_DMA_ENABLE 0x01
++
++void * memmove_dma(void * dest,const void *src,size_t count)
++{
++ ulong count_align, poll_time, data;
++
++ count_align = (count + 3) & 0xFFFFFFFC; /* 4-bytes align */
++ poll_time = 100; /* set 100 us as default */
++
++ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (~FLASH_DMA_ENABLE);
++
++ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_FLASH_BASE) = (ulong *) (src);
++ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_DRAM_BASE) = (ulong *) (dest);
++ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_LENGTH) = (ulong) (count_align);
++ udelay(10);
++ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (FLASH_DMA_ENABLE);
++
++ /* wait poll */
++ do {
++ udelay(poll_time);
++ data = *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS);
++ } while (!(data & FLASH_STATUS_DMA_READY));
++
++ /* clear status */
++ *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS) |= FLASH_STATUS_DMA_CLEAR;
++}
++#endif
++#endif /* CFG_FLASH_CFI */
+diff --git a/board/aspeed/ast2300/flash_spi.c b/board/aspeed/ast2300/flash_spi.c
+new file mode 100755
+index 0000000..6660628
+--- /dev/null
++++ b/board/aspeed/ast2300/flash_spi.c
+@@ -0,0 +1,1639 @@
++/*
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * History
++ * 01/20/2004 - combined variants of original driver.
++ * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
++ * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
++ * 01/27/2004 - Little endian support Ed Okerson
++ *
++ * Tested Architectures
++ * Port Width Chip Width # of banks Flash Chip Board
++ * 32 16 1 28F128J3 seranoa/eagle
++ * 64 16 1 28F128J3 seranoa/falcon
++ *
++ */
++
++/* The DEBUG define must be before common to enable debugging */
++/* #define DEBUG */
++
++#include <common.h>
++#include <asm/processor.h>
++#include <asm/byteorder.h>
++#include <environment.h>
++#ifdef CONFIG_FLASH_SPI
++
++/*
++ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
++ * The width of the port and the width of the chips are determined at initialization.
++ * These widths are used to calculate the address for access CFI data structures.
++ * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
++ *
++ * References
++ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
++ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
++ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
++ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
++ *
++ * TODO
++ *
++ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
++ * Table (ALT) to determine if protection is available
++ *
++ * Add support for other command sets Use the PRI and ALT to determine command set
++ * Verify erase and program timeouts.
++ */
++
++#ifndef CONFIG_FLASH_BANKS_LIST
++#define CONFIG_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
++#endif
++
++/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
++#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
++static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS_DETECT] = CONFIG_FLASH_BANKS_LIST;
++flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
++#else
++static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_FLASH_BANKS_LIST;
++flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
++#endif
++
++/* Support Flash ID */
++#define STM25P64 0x172020
++#define STM25P128 0x182020
++#define N25Q256 0x19ba20
++#define N25Q512 0x20ba20
++#define S25FL064A 0x160201
++#define S25FL128P 0x182001
++#define S25FL256S 0x190201
++#define W25X16 0x1530ef
++#define W25X64 0x1730ef
++#define W25Q64BV 0x1740ef
++#define W25Q128BV 0x1840ef
++#define W25Q256FV 0x1940ef
++#define MX25L1605D 0x1520C2
++#define MX25L12805D 0x1820C2
++#define MX25L25635E 0x1920C2
++#define SST25VF016B 0x4125bf
++#define SST25VF064C 0x4b25bf
++#define AT25DF161 0x02461F
++#define AT25DF321 0x01471F
++
++/* SPI Define */
++#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
++#if defined(CONFIG_AST1300)
++#define STCBaseAddress 0x00620000
++#else
++#define STCBaseAddress 0x1e620000
++#endif
++#define SCU_REVISION_REGISTER 0x1e6e207c
++#define SCU_CACHE_CTRL_REGISTER 0x1e6e2118
++
++#define SPICtrlRegOffset 0x10
++#define SPICtrlRegOffset2 0x14
++
++#define SPIMiscCtrlRegOffset 0x54
++
++/* for DMA */
++#define REG_FLASH_INTERRUPT_STATUS 0x08
++#define REG_FLASH_DMA_CONTROL 0x80
++#define REG_FLASH_DMA_FLASH_BASE 0x84
++#define REG_FLASH_DMA_DRAM_BASE 0x88
++#define REG_FLASH_DMA_LENGTH 0x8c
++
++#define FLASH_STATUS_DMA_BUSY 0x0000
++#define FLASH_STATUS_DMA_READY 0x0800
++#define FLASH_STATUS_DMA_CLEAR 0x0800
++
++#define FLASH_DMA_ENABLE 0x01
++#else
++#define STCBaseAddress 0x16000000
++
++#define SPICtrlRegOffset 0x04
++#define SPICtrlRegOffset2 0x0C
++#endif /* CONFIG_FLASH_AST2300 */
++
++#define CMD_MASK 0xFFFFFFF8
++
++#define NORMALREAD 0x00
++#define FASTREAD 0x01
++#define NORMALWRITE 0x02
++#define USERMODE 0x03
++
++#define CE_LOW 0x00
++#define CE_HIGH 0x04
++
++/* AST2300 only */
++#define IOMODEx1 0x00000000
++#define IOMODEx2 0x20000000
++#define IOMODEx2_dummy 0x30000000
++#define IOMODEx4 0x40000000
++#define IOMODEx4_dummy 0x50000000
++
++#define DUMMY_COMMAND_OUT 0x00008000
++/* ~AST2300 only */
++
++/* specificspi */
++#define SpecificSPI_N25Q512 0x00000001
++
++static ulong AST2300_SPICLK_DIV[16] = {0x0F, 0x07, 0x0E, 0x06, 0x0D, 0x05, 0x0C, 0x04, \
++ 0x0B, 0x03, 0x0A, 0x02, 0x09, 0x01, 0x08, 0x00 };
++
++/*-----------------------------------------------------------------------
++ * Functions
++ */
++static void reset_flash (flash_info_t * info);
++static void enable_write (flash_info_t * info);
++static void write_status_register (flash_info_t * info, uchar data);
++static void enable4b (flash_info_t * info);
++static void enable4b_spansion (flash_info_t * info);
++static void enable4b_numonyx (flash_info_t * info);
++static ulong flash_get_size (ulong base, int banknum);
++static int flash_write_buffer (flash_info_t *info, uchar *src, ulong addr, int len);
++#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
++static flash_info_t *flash_get_info(ulong base);
++#endif
++
++
++/*-----------------------------------------------------------------------
++ * create an address based on the offset and the port width
++ */
++inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
++{
++#ifdef CONFIG_2SPIFLASH
++ if (info->start[0] >= PHYS_FLASH_2)
++ return ((uchar *) (info->start[sect] + (offset * 1) - (PHYS_FLASH_2 - PHYS_FLASH_2_BASE) ));
++ else
++ return ((uchar *) (info->start[sect] + (offset * 1)));
++#else
++ return ((uchar *) (info->start[sect] + (offset * 1)));
++#endif
++}
++
++/*-----------------------------------------------------------------------
++ * read a character at a port width address
++ */
++inline uchar flash_read_uchar (flash_info_t * info, uint offset)
++{
++ uchar *cp;
++
++ cp = flash_make_addr (info, 0, offset);
++#if defined(__LITTLE_ENDIAN)
++ return (cp[0]);
++#else
++ return (cp[1 - 1]);
++#endif
++}
++
++/*-----------------------------------------------------------------------
++ * read a short word by swapping for ppc format.
++ */
++ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
++{
++ uchar *addr;
++ ushort retval;
++
++#ifdef DEBUG
++ int x;
++#endif
++ addr = flash_make_addr (info, sect, offset);
++
++#ifdef DEBUG
++ debug ("ushort addr is at %p 1 = %d\n", addr,
++ 1);
++ for (x = 0; x < 2 * 1; x++) {
++ debug ("addr[%x] = 0x%x\n", x, addr[x]);
++ }
++#endif
++#if defined(__LITTLE_ENDIAN)
++ retval = ((addr[(1)] << 8) | addr[0]);
++#else
++ retval = ((addr[(2 * 1) - 1] << 8) |
++ addr[1 - 1]);
++#endif
++
++ debug ("retval = 0x%x\n", retval);
++ return retval;
++}
++
++/*-----------------------------------------------------------------------
++ * read a long word by picking the least significant byte of each maiximum
++ * port size word. Swap for ppc format.
++ */
++ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
++{
++ uchar *addr;
++ ulong retval;
++
++#ifdef DEBUG
++ int x;
++#endif
++ addr = flash_make_addr (info, sect, offset);
++
++#ifdef DEBUG
++ debug ("long addr is at %p 1 = %d\n", addr,
++ 1);
++ for (x = 0; x < 4 * 1; x++) {
++ debug ("addr[%x] = 0x%x\n", x, addr[x]);
++ }
++#endif
++#if defined(__LITTLE_ENDIAN)
++ retval = (addr[0] << 16) | (addr[(1)] << 24) |
++ (addr[(2 * 1)]) | (addr[(3 * 1)] << 8);
++#else
++ retval = (addr[(2 * 1) - 1] << 24) |
++ (addr[(1) - 1] << 16) |
++ (addr[(4 * 1) - 1] << 8) |
++ addr[(3 * 1) - 1];
++#endif
++ return retval;
++}
++
++/*-----------------------------------------------------------------------
++ */
++static void disable_cache(void)
++{
++#if defined(AST1300_CPU_CACHE_ENABLE)
++ ulong uldata;
++
++ uldata = *(volatile ulong *) (SCU_CACHE_CTRL_REGISTER);
++ uldata &= 0xfffffffd;
++ *(ulong *) (SCU_CACHE_CTRL_REGISTER) = uldata;
++#endif
++}
++
++static void enable_cache(void)
++{
++#if defined(AST1300_CPU_CACHE_ENABLE)
++ ulong uldata;
++
++ uldata = *(volatile ulong *) (SCU_CACHE_CTRL_REGISTER);
++ uldata |= 0x00000002;
++ *(ulong *) (SCU_CACHE_CTRL_REGISTER) = uldata;
++#endif
++}
++
++static void reset_flash (flash_info_t * info)
++{
++ ulong ulCtrlData, CtrlOffset, MiscCtrlOffset;
++
++ if (info->CE == 2)
++ {
++ CtrlOffset = SPICtrlRegOffset2;
++ }
++ else
++ {
++ CtrlOffset = SPICtrlRegOffset;
++ }
++
++#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
++ ulCtrlData = info->iomode | (info->readcmd << 16) | (info->tCK_Read << 8) | (info->dummybyte << 6) | FASTREAD;
++#if 0
++ if (info->quadport)
++ {
++ MiscCtrlOffset = SPIMiscCtrlRegOffset;
++ *(ulong *) (STCBaseAddress + MiscCtrlOffset) = info->dummydata;
++ ulCtrlData |= DUMMY_COMMAND_OUT;
++ }
++#endif
++#else
++ ulCtrlData = (info->readcmd << 16) | (info->tCK_Read << 8) | (info->dummybyte << 6) | FASTREAD;
++ if (info->dualport)
++ ulCtrlData |= 0x08;
++#endif
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++
++ enable_cache();
++}
++
++static void enable_write (flash_info_t * info)
++{
++ ulong base;
++ ulong ulCtrlData, CtrlOffset;
++ uchar jReg;
++
++ if (info->CE == 2)
++ {
++ CtrlOffset = SPICtrlRegOffset2;
++ }
++ else
++ {
++ CtrlOffset = SPICtrlRegOffset;
++ }
++
++ //base = info->start[0];
++ base = flash_make_addr (info, 0, 0);
++
++ ulCtrlData = (info->tCK_Write << 8);
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0x06);
++ udelay(10);
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0x05);
++ udelay(10);
++ do {
++ jReg = *(volatile uchar *) (base);
++ } while (!(jReg & 0x02));
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++
++}
++
++static void write_status_register (flash_info_t * info, uchar data)
++{
++ ulong base;
++ ulong ulSMMBase, ulCtrlData, CtrlOffset;
++ uchar jReg;
++
++ if (info->CE == 2)
++ {
++ CtrlOffset = SPICtrlRegOffset2;
++ }
++ else
++ {
++ CtrlOffset = SPICtrlRegOffset;
++ }
++
++ //base = info->start[0];
++ base = flash_make_addr (info, 0, 0);
++
++ enable_write (info);
++
++ ulCtrlData = (info->tCK_Write << 8);
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0x01);
++ udelay(10);
++ *(uchar *) (base) = (uchar) (data);
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0x05);
++ udelay(10);
++ do {
++ jReg = *(volatile uchar *) (base);
++ } while (jReg & 0x01);
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++
++}
++
++static void enable4b (flash_info_t * info)
++{
++ ulong base;
++ ulong ulSMMBase, ulCtrlData, CtrlOffset;
++ uchar jReg;
++
++ if (info->CE == 2)
++ {
++ CtrlOffset = SPICtrlRegOffset2;
++ }
++ else
++ {
++ CtrlOffset = SPICtrlRegOffset;
++ }
++
++ //base = info->start[0];
++ base = flash_make_addr (info, 0, 0);
++
++ ulCtrlData = (info->tCK_Write << 8);
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0xb7);
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++
++} /* enable4b */
++
++static void enable4b_spansion (flash_info_t * info)
++{
++ ulong base;
++ ulong ulSMMBase, ulCtrlData, CtrlOffset;
++ uchar jReg;
++
++ if (info->CE == 2)
++ {
++ CtrlOffset = SPICtrlRegOffset2;
++ }
++ else
++ {
++ CtrlOffset = SPICtrlRegOffset;
++ }
++
++ //base = info->start[0];
++ base = flash_make_addr (info, 0, 0);
++
++ /* Enable 4B: BAR0 D[7] = 1 */
++ ulCtrlData = (info->tCK_Write << 8);
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0x17);
++ udelay(10);
++ *(uchar *) (base) = (uchar) (0x80);
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0x16);
++ udelay(10);
++ do {
++ jReg = *(volatile uchar *) (base);
++ } while (!(jReg & 0x80));
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++
++} /* enable4b_spansion */
++
++static void enable4b_numonyx (flash_info_t * info)
++{
++ ulong base;
++ ulong ulSMMBase, ulCtrlData, CtrlOffset;
++ uchar jReg;
++
++ if (info->CE == 2)
++ {
++ CtrlOffset = SPICtrlRegOffset2;
++ }
++ else
++ {
++ CtrlOffset = SPICtrlRegOffset;
++ }
++
++ //base = info->start[0];
++ base = flash_make_addr (info, 0, 0);
++
++ /* Enable Write */
++ enable_write (info);
++
++ /* Enable 4B: CMD:0xB7 */
++ ulCtrlData = (info->tCK_Write << 8);
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0xB7);
++ udelay(10);
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++
++} /* enable4b_numonyx */
++
++/*
++ *
++ */
++static ulong flash_get_size (ulong base, int banknum)
++{
++ flash_info_t *info = &flash_info[banknum];
++ int j;
++ unsigned long sector;
++ int erase_region_size;
++ ulong ulCtrlData, CtrlOffset;
++ ulong ulID;
++ uchar ch[3];
++ ulong cpuclk, div, reg;
++ ulong WriteClk, EraseClk, ReadClk;
++ ulong vbase;
++ ulong SCURevision;
++
++ ulong ulRefPLL;
++ ulong ulDeNumerator;
++ ulong ulNumerator;
++ ulong ulOD;
++
++ disable_cache();
++
++ info->start[0] = base;
++ vbase = flash_make_addr (info, 0, 0);
++
++#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
++ CtrlOffset = SPICtrlRegOffset;
++ info->CE = 0;
++#else
++ if (vbase == PHYS_FLASH_1)
++ {
++ CtrlOffset = SPICtrlRegOffset2;
++ info->CE = 2;
++ }
++ else
++ {
++ CtrlOffset = SPICtrlRegOffset;
++ info->CE = 0;
++ }
++#endif
++
++ /* Get Flash ID */
++ ulCtrlData = *(ulong *) (STCBaseAddress + CtrlOffset) & CMD_MASK;
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (vbase) = (uchar) (0x9F);
++ udelay(10);
++ ch[0] = *(volatile uchar *)(vbase);
++ udelay(10);
++ ch[1] = *(volatile uchar *)(vbase);
++ udelay(10);
++ ch[2] = *(volatile uchar *)(vbase);
++ udelay(10);
++ ulCtrlData = *(ulong *) (STCBaseAddress + CtrlOffset) & CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ ulID = ((ulong)ch[0]) | ((ulong)ch[1] << 8) | ((ulong)ch[2] << 16) ;
++ info->flash_id = ulID;
++
++ //printf("SPI Flash ID: %x \n", ulID);
++
++ /* init default */
++ info->iomode = IOMODEx1;
++ info->address32 = 0;
++ info->quadport = 0;
++ info->specificspi = 0;
++
++ switch (info->flash_id)
++ {
++ case STM25P64:
++ info->sector_count = 128;
++ info->size = 0x800000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 256;
++ WriteClk = 40;
++ EraseClk = 20;
++ ReadClk = 40;
++ break;
++
++ case STM25P128:
++ info->sector_count = 64;
++ info->size = 0x1000000;
++ erase_region_size = 0x40000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 256;
++ WriteClk = 50;
++ EraseClk = 20;
++ ReadClk = 50;
++ break;
++
++ case N25Q256:
++ info->sector_count = 256;
++ info->size = 0x1000000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 256;
++ WriteClk = 50;
++ EraseClk = 20;
++ ReadClk = 50;
++#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
++ info->sector_count = 512;
++ info->size = 0x2000000;
++ info->address32 = 1;
++#endif
++ break;
++
++ case N25Q512:
++ info->sector_count = 256;
++ info->size = 0x1000000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 256;
++ info->specificspi = SpecificSPI_N25Q512;
++ WriteClk = 50;
++ EraseClk = 20;
++ ReadClk = 50;
++#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
++ info->sector_count = 1024;
++ info->size = 0x4000000;
++ info->address32 = 1;
++#endif
++ break;
++
++ case W25X16:
++ info->sector_count = 32;
++ info->size = 0x200000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x3b;
++ info->dualport = 1;
++ info->dummybyte = 1;
++ info->iomode = IOMODEx2;
++ info->buffersize = 256;
++ WriteClk = 50;
++ EraseClk = 25;
++ ReadClk = 50;
++ break;
++
++ case W25X64:
++ info->sector_count = 128;
++ info->size = 0x800000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x3b;
++ info->dualport = 1;
++ info->dummybyte = 1;
++ info->iomode = IOMODEx2;
++ info->buffersize = 256;
++ WriteClk = 50;
++ EraseClk = 25;
++ ReadClk = 50;
++ break;
++
++ case W25Q64BV:
++ info->sector_count = 128;
++ info->size = 0x800000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x3b;
++ info->dualport = 1;
++ info->dummybyte = 1;
++ info->iomode = IOMODEx2;
++ info->buffersize = 256;
++ WriteClk = 80;
++ EraseClk = 40;
++ ReadClk = 80;
++ break;
++
++ case W25Q128BV:
++ info->sector_count = 256;
++ info->size = 0x1000000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x3b;
++ info->dualport = 1;
++ info->dummybyte = 1;
++ info->iomode = IOMODEx2;
++ info->buffersize = 256;
++ WriteClk = 104;
++ EraseClk = 50;
++ ReadClk = 104;
++ break;
++
++ case W25Q256FV:
++ info->sector_count = 256;
++ info->size = 0x1000000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 256;
++ WriteClk = 50;
++ EraseClk = 20;
++ ReadClk = 50;
++#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
++ info->sector_count = 512;
++ info->size = 0x2000000;
++ info->address32 = 1;
++#endif
++ break;
++
++ case S25FL064A:
++ info->sector_count = 128;
++ info->size = 0x800000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 256;
++ WriteClk = 50;
++ EraseClk = 25;
++ ReadClk = 50;
++ break;
++
++ case S25FL128P:
++ info->sector_count = 256;
++ info->size = 0x1000000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 256;
++ WriteClk = 100;
++ EraseClk = 40;
++ ReadClk = 100;
++ break;
++
++ case S25FL256S:
++ info->sector_count = 256;
++ info->size = 0x1000000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 256;
++ WriteClk = 50;
++ EraseClk = 20;
++ ReadClk = 50;
++#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
++ info->sector_count = 512;
++ info->size = 0x2000000;
++ info->address32 = 1;
++#endif
++ break;
++
++ case MX25L25635E:
++ info->sector_count = 256;
++ info->size = 0x1000000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 256;
++ WriteClk = 50;
++ EraseClk = 20;
++ ReadClk = 50;
++#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
++ info->sector_count = 512;
++ info->size = 0x2000000;
++ info->address32 = 1;
++#if defined(CONFIG_FLASH_SPIx2_Dummy)
++ info->readcmd = 0xbb;
++ info->dummybyte = 1;
++ info->dualport = 1;
++ info->iomode = IOMODEx2_dummy;
++#elif defined(CONFIG_FLASH_SPIx4_Dummy)
++ info->readcmd = 0xeb;
++ info->dummybyte = 3;
++ info->dualport = 0;
++ info->iomode = IOMODEx4_dummy;
++ info->quadport = 1;
++ info->dummydata = 0xaa;
++#endif
++#endif
++ break;
++
++ case MX25L12805D:
++ info->sector_count = 256;
++ info->size = 0x1000000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 256;
++/*
++SCU7C: Silicon Revision ID Register
++D[31:24]: Chip ID
++0: AST2050/AST2100/AST2150/AST2200/AST3000
++1: AST2300
++
++D[23:16] Silicon revision ID for AST2300 generation and later
++0: A0
++1: A1
++2: A2
++.
++.
++.
++FPGA revision starts from 0x80
++
++AST2300 A0 SPI can't run faster than 50Mhz
++*/
++ WriteClk = 50;
++ EraseClk = 20;
++ ReadClk = 50;
++
++ SCURevision = *(ulong *) (SCU_REVISION_REGISTER);
++ if (((SCURevision >> 24) & 0xff) == 0x01) { //AST2300
++ if (((SCURevision >> 16) & 0xff) == 0x00) { //A0
++ WriteClk = 25;
++ EraseClk = 20;
++ ReadClk = 25;
++ }
++ }
++#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
++#if defined(CONFIG_FLASH_SPIx2_Dummy)
++ info->readcmd = 0xbb;
++ info->dummybyte = 1;
++ info->dualport = 1;
++ info->iomode = IOMODEx2_dummy;
++#elif defined(CONFIG_FLASH_SPIx4_Dummy)
++ info->readcmd = 0xeb;
++ info->dummybyte = 3;
++ info->dualport = 0;
++ info->iomode = IOMODEx4_dummy;
++ info->quadport = 1;
++ info->dummydata = 0xaa;
++#endif
++#endif
++ break;
++
++ case MX25L1605D:
++ info->sector_count = 32;
++ info->size = 0x200000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 256;
++ WriteClk = 50;
++ EraseClk = 20;
++ ReadClk = 50;
++ break;
++
++ case SST25VF016B:
++ info->sector_count = 32;
++ info->size = 0x200000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 1;
++ WriteClk = 50;
++ EraseClk = 25;
++ ReadClk = 50;
++ break;
++
++ case SST25VF064C:
++ info->sector_count = 128;
++ info->size = 0x800000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 1;
++ WriteClk = 50;
++ EraseClk = 25;
++ ReadClk = 50;
++ break;
++
++ case AT25DF161:
++ info->sector_count = 32;
++ info->size = 0x200000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 1;
++ WriteClk = 50;
++ EraseClk = 25;
++ ReadClk = 50;
++ break;
++
++ case AT25DF321:
++ info->sector_count = 32;
++ info->size = 0x400000;
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 1;
++ WriteClk = 50;
++ EraseClk = 25;
++ ReadClk = 50;
++ break;
++
++ default: /* use JEDEC ID */
++ erase_region_size = 0x10000;
++ info->readcmd = 0x0b;
++ info->dualport = 0;
++ info->dummybyte = 1;
++ info->buffersize = 1;
++ WriteClk = 50;
++ EraseClk = 25;
++ ReadClk = 50;
++ if ((info->flash_id & 0xFF) == 0x1F) /* Atmel */
++ {
++ switch (info->flash_id & 0x001F00)
++ {
++ case 0x000400:
++ info->sector_count = 8;
++ info->size = 0x80000;
++ break;
++ case 0x000500:
++ info->sector_count = 16;
++ info->size = 0x100000;
++ break;
++ case 0x000600:
++ info->sector_count = 32;
++ info->size = 0x200000;
++ break;
++ case 0x000700:
++ info->sector_count = 64;
++ info->size = 0x400000;
++ break;
++ case 0x000800:
++ info->sector_count = 128;
++ info->size = 0x800000;
++ break;
++ case 0x000900:
++ info->sector_count = 256;
++ info->size = 0x1000000;
++ break;
++ default:
++ printf("Can't support this SPI Flash!! \n");
++ return 0;
++ }
++ } /* Atmel JDEC */
++ else /* JDEC */
++ {
++ switch (info->flash_id & 0xFF0000)
++ {
++ case 0x120000:
++ info->sector_count = 4;
++ info->size = 0x40000;
++ break;
++ case 0x130000:
++ info->sector_count = 8;
++ info->size = 0x80000;
++ break;
++ case 0x140000:
++ info->sector_count =16;
++ info->size = 0x100000;
++ break;
++ case 0x150000:
++ info->sector_count =32;
++ info->size = 0x200000;
++ break;
++ case 0x160000:
++ info->sector_count =64;
++ info->size = 0x400000;
++ break;
++ case 0x170000:
++ info->sector_count =128;
++ info->size = 0x800000;
++ break;
++ case 0x180000:
++ info->sector_count =256;
++ info->size = 0x1000000;
++ break;
++ case 0x190000:
++ info->sector_count =256;
++ info->size = 0x1000000;
++#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
++ info->sector_count = 512;
++ info->size = 0x2000000;
++ info->address32 = 1;
++#if defined(CONFIG_FLASH_SPIx2_Dummy)
++ info->readcmd = 0xbb;
++ info->dummybyte = 1;
++ info->dualport = 1;
++ info->iomode = IOMODEx2_dummy;
++#elif defined(CONFIG_FLASH_SPIx4_Dummy)
++ info->readcmd = 0xeb;
++ info->dummybyte = 3;
++ info->dualport = 0;
++ info->iomode = IOMODEx4_dummy;
++ info->quadport = 1;
++ info->dummydata = 0xaa;
++#endif
++#endif
++ break;
++
++ case 0x200000:
++ info->sector_count =256;
++ info->size = 0x1000000;
++ if ((info->flash_id & 0xFF) == 0x20) /* numonyx */
++ info->specificspi = SpecificSPI_N25Q512;
++#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
++ info->sector_count = 1024;
++ info->size = 0x4000000;
++ info->address32 = 1;
++#if defined(CONFIG_FLASH_SPIx2_Dummy)
++ info->readcmd = 0xbb;
++ info->dummybyte = 1;
++ info->dualport = 1;
++ info->iomode = IOMODEx2_dummy;
++#elif defined(CONFIG_FLASH_SPIx4_Dummy)
++ info->readcmd = 0xeb;
++ info->dummybyte = 3;
++ info->dualport = 0;
++ info->iomode = IOMODEx4_dummy;
++ info->quadport = 1;
++ info->dummydata = 0xaa;
++#endif
++#endif
++ break;
++
++ default:
++ printf("Can't support this SPI Flash!! \n");
++ return 0;
++ }
++ } /* JDEC */
++ }
++
++ debug ("erase_region_count = %d erase_region_size = %d\n",
++ erase_region_count, erase_region_size);
++
++ sector = base;
++ for (j = 0; j < info->sector_count; j++) {
++
++ info->start[j] = sector;
++ sector += erase_region_size;
++ info->protect[j] = 0; /* default: not protected */
++ }
++
++ /* set SPI flash extended info */
++#if defined(CONFIG_AST1300)
++ if (info->size > 0x200000) /* limit MAX Flash to 2MB for AST1300 */
++ info->size = 0x200000;
++#endif
++#if defined(CONFIG_AST2400) || defined(CONFIG_AST2300) || defined(CONFIG_AST2300_FPGA_1) || defined(CONFIG_AST2300_FPGA_2) || defined(CONFIG_AST1300)
++ reg = *((volatile ulong*) 0x1e6e2024);
++ if (reg & 0x40000)
++ {
++ reg = *((volatile ulong*) 0x1e6e2070);
++
++ ulRefPLL = 24;
++ ulDeNumerator = reg & 0x0F;
++ ulNumerator = (reg & 0x07E0) >> 5;
++ ulOD = (reg & 0x10) ? 1:2;
++
++ cpuclk = ulRefPLL * ulOD * (ulNumerator + 2) / (ulDeNumerator + 1);
++ }
++ else
++ {
++ reg = *((volatile ulong*) 0x1e6e2070);
++#if defined(CONFIG_AST2400)
++ if (reg & 0x00800000) //ref. clk:25MHz
++ {
++ switch (reg & 0x300)
++ {
++ case 0x000:
++ cpuclk = 400;
++ break;
++ case 0x100:
++ cpuclk = 375;
++ break;
++ case 0x200:
++ cpuclk = 350;
++ break;
++ case 0x300:
++ cpuclk = 325;
++ break;
++ }
++ }
++ else
++ {
++ switch (reg & 0x300) //ref. clk:24MHz
++ {
++ case 0x000:
++ cpuclk = 384;
++ break;
++ case 0x100:
++ cpuclk = 360;
++ break;
++ case 0x200:
++ cpuclk = 336;
++ break;
++ case 0x300:
++ cpuclk = 312;
++ break;
++ }
++ }
++#else
++ switch (reg & 0x300)
++ {
++ case 0x000:
++ cpuclk = 384;
++ break;
++ case 0x100:
++ cpuclk = 360;
++ break;
++ case 0x200:
++ cpuclk = 336;
++ break;
++ case 0x300:
++ cpuclk = 408;
++ break;
++ }
++#endif
++ }
++
++ reg = *((volatile ulong*) 0x1e6e2070);
++ switch (reg & 0xc00)
++ {
++ case 0x000:
++ cpuclk /= 1;
++ break;
++ case 0x400:
++ cpuclk /= 2;
++ break;
++ case 0x800:
++ cpuclk /= 4;
++ break;
++ case 0xC00:
++ cpuclk /= 3;
++ break;
++ }
++#else /* AST2100 */
++ reg = *((volatile ulong*) 0x1e6e2070);
++ switch (reg & 0xe00)
++ {
++ case 0x000:
++ cpuclk = 266;
++ break;
++ case 0x200:
++ cpuclk = 233;
++ break;
++ case 0x400:
++ cpuclk = 200;
++ break;
++ case 0x600:
++ cpuclk = 166;
++ break;
++ case 0x800:
++ cpuclk = 133;
++ break;
++ case 0xA00:
++ cpuclk = 100;
++ break;
++ case 0xC00:
++ cpuclk = 300;
++ break;
++ case 0xE00:
++ cpuclk = 24;
++ break;
++ }
++ switch (reg & 0x3000)
++ {
++ case 0x1000:
++ cpuclk /= 2;
++ break;
++ case 0x2000:
++ cpuclk /= 4;
++ break;
++ case 0x3000:
++ cpuclk /= 3;
++ break;
++ }
++#endif
++
++#if defined(CONFIG_AST2400) || defined(CONFIG_AST2300) || defined(CONFIG_AST2300_FPGA_1) || defined(CONFIG_AST2300_FPGA_2) || defined(CONFIG_AST1300)
++
++#if defined(CONFIG_AST2300) || defined(CONFIG_AST1300)
++ /* limit Max SPI CLK to 50MHz (Datasheet v1.2) */
++ if (WriteClk > 50) WriteClk = 50;
++ if (EraseClk > 50) EraseClk = 50;
++ if (ReadClk > 50) ReadClk = 50;
++#endif
++
++ div = 1;
++ while ( ((cpuclk/div) > WriteClk) && (div < 16) )
++ {
++ div++;
++ }
++ info->tCK_Write = AST2300_SPICLK_DIV[div-1];
++
++ div = 1;
++ while ( ((cpuclk/div) > EraseClk) && (div < 16) )
++ {
++ div++;
++ }
++ info->tCK_Erase = AST2300_SPICLK_DIV[div-1];
++
++ div = 1;
++ while ( ((cpuclk/div) > ReadClk) && (div < 16) )
++ {
++ div++;
++ }
++ info->tCK_Read = AST2300_SPICLK_DIV[div-1];
++#else
++ div = 2;
++ info->tCK_Write = 7;
++ while ( (cpuclk/div) > WriteClk )
++ {
++ info->tCK_Write--;
++ div +=2;
++ }
++ div = 2;
++ info->tCK_Erase = 7;
++ while ( (cpuclk/div) > EraseClk )
++ {
++ info->tCK_Erase--;
++ div +=2;
++ }
++ div = 2;
++ info->tCK_Read = 7;
++ while ( (cpuclk/div) > ReadClk )
++ {
++ info->tCK_Read--;
++ div +=2;
++ }
++#endif
++
++ /* unprotect flash */
++ write_status_register(info, 0);
++
++ if (info->quadport)
++ write_status_register(info, 0x40); /* enable QE */
++
++ if (info->address32)
++ {
++ reg = *((volatile ulong*) 0x1e6e2070); /* set H/W Trappings */
++ reg |= 0x10;
++ *((volatile ulong*) 0x1e6e2070) = reg;
++
++ reg = *((volatile ulong*) 0x1e620004); /* enable 32b control bit*/
++ reg |= (0x01 << info->CE);
++ *((volatile ulong*) 0x1e620004) = reg;
++
++ /* set flash chips to 32bits addressing mode */
++ if ((info->flash_id & 0xFF) == 0x01) /* Spansion */
++ enable4b_spansion(info);
++ else if ((info->flash_id & 0xFF) == 0x20) /* Numonyx */
++ enable4b_numonyx(info);
++ else /* MXIC, Winbond */
++ enable4b(info);
++
++ }
++
++ reset_flash(info);
++
++ return (info->size);
++}
++
++
++/*-----------------------------------------------------------------------
++ */
++static int flash_write_buffer (flash_info_t *info, uchar *src, ulong addr, int len)
++{
++ ulong j, base, offset;
++ ulong ulSMMBase, ulCtrlData, CtrlOffset;
++ uchar jReg;
++
++ if (info->CE == 2)
++ {
++ CtrlOffset = SPICtrlRegOffset2;
++ }
++ else
++ {
++ CtrlOffset = SPICtrlRegOffset;
++ }
++
++ base = info->start[0];
++ offset = addr - base;
++ base = flash_make_addr (info, 0, 0);
++
++ enable_write (info);
++
++ ulCtrlData = (info->tCK_Write << 8);
++
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0x02);
++ udelay(10);
++ if (info->address32)
++ {
++ *(uchar *) (base) = (uchar) ((offset & 0xff000000) >> 24);
++ udelay(10);
++ }
++ *(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16);
++ udelay(10);
++ *(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8);
++ udelay(10);
++ *(uchar *) (base) = (uchar) ((offset & 0x0000ff));
++ udelay(10);
++
++ for (j=0; j<len; j++)
++ {
++ *(uchar *) (base) = *(uchar *) (src++);
++ udelay(10);
++ }
++
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0x05);
++ udelay(10);
++ do {
++ jReg = *(volatile uchar *) (base);
++ } while ((jReg & 0x01));
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++
++ /* RFSR */
++ if (info->specificspi == SpecificSPI_N25Q512)
++ {
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0x70);
++ udelay(10);
++ do {
++ jReg = *(volatile uchar *) (base);
++ } while (!(jReg & 0x80));
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ }
++}
++
++/*-----------------------------------------------------------------------
++ *
++ * export functions
++ *
++ */
++
++/*-----------------------------------------------------------------------
++ *
++ */
++unsigned long flash_init (void)
++{
++ unsigned long size = 0;
++ int i;
++
++ /* Init: no FLASHes known */
++ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
++ flash_info[i].flash_id = FLASH_UNKNOWN;
++ size += flash_info[i].size = flash_get_size (bank_base[i], i);
++ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
++#ifndef CFG_FLASH_QUIET_TEST
++ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
++ i, flash_info[i].size, flash_info[i].size << 20);
++#endif /* CFG_FLASH_QUIET_TEST */
++ }
++ }
++
++ /* Monitor protection ON by default */
++#if (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
++ flash_protect (FLAG_PROTECT_SET,
++ CONFIG_MONITOR_BASE,
++ CONFIG_MONITOR_BASE + monitor_flash_len - 1,
++ flash_get_info(CONFIG_MONITOR_BASE));
++#endif
++
++ /* Environment protection ON by default */
++#ifdef CONFIG_ENV_IS_IN_FLASH
++ flash_protect (FLAG_PROTECT_SET,
++ CONFIG_ENV_ADDR,
++ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
++ flash_get_info(CONFIG_ENV_ADDR));
++#endif
++
++ /* Redundant environment protection ON by default */
++#ifdef CONFIG_ENV_ADDR_REDUND
++ flash_protect (FLAG_PROTECT_SET,
++ CONFIG_ENV_ADDR_REDUND,
++ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
++ flash_get_info(CONFIG_ENV_ADDR_REDUND));
++#endif
++ return (size);
++}
++
++/*-----------------------------------------------------------------------
++ */
++#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
++static flash_info_t *flash_get_info(ulong base)
++{
++ int i;
++ flash_info_t * info = 0;
++
++ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
++ info = & flash_info[i];
++ if (info->size && info->start[0] <= base &&
++ base <= info->start[0] + info->size - 1)
++ break;
++ }
++
++ return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
++}
++#endif
++
++/*-----------------------------------------------------------------------
++ */
++int flash_erase (flash_info_t * info, int s_first, int s_last)
++{
++ int rcode = 0;
++ int prot;
++ flash_sect_t sect;
++
++ ulong base, offset;
++ ulong ulSMMBase, ulCtrlData, CtrlOffset;
++ uchar jReg;
++
++ disable_cache();
++
++ if (info->CE == 2)
++ {
++ CtrlOffset = SPICtrlRegOffset2;
++ }
++ else
++ {
++ CtrlOffset = SPICtrlRegOffset;
++ }
++
++ if ((s_first < 0) || (s_first > s_last)) {
++ puts ("- no sectors to erase\n");
++ return 1;
++ }
++
++ prot = 0;
++ for (sect = s_first; sect <= s_last; ++sect) {
++ if (info->protect[sect]) {
++ prot++;
++ }
++ }
++ if (prot) {
++ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
++ } else {
++ putc ('\n');
++ }
++
++ ulCtrlData = (info->tCK_Erase << 8);
++ for (sect = s_first; sect <= s_last; sect++) {
++ if (info->protect[sect] == 0) { /* not protected */
++ /* start erasing */
++ enable_write(info);
++
++ base = info->start[0];
++ offset = info->start[sect] - base;
++ base = flash_make_addr (info, 0, 0);
++
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0xd8);
++ udelay(10);
++ if (info->address32)
++ {
++ *(uchar *) (base) = (uchar) ((offset & 0xff000000) >> 24);
++ udelay(10);
++ }
++ *(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16);
++ udelay(10);
++ *(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8);
++ udelay(10);
++ *(uchar *) (base) = (uchar) ((offset & 0x0000ff));
++ udelay(10);
++
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0x05);
++ udelay(10);
++ do {
++ jReg = *(volatile uchar *) (base);
++ } while ((jReg & 0x01));
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++
++ /* RFSR */
++ if (info->specificspi == SpecificSPI_N25Q512)
++ {
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_LOW | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ *(uchar *) (base) = (uchar) (0x70);
++ udelay(10);
++ do {
++ jReg = *(volatile uchar *) (base);
++ } while (!(jReg & 0x80));
++ ulCtrlData &= CMD_MASK;
++ ulCtrlData |= CE_HIGH | USERMODE;
++ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
++ udelay(200);
++ }
++
++ putc ('.');
++ }
++ }
++ puts (" done\n");
++
++ reset_flash(info);
++
++ return rcode;
++}
++
++/*-----------------------------------------------------------------------
++ */
++void flash_print_info (flash_info_t * info)
++{
++ putc ('\n');
++ return;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
++{
++ int count;
++ unsigned char pat[] = {'|', '-', '/', '\\'};
++ int patcnt;
++
++ disable_cache();
++
++ /* get lower aligned address */
++ if (addr & (info->buffersize - 1))
++ {
++ count = cnt >= info->buffersize ? (info->buffersize - (addr & 0xff)):cnt;
++ flash_write_buffer (info, src, addr, count);
++ addr+= count;
++ src += count;
++ cnt -= count;
++ }
++
++ /* prog */
++ while (cnt > 0) {
++ count = cnt >= info->buffersize ? info->buffersize:cnt;
++ flash_write_buffer (info, src, addr, count);
++ addr+= count;
++ src += count;
++ cnt -= count;
++ printf("%c\b", pat[(patcnt++) & 0x03]);
++ }
++
++ reset_flash(info);
++
++ return (0);
++}
++
++#ifdef CONFIG_FLASH_AST2300_DMA
++void * memmove_dma(void * dest,const void *src,size_t count)
++{
++ ulong count_align, poll_time, data;
++
++ count_align = (count + 3) & 0xFFFFFFFC; /* 4-bytes align */
++ poll_time = 100; /* set 100 us as default */
++
++ /* force end of burst read */
++ *(volatile ulong *) (STCBaseAddress + SPICtrlRegOffset) |= CE_HIGH;
++ *(volatile ulong *) (STCBaseAddress + SPICtrlRegOffset) &= ~CE_HIGH;
++
++ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (~FLASH_DMA_ENABLE);
++ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_FLASH_BASE) = (ulong *) (src);
++ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_DRAM_BASE) = (ulong *) (dest);
++ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_LENGTH) = (ulong) (count_align);
++ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (FLASH_DMA_ENABLE);
++
++ /* wait poll */
++ do {
++ udelay(poll_time);
++ data = *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS);
++ } while (!(data & FLASH_STATUS_DMA_READY));
++
++ /* clear status */
++ *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS) |= FLASH_STATUS_DMA_CLEAR;
++}
++#endif
++#endif /* CONFIG_FLASH_SPI */
+diff --git a/board/aspeed/ast2300/hactest.c b/board/aspeed/ast2300/hactest.c
+new file mode 100755
+index 0000000..bfa87d5
+--- /dev/null
++++ b/board/aspeed/ast2300/hactest.c
+@@ -0,0 +1,762 @@
++/*
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/*
++ * Diagnostics support
++ */
++#include <common.h>
++#include <command.h>
++#include <post.h>
++#include "slt.h"
++
++#if ((CFG_CMD_SLT & CFG_CMD_HACTEST) && defined(CONFIG_SLT))
++#include "hactest.h"
++
++#include "aes.c"
++#include "rc4.c"
++
++static unsigned char crypto_src[CRYPTO_MAX_SRC], crypto_dst[CRYPTO_MAX_DST], crypto_context[CRYPTO_MAX_CONTEXT];
++static unsigned char hash_src[HASH_MAX_SRC], hash_dst[HASH_MAX_DST], hmac_key[HMAC_MAX_KEY];
++
++/*
++ * table
++ */
++static aes_test aestest[] = {
++ { CRYPTOMODE_ECB, 128,
++ {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c, '\0'},
++ {0x32, 0x43, 0xf6, 0xa8, 0x88, 0x5a, 0x30, 0x8d, 0x31, 0x31, 0x98, 0xa2, 0xe0, 0x37, 0x07, 0x34, '\0'},
++ {0x39, 0x25, 0x84, 0x1d, 0x02, 0xdc, 0x09, 0xfb, 0xdc, 0x11, 0x85, 0x97, 0x19, 0x6a, 0x0b, 0x32, '\0'} },
++ {0xFF, 0xFF, "", "", ""}, /* End Mark */
++};
++
++static rc4_test rc4test[] = {
++ {{0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, '\0'},
++ {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, '\0'}},
++ {{0xff}, {0xff}}, /* End Mark */
++};
++
++static hash_test hashtest[] = {
++ {HASHMODE_SHA1, 20,
++ "abc",
++ {0x53, 0x20, 0xb0, 0x8c, 0xa1, 0xf5, 0x74, 0x62, 0x50, 0x71, 0x89, 0x41, 0xc5, 0x0a, 0xdf, 0x4e, 0xbb, 0x55, 0x76, 0x06, '\0'}},
++ {0xFF, 0xFF, "", ""}, /* End Mark */
++};
++
++static hmac_test hmactest[] = {
++ {HASHMODE_SHA1, 64, 20,
++ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16,0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, '\0' },
++ "Sample #1",
++ {0xbf, 0x39, 0xda, 0xb1, 0x7d, 0xc2, 0xe1, 0x23, 0x0d, 0x28, 0x35, 0x3b, 0x8c, 0xcb, 0x14, 0xb6, 0x22, 0x02, 0x65, 0xb3, '\0'}},
++ {0xFF, 0xFF, 0xFF, "", "", ""}, /* End Mark */
++};
++
++void EnableHMAC(void)
++{
++ unsigned long ulData;
++
++ /* init SCU */
++ *(unsigned long *) (0x1e6e2000) = 0x1688a8a8;
++
++ ulData = *(volatile unsigned long *) (0x1e6e200c);
++ ulData &= 0xfdfff;
++ *(unsigned long *) (0x1e6e200c) = ulData;
++ udelay(100);
++ ulData = *(volatile unsigned long *) (0x1e6e2004);
++ ulData &= 0xfffef;
++ *(unsigned long *) (0x1e6e2004) = ulData;
++
++}
++
++/* AES */
++void aes_enc_ast3000(aes_context *ctx, uint8 *input, uint8 *iv, uint8 *output, uint32 ulMsgLength , uint32 ulAESMode)
++{
++
++ unsigned long i, ulTemp, ulCommand;
++ unsigned char ch;
++ unsigned char *pjsrc, *pjdst, *pjcontext;
++
++ ulCommand = CRYPTO_ENABLE_RW | CRYPTO_ENABLE_CONTEXT_LOAD | CRYPTO_ENABLE_CONTEXT_SAVE | \
++ CRYPTO_AES | CRYPTO_ENCRYPTO | CRYPTO_SYNC_MODE_ASYNC;
++
++ switch (ctx->nr)
++ {
++ case 10:
++ ulCommand |= CRYPTO_AES128;
++ break;
++ case 12:
++ ulCommand |= CRYPTO_AES192;
++ break;
++ case 14:
++ ulCommand |= CRYPTO_AES256;
++ break;
++ }
++
++ switch (ulAESMode)
++ {
++ case CRYPTOMODE_ECB:
++ ulCommand |= CRYPTO_AES_ECB;
++ break;
++ case CRYPTOMODE_CBC:
++ ulCommand |= CRYPTO_AES_CBC;
++ break;
++ case CRYPTOMODE_CFB:
++ ulCommand |= CRYPTO_AES_CFB;
++ break;
++ case CRYPTOMODE_OFB:
++ ulCommand |= CRYPTO_AES_OFB;
++ break;
++ case CRYPTOMODE_CTR:
++ ulCommand |= CRYPTO_AES_CTR;
++ break;
++ }
++
++ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) crypto_src);
++ pjdst = (unsigned char *) m16byteAlignment((unsigned long) crypto_dst);
++ pjcontext = (unsigned char *) m16byteAlignment((unsigned long) crypto_context);
++
++ /* Init HW */
++ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
++ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_DST_BASE_OFFSET) = (unsigned long) pjdst;
++ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CONTEXT_BASE_OFFSET) = (unsigned long) pjcontext;
++ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_LEN_OFFSET) = ulMsgLength;
++
++ /* Set source */
++ for (i=0; i< ulMsgLength; i++)
++ {
++ ch = *(uint8 *)(input + i);
++ *(uint8 *) (pjsrc + i) = ch;
++ }
++
++ /* Set Context */
++ /* Set IV */
++ for (i=0; i<16; i++)
++ {
++ ch = *(uint8 *) (iv + i);
++ *(uint8 *) (pjcontext + i) = ch;
++ }
++
++ /* Set Expansion Key */
++ for (i=0; i<(4*(ctx->nr+1)); i++)
++ {
++ ulTemp = ((ctx->erk[i] & 0xFF) << 24) + ((ctx->erk[i] & 0xFF00) << 8) + ((ctx->erk[i] & 0xFF0000) >> 8) + ((ctx->erk[i] & 0xFF000000) >> 24);
++ *(uint32 *) (pjcontext + i*4 + 16) = ulTemp;
++ }
++
++ /* fire cmd */
++ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CMD_BASE_OFFSET) = ulCommand;
++ do {
++ ulTemp = *(volatile unsigned long *) (HAC_REG_BASE + REG_CRYPTO_STATUS_OFFSET);
++ } while (ulTemp & CRYPTO_BUSY);
++
++ /* Output */
++ for (i=0; i<ulMsgLength; i++)
++ {
++ ch = *(uint8 *) (pjdst + i);
++ *(uint8 *) (output + i) = ch;
++ }
++
++} /* aes_enc_ast3000 */
++
++
++void aes_dec_ast3000(aes_context *ctx, uint8 *input, uint8 *iv, uint8 *output, uint32 ulMsgLength , uint32 ulAESMode)
++{
++ unsigned long i, ulTemp, ulCommand;
++ unsigned char ch;
++ unsigned char *pjsrc, *pjdst, *pjcontext;
++
++ ulCommand = CRYPTO_ENABLE_RW | CRYPTO_ENABLE_CONTEXT_LOAD | CRYPTO_ENABLE_CONTEXT_SAVE | \
++ CRYPTO_AES | CRYPTO_DECRYPTO | CRYPTO_SYNC_MODE_ASYNC;
++
++ switch (ctx->nr)
++ {
++ case 10:
++ ulCommand |= CRYPTO_AES128;
++ break;
++ case 12:
++ ulCommand |= CRYPTO_AES192;
++ break;
++ case 14:
++ ulCommand |= CRYPTO_AES256;
++ break;
++ }
++
++ switch (ulAESMode)
++ {
++ case CRYPTOMODE_ECB:
++ ulCommand |= CRYPTO_AES_ECB;
++ break;
++ case CRYPTOMODE_CBC:
++ ulCommand |= CRYPTO_AES_CBC;
++ break;
++ case CRYPTOMODE_CFB:
++ ulCommand |= CRYPTO_AES_CFB;
++ break;
++ case CRYPTOMODE_OFB:
++ ulCommand |= CRYPTO_AES_OFB;
++ break;
++ case CRYPTOMODE_CTR:
++ ulCommand |= CRYPTO_AES_CTR;
++ break;
++ }
++
++ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) crypto_src);
++ pjdst = (unsigned char *) m16byteAlignment((unsigned long) crypto_dst);
++ pjcontext = (unsigned char *) m16byteAlignment((unsigned long) crypto_context);
++
++ /* Init HW */
++ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
++ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_DST_BASE_OFFSET) = (unsigned long) pjdst;
++ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CONTEXT_BASE_OFFSET) = (unsigned long) pjcontext;
++ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_LEN_OFFSET) = ulMsgLength;
++
++ /* Set source */
++ for (i=0; i< ulMsgLength; i++)
++ {
++ ch = *(uint8 *)(input + i);
++ *(uint8 *) (pjsrc + i) = ch;
++ }
++
++ /* Set Context */
++ /* Set IV */
++ for (i=0; i<16; i++)
++ {
++ ch = *(uint8 *) (iv + i);
++ *(uint8 *) (pjcontext + i) = ch;
++ }
++
++ /* Set Expansion Key */
++ for (i=0; i<(4*(ctx->nr+1)); i++)
++ {
++ ulTemp = ((ctx->erk[i] & 0xFF) << 24) + ((ctx->erk[i] & 0xFF00) << 8) + ((ctx->erk[i] & 0xFF0000) >> 8) + ((ctx->erk[i] & 0xFF000000) >> 24);
++ *(uint32 *) (pjcontext + i*4 + 16) = ulTemp;
++ }
++
++ /* fire cmd */
++ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CMD_BASE_OFFSET) = ulCommand;
++ do {
++ ulTemp = *(volatile unsigned long *) (HAC_REG_BASE + REG_CRYPTO_STATUS_OFFSET);
++ } while (ulTemp & CRYPTO_BUSY);
++
++ /* Output */
++ for (i=0; i<ulMsgLength; i++)
++ {
++ ch = *(uint8 *) (pjdst + i);
++ *(uint8 *) (output + i) = ch;
++ }
++
++} /* aes_dec_ast3000 */
++
++void rc4_crypt_ast3000(uint8 *data, int ulMsgLength, uint8 *rc4_key, uint32 ulKeyLength)
++{
++ struct rc4_state s;
++ unsigned long i, ulTemp, ulCommand;
++ unsigned char ch;
++ unsigned char *pjsrc, *pjdst, *pjcontext;
++
++ ulCommand = CRYPTO_ENABLE_RW | CRYPTO_ENABLE_CONTEXT_LOAD | CRYPTO_ENABLE_CONTEXT_SAVE | \
++ CRYPTO_RC4 | CRYPTO_SYNC_MODE_ASYNC;
++
++ rc4_setup( &s, rc4_key, ulKeyLength );
++
++ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) crypto_src);
++ pjdst = (unsigned char *) m16byteAlignment((unsigned long) crypto_dst);
++ pjcontext = (unsigned char *) m16byteAlignment((unsigned long) crypto_context);
++
++ /* Init HW */
++ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
++ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_DST_BASE_OFFSET) = (unsigned long) pjdst;
++ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_CONTEXT_BASE_OFFSET) = (unsigned long) pjcontext;
++ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_LEN_OFFSET) = ulMsgLength;
++
++
++ /* Set source */
++ for (i=0; i< ulMsgLength; i++)
++ {
++ ch = *(uint8 *)(data + i);
++ *(uint8 *) (pjsrc + i) = ch;
++ }
++
++ /* Set Context */
++ /* Set i, j */
++ *(uint32 *) (pjcontext + 8) = 0x0001;
++
++ /* Set Expansion Key */
++ for (i=0; i<(256/4); i++)
++ {
++ ulTemp = (s.m[i * 4] & 0xFF) + ((s.m[i * 4 + 1] & 0xFF) << 8) + ((s.m[i * 4 + 2] & 0xFF) << 16) + ((s.m[i * 4+ 3] & 0xFF) << 24);
++ *(uint32 *) (pjcontext + i*4 + 16) = ulTemp;
++ }
++
++ /* fire cmd */
++ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_CMD_BASE_OFFSET) = ulCommand;
++ do {
++ ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_CRYPTO_STATUS_OFFSET);
++ } while (ulTemp & CRYPTO_BUSY);
++
++ /* Output */
++ for (i=0; i<ulMsgLength; i++)
++ {
++ ch = *(volatile uint8 *) (pjdst + i);
++ *(uint8 *) (data + i) = ch;
++ }
++
++} /* rc4_crypt_ast3000 */
++
++/* Hash */
++void hash_ast3000(uint8 *msg, uint32 ulLength, unsigned char *output, uint32 ulHashMode)
++{
++ uint32 i, ulTemp, ulCommand, ulDigestLength, ulMyMsgLength;
++ uint8 ch;
++ unsigned char *pjsrc, *pjdst;
++
++ /* Get Info */
++ switch (ulHashMode)
++ {
++ case HASHMODE_MD5:
++ ulCommand = HASH_ALG_SELECT_MD5;
++ ulDigestLength = 16;
++ break;
++ case HASHMODE_SHA1:
++ ulCommand = HASH_ALG_SELECT_SHA1 | 0x08;
++ ulDigestLength = 20;
++ break;
++ case HASHMODE_SHA256:
++ ulCommand = HASH_ALG_SELECT_SHA256 | 0x08;
++ ulDigestLength = 32;
++ break;
++ case HASHMODE_SHA224:
++ ulCommand = HASH_ALG_SELECT_SHA224 | 0x08;
++ ulDigestLength = 28;
++ break;
++ }
++
++ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) hash_src);
++ pjdst = (unsigned char *) m16byteAlignment((unsigned long) hash_dst);
++
++ /* 16byte alignment */
++ ulMyMsgLength = m16byteAlignment(ulLength);
++
++ /* Init. HW */
++ *(uint32 *) (HAC_REG_BASE + REG_HASH_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
++ *(uint32 *) (HAC_REG_BASE + REG_HASH_DST_BASE_OFFSET) = (unsigned long) pjdst;
++ *(uint32 *) (HAC_REG_BASE + REG_HASH_LEN_OFFSET) = ulMyMsgLength;
++
++ /* write src */
++ for (i=0; i<ulLength; i++)
++ {
++ ch = *(uint8 *)(msg+i);
++ *(uint8 *) (pjsrc + i) = ch;
++ }
++ for (i=ulLength; i<ulMyMsgLength; i++)
++ *(uint8 *) (pjsrc + i) = 0;
++
++ /* fire cmd */
++ *(uint32 *) (HAC_REG_BASE + REG_HASH_CMD_OFFSET) = ulCommand;
++
++ /* get digest */
++ do {
++ ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_HASH_STATUS_OFFSET);
++ } while (ulTemp & HASH_BUSY);
++
++ for (i=0; i<ulDigestLength; i++)
++ {
++ ch = *(volatile uint8 *) (pjdst + i);
++ *(uint8 *) (output + i) = ch;
++ }
++
++} /* hash_ast3000 */
++
++/* HMAC */
++void hmackey_ast3000(uint8 *key, uint32 ulKeyLength, uint32 ulHashMode)
++{
++ uint32 i, ulBlkLength, ulDigestLength, ulTemp, ulCommand;
++ uint8 k0[64], sum[32];
++ uint8 ch;
++ unsigned char *pjsrc, *pjdst, *pjkey;
++
++ /* Get Info */
++ switch (ulHashMode)
++ {
++ case HASHMODE_MD5:
++ ulCommand = HASH_ALG_SELECT_MD5;
++ ulDigestLength = 16;
++ break;
++ case HASHMODE_SHA1:
++ ulCommand = HASH_ALG_SELECT_SHA1 | 0x08;
++ ulDigestLength = 20;
++ break;
++ case HASHMODE_SHA256:
++ ulCommand = HASH_ALG_SELECT_SHA256 | 0x08;
++ ulDigestLength = 32;
++ break;
++ case HASHMODE_SHA224:
++ ulCommand = HASH_ALG_SELECT_SHA224 | 0x08;
++ ulDigestLength = 28;
++ break;
++ }
++ ulBlkLength = 64; /* MD5, SHA1/256/224: 64bytes */
++
++ /* Init */
++ memset( (void *) k0, 0, 64); /* reset to zero */
++ memset( (void *) sum, 0, 32); /* reset to zero */
++
++ /* Get k0 */
++ if (ulKeyLength <= ulBlkLength)
++ memcpy( (void *) k0, (void *) key, ulKeyLength );
++ else /* (ulKeyLength > ulBlkLength) */
++ {
++ hash_ast3000(key, ulKeyLength, sum, ulHashMode);
++ memcpy( (void *) k0, (void *) sum, ulDigestLength );
++ }
++
++ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) hash_src);
++ pjdst = (unsigned char *) m16byteAlignment((unsigned long) hash_dst);
++ pjkey = (unsigned char *) m64byteAlignment((unsigned long) hmac_key);
++
++ /* Calculate digest */
++ *(uint32 *) (HAC_REG_BASE + REG_HASH_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
++ *(uint32 *) (HAC_REG_BASE + REG_HASH_DST_BASE_OFFSET) = (unsigned long) pjdst;
++ *(uint32 *) (HAC_REG_BASE + REG_HASH_KEY_BASE_OFFSET) = (unsigned long) pjkey;
++ *(uint32 *) (HAC_REG_BASE + REG_HASH_LEN_OFFSET) = ulBlkLength;
++
++ /* write key to src */
++ for (i=0; i<ulBlkLength; i++)
++ {
++ ch = *(uint8 *)(k0+i);
++ *(uint8 *) (pjsrc + i) = ch;
++ }
++
++ /* fire cmd for calculate */
++ *(uint32 *) (HAC_REG_BASE + REG_HASH_CMD_OFFSET) = ulCommand