From 0223e595f4033e91e93403a7317bcc9e47676b8f Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Wed, 23 Aug 2017 15:54:21 -0500 Subject: Initial import of modified u-boot tree Original upstream URL: git://git.denx.de/u-boot.git Original upstream GIT hash: 62c175fbb8a0f9a926c88294ea9f7e88eb898f6c --- board/pm826/Makefile | 44 ++++++ board/pm826/flash.c | 386 +++++++++++++++++++++++++++++++++++++++++++++++++++ board/pm826/pm826.c | 335 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 765 insertions(+) create mode 100644 board/pm826/Makefile create mode 100644 board/pm826/flash.c create mode 100644 board/pm826/pm826.c (limited to 'board/pm826') diff --git a/board/pm826/Makefile b/board/pm826/Makefile new file mode 100644 index 0000000..12e4aa6 --- /dev/null +++ b/board/pm826/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS = $(BOARD).o flash.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/pm826/flash.c b/board/pm826/flash.c new file mode 100644 index 0000000..010f59a --- /dev/null +++ b/board/pm826/flash.c @@ -0,0 +1,386 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for Intel devices + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------- + */ +ulong flash_get_size (volatile unsigned long *baseaddr, + flash_info_t * info) +{ + short i; + unsigned long flashtest_h, flashtest_l; + + info->sector_count = info->size = 0; + info->flash_id = FLASH_UNKNOWN; + + /* Write query command sequence and test FLASH answer + */ + baseaddr[0] = 0x00980098; + baseaddr[1] = 0x00980098; + + flashtest_h = baseaddr[0]; /* manufacturer ID */ + flashtest_l = baseaddr[1]; + + if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) + return (0); /* no or unknown flash */ + + flashtest_h = baseaddr[2]; /* device ID */ + flashtest_l = baseaddr[3]; + + if (flashtest_h != flashtest_l) + return (0); + + switch (flashtest_h) { + case INTEL_ID_28F160C3B: + info->flash_id = FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ + break; + case INTEL_ID_28F160F3B: + info->flash_id = FLASH_28F160F3B; + info->sector_count = 39; + info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ + break; + case INTEL_ID_28F640C3B: + info->flash_id = FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x02000000; /* 16 * 2 MB = 32 MB */ + break; + default: + return (0); /* no or unknown flash */ + } + + info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ + + if (info->flash_id & FLASH_BTYPE) { + volatile unsigned long *tmp = baseaddr; + + /* set up sector start adress table (bottom sector type) + * AND unlock the sectors (if our chip is 160C3 or 640C3) + */ + for (i = 0; i < info->sector_count; i++) { + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) { + tmp[0] = 0x00600060; + tmp[1] = 0x00600060; + tmp[0] = 0x00D000D0; + tmp[1] = 0x00D000D0; + } + info->start[i] = (uint) tmp; + tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ + } + } + + memset (info->protect, 0, info->sector_count); + + baseaddr[0] = 0x00FF00FF; + baseaddr[1] = 0x00FF00FF; + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size_b0 = 0; + int i; + + /* Init: no FLASHes known + */ + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here (only one bank) */ + + size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]); + if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 >> 20); + } + + /* protect monitor and environment sectors + */ + +#ifndef CONFIG_BOOT_ROM + /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE + * but we shouldn't protect it. + */ + +# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE + flash_protect (FLAG_PROTECT_SET, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] + ); +# endif +#endif /* CONFIG_BOOT_ROM */ + +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +# endif + flash_protect (FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); +#endif + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch ((info->flash_id >> 16) & 0xff) { + case 0x89: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + printf ("28F160C3B (16 M, bottom sector)\n"); + break; + case FLASH_28F160F3B: + printf ("28F160F3B (16 M, bottom sector)\n"); + break; + case FLASH_28F640C3B: + printf ("28F640C3B (64 M, bottom sector)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) + prot++; + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* Start erase on unprotected sectors + */ + for (sect = s_first; sect <= s_last; sect++) { + volatile ulong *addr = + (volatile unsigned long *) info->start[sect]; + + start = get_timer (0); + last = start; + if (info->protect[sect] == 0) { + /* Disable interrupts which might cause a timeout here + */ + flag = disable_interrupts (); + + /* Erase the block + */ + addr[0] = 0x00200020; + addr[1] = 0x00200020; + addr[0] = 0x00D000D0; + addr[1] = 0x00D000D0; + + /* re-enable interrupts if necessary + */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms + */ + udelay (1000); + + last = start; + while ((addr[0] & 0x00800080) != 0x00800080 || + (addr[1] & 0x00800080) != 0x00800080) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { + printf ("Timeout (erase suspended!)\n"); + /* Suspend erase + */ + addr[0] = 0x00B000B0; + addr[1] = 0x00B000B0; + goto DONE; + } + /* show that we're waiting + */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { + printf ("*** ERROR: erase failed!\n"); + goto DONE; + } + } + /* Clear status register and reset to read mode + */ + addr[0] = 0x00500050; + addr[1] = 0x00500050; + addr[0] = 0x00FF00FF; + addr[1] = 0x00FF00FF; + } + + printf (" done\n"); + +DONE: + return 0; +} + +static int write_word (flash_info_t *, volatile unsigned long *, ulong); + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong v; + int i, l, cc = cnt, res = 0; + + + for (v=0; cc > 0; addr += 4, cc -= 4 - l) { + l = (addr & 3); + addr &= ~3; + + for (i = 0; i < 4; i++) { + v = (v << 8) + (i < l || i - l >= cc ? + *((unsigned char *) addr + i) : *src++); + } + + if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) + break; + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, volatile unsigned long *addr, + ulong data) +{ + int flag, res = 0; + ulong start; + + /* Check if Flash is (sufficiently) erased + */ + if ((*addr & data) != data) + return (2); + + /* Disable interrupts which might cause a timeout here + */ + flag = disable_interrupts (); + + *addr = 0x00400040; + *addr = data; + + /* re-enable interrupts if necessary + */ + if (flag) + enable_interrupts (); + + start = get_timer (0); + while ((*addr & 0x00800080) != 0x00800080) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { + /* Suspend program + */ + *addr = 0x00B000B0; + res = 1; + goto OUT; + } + } + + if (*addr & 0x00220022) { + printf ("*** ERROR: program failed!\n"); + res = 1; + } + +OUT: + /* Clear status register and reset to read mode + */ + *addr = 0x00500050; + *addr = 0x00FF00FF; + + return (res); +} diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c new file mode 100644 index 0000000..19e7a00 --- /dev/null +++ b/board/pm826/pm826.c @@ -0,0 +1,335 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ + /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ + /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */ +#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) +#ifdef CONFIG_ETHER_ON_FCC2 +#error "SCC1 conflicts with FCC2" +#endif + /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ +#else + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */ +#endif + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ + /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */ + /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ + /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */ + /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ + /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */ + /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */ + /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */ + /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */ + /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + puts ("Board: PM826\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or2; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + + *orx_ptr = orx | ~(size - 1); + + return (size); +} + + +phys_size_t initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CONFIG_SYS_RAMBOOT + ulong size8, size9; +#endif + ulong psize = 32 * 1024 * 1024; + + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; + +#ifndef CONFIG_SYS_RAMBOOT + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL) "); + } else { + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + printf ("(60x:8COL) "); + } +#endif + return (psize); +} + +#if defined(CONFIG_CMD_DOC) +void doc_init (void) +{ + doc_probe (CONFIG_SYS_DOC_BASE); +} +#endif + +#ifdef CONFIG_PCI +struct pci_controller hose; + +extern void pci_mpc8250_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc8250_init(&hose); +} +#endif + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} -- cgit v1.1