From d54ef6e789712b41cb4190021448f4fcaa729c56 Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Sat, 15 Nov 2008 13:55:43 +0000 Subject: The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs The AT45 series SPI chips are DataFlash EEPROMs which means they have odd (non-power-of-two) sector sizes, but some of the DataFlash chips can be configured or ordered with power-of-two sector sizes. Add probe support for the following Atmel SPI chips: AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 AT45CS1282 AT45DB011D AT45DB021D AT45DB041D AT45DB081D AT45DB161D AT45DB321C AT45DB321D AT45DB642D Add an explanation why the following chips can't be probed: AT45BR3214B AT45D011 AT45D021A AT45D041A AT45D081A AT45D161 AT45DB011 AT45DB011B AT45DB021A AT45DB021B AT45DB041A AT45DB081A AT45DB161 AT45DB161B AT45DB321 AT45DB321B AT45DB642 Add the ID, but no probing function for this chip: AT25F512A Corresponding to flashrom svn r342 and coreboot v2 svn r3754. Signed-off-by: Carl-Daniel Hailfinger Tested-by: Jesse Brandeburg Tested-by: Andriy Gapon Acked-by: Myles Watson --- spi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'spi.h') diff --git a/spi.h b/spi.h index 429ca6f..54c71fc 100644 --- a/spi.h +++ b/spi.h @@ -54,7 +54,7 @@ #define JEDEC_CE_C7_OUTSIZE 0x01 #define JEDEC_CE_C7_INSIZE 0x00 -/* Block Erase 0x52 is supported by SST chips. */ +/* Block Erase 0x52 is supported by SST and old Atmel chips. */ #define JEDEC_BE_52 0x52 #define JEDEC_BE_52_OUTSIZE 0x04 #define JEDEC_BE_52_INSIZE 0x00 -- cgit v1.1