From 0b4ffd58aaca065c55a7933df286dbe275d9ebd7 Mon Sep 17 00:00:00 2001 From: Urja Rannikko Date: Mon, 29 Jun 2015 23:24:23 +0000 Subject: serprog: Fix FWH/LPC by implementing serprog_map The serprog protocol does only transmit 24 bit-wide address and ignores the top 8 bit. This is fine as long as the underlying hardware ignores the latter anyway (which is the case for parallel chips that even lack the respective pins). FWH/LPC chips, however, operate on a full 32-bit (LPC) or 28-bit (FWH) address space and would fail with the fallback mapping to NULL. Corresponding to flashrom svn r1895. Signed-off-by: Urja Rannikko Acked-by: Stefan Tauner --- serprog.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'serprog.c') diff --git a/serprog.c b/serprog.c index 3de0182..a2a3fe0 100644 --- a/serprog.c +++ b/serprog.c @@ -943,3 +943,19 @@ static int serprog_spi_read(struct flashctx *flash, uint8_t *buf, } return 0; } + +void *serprog_map(const char *descr, uintptr_t phys_addr, size_t len) +{ + /* Serprog transmits 24 bits only and assumes the underlying implementation handles any remaining bits + * correctly (usually setting them to one either in software (for FWH/LPC) or relying on the fact that + * the hardware observes a subset of the address bits only). Combined with the standard mapping of + * flashrom this creates a 16 MB-wide window just below the 4 GB boundary where serprog can operate (as + * needed for non-SPI chips). Below we make sure that the requested range is within this window. */ + if ((phys_addr & 0xFF000000) == 0xFF000000) { + return (void*)phys_addr; + } else { + msg_pwarn(MSGHEADER "requested mapping %s is incompatible: 0x%zx bytes at 0x%0*" PRIxPTR ".\n", + descr, len, PRIxPTR_WIDTH, phys_addr); + return NULL; + } +} -- cgit v1.1