From 54ce73a1f5c7ddecc7579c136dbac9c2c201b621 Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Tue, 3 May 2011 21:49:41 +0000 Subject: Revert MMIO space writes on shutdown as needed Reversible MMIO space writes now use rmmio_write*(). Reversible PCI MMIO space writes now use pci_rmmio_write*(). If a MMIO value needs to be queued for restore without writing it, use rmmio_val*(). MMIO space writes which are one-shot (e.g. communication with some chip) should continue to use the permanent mmio_write* variants. Corresponding to flashrom svn r1292. Signed-off-by: Carl-Daniel Hailfinger David tested it successfully on some NM10/ICH7 platforms which switch between SPI and LPC targets (x86 BIOS ROM vs. EC firmware ROM). Acked-by: David Hendricks --- nicintel_spi.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'nicintel_spi.c') diff --git a/nicintel_spi.c b/nicintel_spi.c index 3882e81..28d332e 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -148,6 +148,11 @@ int nicintel_spi_init(void) nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, 4096); + /* Automatic restore of EECD on shutdown is not possible because EECD + * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, + * but other bits with side effects as well. Those other bits must be + * left untouched. + */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_DISABLED; tmp |= FLASH_WRITES_ENABLED; @@ -167,6 +172,9 @@ int nicintel_spi_shutdown(void) { uint32_t tmp; + /* Disable writes manually. See the comment about EECD in + * nicintel_spi_init() for details. + */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_DISABLED; -- cgit v1.1