From 75da80c17bbb992ce2b60ae15ef2fba7d23bfd8e Mon Sep 17 00:00:00 2001 From: Stefan Tauner Date: Sat, 17 Sep 2011 22:21:55 +0000 Subject: ichspi: unlock PR register restrictions on ICH8+ if not locked down Tested-by: Shailendra Sodhi (predecessor/proof of concept patch) http://www.flashrom.org/pipermail/flashrom/2011-August/007717.html Corresponding to flashrom svn r1447. Signed-off-by: Stefan Tauner Acked-by: Carl-Daniel Hailfinger --- ichspi.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'ichspi.c') diff --git a/ichspi.c b/ichspi.c index 19edb83..e3a2d75 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1200,6 +1200,29 @@ static void prettyprint_ich9_reg_pr(int i) msg_pdbg2(", unused)\n"); } +/* Set/Clear the read and write protection enable bits of PR register @i + * according to @read_prot and @write_prot. */ +static void ich9_set_pr(int i, int read_prot, int write_prot) +{ + void *addr = ich_spibar + ICH9_REG_PR0 + (i * 4); + uint32_t old = mmio_readl(addr); + uint32_t new; + + msg_gspew("PR%u is 0x%08x", i, old); + new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF)); + if (read_prot) + new |= (1 << PR_RP_OFF); + if (write_prot) + new |= (1 << PR_WP_OFF); + if (old == new) { + msg_gspew(" already.\n"); + return; + } + msg_gspew(", trying to set it to 0x%08x ", new); + rmmio_writel(new, addr); + msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); +} + static const struct spi_programmer spi_programmer_ich7 = { .type = SPI_CONTROLLER_ICH7, .max_data_read = 64, @@ -1320,6 +1343,10 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, for(i = 0; i < 5; i++) do_ich9_spi_frap(tmp, i); + /* try to disable PR locks before printing them */ + if (!ichspi_lock) + for(i = 0; i < 5; i++) + ich9_set_pr(i, 0, 0); for(i = 0; i < 5; i++) prettyprint_ich9_reg_pr(i); -- cgit v1.1