From ca8bfc6c22196e5d16c6d2625c65d6b50c04daaf Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Fri, 5 Jun 2009 17:48:08 +0000 Subject: Add programmer-specific delay functions Add external programmer delay functions so external programmers can handle the delay on their own if needed. Corresponding to flashrom svn r578. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Uwe Hermann Acked-by: Urja Rannikko --- 82802ab.c | 10 +++++----- am29f040b.c | 6 +++--- en29f002a.c | 6 +++--- flash.h | 6 +++++- flashrom.c | 10 ++++++++++ ichspi.c | 4 ++-- internal.c | 12 ++++++++++++ it87spi.c | 4 ++-- jedec.c | 52 ++++++++++++++++++++++++++-------------------------- m29f002.c | 4 ++-- m29f400bt.c | 12 ++++++------ mx29f002.c | 6 +++--- sharplhf00l04.c | 10 +++++----- spi.c | 16 ++++++++-------- sst28sf040.c | 10 +++++----- stm50flw0x0x.c | 18 +++++++++--------- udelay.c | 4 ++-- w29ee011.c | 18 +++++++++--------- w39v040c.c | 12 ++++++------ w39v080fa.c | 8 ++++---- wbsio_spi.c | 4 ++-- 21 files changed, 129 insertions(+), 103 deletions(-) diff --git a/82802ab.c b/82802ab.c index c9ec9ae..c5cf52f 100644 --- a/82802ab.c +++ b/82802ab.c @@ -53,9 +53,9 @@ int probe_82802ab(struct flashchip *flash) #endif chip_writeb(0xff, bios); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -65,7 +65,7 @@ int probe_82802ab(struct flashchip *flash) chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -92,7 +92,7 @@ uint8_t wait_82802ab(chipaddr bios) // put another command to get out of status register mode chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -124,7 +124,7 @@ int erase_82802ab_block(struct flashchip *flash, int offset) // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); - myusec_delay(10); + programmer_delay(10); // now let's see what the register is status = wait_82802ab(flash->virtual_memory); //print_82802ab_status(status); diff --git a/am29f040b.c b/am29f040b.c index 7b11e25..2dc4c36 100644 --- a/am29f040b.c +++ b/am29f040b.c @@ -29,7 +29,7 @@ static int erase_sector_29f040b(chipaddr bios, unsigned long address) chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x30, bios + address); - sleep(2); + programmer_delay(2 * 1000 * 1000); /* wait for Toggle bit ready */ toggle_ready_jedec(bios + address); @@ -75,7 +75,7 @@ int probe_29f040b(struct flashchip *flash) chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) @@ -95,7 +95,7 @@ int erase_29f040b(struct flashchip *flash) chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x10, bios + 0x555); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; diff --git a/en29f002a.c b/en29f002a.c index 9997581..f4242f5 100644 --- a/en29f002a.c +++ b/en29f002a.c @@ -37,7 +37,7 @@ int probe_en29f512(struct flashchip *flash) chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x90, bios + 0x555); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios + 0x100); id2 = chip_readb(bios + 0x101); @@ -70,7 +70,7 @@ int probe_en29f002a(struct flashchip *flash) chip_writeb(0x55, bios + 0xAAA); chip_writeb(0x90, bios + 0x555); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios + 0x100); id2 = chip_readb(bios + 0x101); @@ -97,7 +97,7 @@ int write_en29f002a(struct flashchip *flash, uint8_t *buf) chipaddr dst = bios; //chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); erase_chip_jedec(flash); printf("Programming page: "); diff --git a/flash.h b/flash.h index f6cb0cd..31c2fed 100644 --- a/flash.h +++ b/flash.h @@ -103,6 +103,8 @@ struct programmer_entry { uint8_t (*chip_readb) (const chipaddr addr); uint16_t (*chip_readw) (const chipaddr addr); uint32_t (*chip_readl) (const chipaddr addr); + + void (*delay) (int usecs); }; extern const struct programmer_entry programmer_table[]; @@ -118,6 +120,7 @@ void chip_writel(uint32_t val, chipaddr addr); uint8_t chip_readb(const chipaddr addr); uint16_t chip_readw(const chipaddr addr); uint32_t chip_readl(const chipaddr addr); +void programmer_delay(int usecs); #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) @@ -590,7 +593,7 @@ extern const struct board_info boards_bad[]; #define W_49V002FA 0x32 /* udelay.c */ -void myusec_delay(int time); +void myusec_delay(int usecs); void myusec_calibrate_delay(void); /* pcidev.c */ @@ -652,6 +655,7 @@ void mmio_writel(uint32_t val, void *addr); uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void internal_delay(int usecs); void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); void fallback_unmap(void *virt_addr, size_t len); void fallback_chip_writew(uint16_t val, chipaddr addr); diff --git a/flashrom.c b/flashrom.c index 7b6f9d5..7368d4f 100644 --- a/flashrom.c +++ b/flashrom.c @@ -46,6 +46,7 @@ const struct programmer_entry programmer_table[] = { .chip_writeb = internal_chip_writeb, .chip_writew = internal_chip_writew, .chip_writel = internal_chip_writel, + .delay = internal_delay, }, { @@ -59,6 +60,7 @@ const struct programmer_entry programmer_table[] = { .chip_writeb = dummy_chip_writeb, .chip_writew = dummy_chip_writew, .chip_writel = dummy_chip_writel, + .delay = internal_delay, }, { @@ -72,6 +74,7 @@ const struct programmer_entry programmer_table[] = { .chip_writeb = nic3com_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, + .delay = internal_delay, }, { @@ -85,6 +88,7 @@ const struct programmer_entry programmer_table[] = { .chip_writeb = satasii_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, + .delay = internal_delay, }, { @@ -98,6 +102,7 @@ const struct programmer_entry programmer_table[] = { .chip_writeb = dummy_chip_writeb, .chip_writew = dummy_chip_writew, .chip_writel = dummy_chip_writel, + .delay = internal_delay, }, {}, @@ -155,6 +160,11 @@ uint32_t chip_readl(const chipaddr addr) return programmer_table[programmer].chip_readl(addr); } +void programmer_delay(int usecs) +{ + programmer_table[programmer].delay(usecs); +} + void map_flash_registers(struct flashchip *flash) { size_t size = flash->total_size * 1024; diff --git a/ichspi.c b/ichspi.c index 8f8d6e6..4f83908 100644 --- a/ichspi.c +++ b/ichspi.c @@ -453,7 +453,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, /* wait for cycle complete */ timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) { - myusec_delay(10); + programmer_delay(10); } if (!timeout) { printf_debug("timeout\n"); @@ -570,7 +570,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /*wait for cycle complete */ timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { - myusec_delay(10); + programmer_delay(10); } if (!timeout) { printf_debug("timeout\n"); diff --git a/internal.c b/internal.c index c2d8f6b..d24bb34 100644 --- a/internal.c +++ b/internal.c @@ -195,6 +195,18 @@ uint32_t mmio_readl(void *addr) return *(volatile uint32_t *) addr; } +void internal_delay(int usecs) +{ + /* If the delay is >1 s, use usleep because timing does not need to + * be so precise. + */ + if (usecs > 1000000) { + usleep(usecs); + } else { + myusec_delay(usecs); + } +} + /* Fallback map() for programmers which don't need special handling */ void *fallback_map(const char *descr, unsigned long phys_addr, size_t len) { diff --git a/it87spi.c b/it87spi.c index 2528b91..e90cf8d 100644 --- a/it87spi.c +++ b/it87spi.c @@ -220,7 +220,7 @@ static int it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) * This usually takes 1-10 ms, so wait in 1 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(1000); + programmer_delay(1000); return 0; } @@ -245,7 +245,7 @@ int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf) return result; spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); + programmer_delay(10); } /* resume normal ops... */ OUTB(0x20, it8716f_flashport); diff --git a/jedec.c b/jedec.c index 5f23f51..26e9caa 100644 --- a/jedec.c +++ b/jedec.c @@ -73,7 +73,7 @@ void unprotect_jedec(chipaddr bios) chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0x20, bios + 0x5555); - usleep(200); + programmer_delay(200); } void protect_jedec(chipaddr bios) @@ -82,7 +82,7 @@ void protect_jedec(chipaddr bios) chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xA0, bios + 0x5555); - usleep(200); + programmer_delay(200); } int probe_jedec(struct flashchip *flash) @@ -110,14 +110,14 @@ int probe_jedec(struct flashchip *flash) /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ - myusec_delay(probe_timing_enter); + programmer_delay(probe_timing_enter); /* Read product ID */ id1 = chip_readb(bios); @@ -139,11 +139,11 @@ int probe_jedec(struct flashchip *flash) /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(probe_timing_exit); + programmer_delay(probe_timing_exit); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); if (!oddparity(id1)) @@ -179,18 +179,18 @@ int erase_sector_jedec(chipaddr bios, unsigned int page) { /* Issue the Sector Erase command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x30, bios + page); - myusec_delay(10); + programmer_delay(10); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -202,18 +202,18 @@ int erase_block_jedec(chipaddr bios, unsigned int block) { /* Issue the Sector Erase command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x50, bios + block); - myusec_delay(10); + programmer_delay(10); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -227,18 +227,18 @@ int erase_chip_jedec(struct flashchip *flash) /* Issue the JEDEC Chip Erase command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x10, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); diff --git a/m29f002.c b/m29f002.c index 78cdc75..8ad86d2 100644 --- a/m29f002.c +++ b/m29f002.c @@ -29,7 +29,7 @@ int erase_m29f002(struct flashchip *flash) chip_writeb(0xaa, bios + 0x555); chip_writeb(0x55, bios + 0xaaa); chip_writeb(0x10, bios + 0x555); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; } @@ -44,7 +44,7 @@ static void rewrite_block(chipaddr bios, uint8_t *src, chip_writeb(0xaa, bios + 0x555); chip_writeb(0x55, bios + 0xaaa); chip_writeb(0x30, dst); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); /* program */ diff --git a/m29f400bt.c b/m29f400bt.c index 7d63d58..85f9dc0 100644 --- a/m29f400bt.c +++ b/m29f400bt.c @@ -26,7 +26,7 @@ void protect_m29f400bt(chipaddr bios) chip_writeb(0x55, bios + 0x555); chip_writeb(0xA0, bios + 0xAAA); - usleep(200); + programmer_delay(200); } void write_page_m29f400bt(chipaddr bios, uint8_t *src, @@ -42,7 +42,7 @@ void write_page_m29f400bt(chipaddr bios, uint8_t *src, /* transfer data from source to destination */ chip_writeb(*src, dst); //chip_writeb(0xF0, bios); - //usleep(5); + //programmer_delay(5); toggle_ready_jedec(dst); printf ("Value in the flash at address 0x%lx = %#x, want %#x\n", @@ -61,7 +61,7 @@ int probe_m29f400bt(struct flashchip *flash) chip_writeb(0x55, bios + 0x555); chip_writeb(0x90, bios + 0xAAA); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in @@ -73,7 +73,7 @@ int probe_m29f400bt(struct flashchip *flash) chip_writeb(0x55, bios + 0x555); chip_writeb(0xF0, bios + 0xAAA); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -95,7 +95,7 @@ int erase_m29f400bt(struct flashchip *flash) chip_writeb(0x55, bios + 0x555); chip_writeb(0x10, bios + 0xAAA); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; @@ -113,7 +113,7 @@ int block_erase_m29f400bt(chipaddr bios, chipaddr dst) //chip_writeb(0x10, bios + 0xAAA); chip_writeb(0x30, dst); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; diff --git a/mx29f002.c b/mx29f002.c index faff6f8..c96cc93 100644 --- a/mx29f002.c +++ b/mx29f002.c @@ -34,7 +34,7 @@ int probe_29f002(struct flashchip *flash) chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) @@ -55,7 +55,7 @@ int erase_29f002(struct flashchip *flash) chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x10, bios + 0x555); - myusec_delay(100); + programmer_delay(100); toggle_ready_jedec(bios); // while ((*bios & 0x40) != 0x40) @@ -82,7 +82,7 @@ int write_29f002(struct flashchip *flash, uint8_t *buf) chipaddr dst = bios; chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); erase_29f002(flash); //*bios = 0xF0; #if 1 diff --git a/sharplhf00l04.c b/sharplhf00l04.c index 1aeb2f3..4d652ae 100644 --- a/sharplhf00l04.c +++ b/sharplhf00l04.c @@ -46,9 +46,9 @@ int probe_lhf00l04(struct flashchip *flash) #endif chip_writeb(0xff, bios); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -58,7 +58,7 @@ int probe_lhf00l04(struct flashchip *flash) chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -85,7 +85,7 @@ uint8_t wait_lhf00l04(chipaddr bios) // put another command to get out of status register mode chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -118,7 +118,7 @@ int erase_lhf00l04_block(struct flashchip *flash, int offset) // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); - myusec_delay(10); + programmer_delay(10); // now let's see what the register is status = wait_lhf00l04(flash->virtual_memory); print_lhf00l04_status(status); diff --git a/spi.c b/spi.c index 5d19c41..a342923 100644 --- a/spi.c +++ b/spi.c @@ -425,7 +425,7 @@ int spi_chip_erase_60(struct flashchip *flash) */ /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - sleep(1); + programmer_delay(1000 * 1000); return 0; } @@ -453,7 +453,7 @@ int spi_chip_erase_c7(struct flashchip *flash) */ /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - sleep(1); + programmer_delay(1000 * 1000); return 0; } @@ -485,7 +485,7 @@ int spi_block_erase_52(const struct flashchip *flash, unsigned long addr) * This usually takes 100-4000 ms, so wait in 100 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(100 * 1000); + programmer_delay(100 * 1000); return 0; } @@ -511,7 +511,7 @@ int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr) * This usually takes 100-4000 ms, so wait in 100 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(100 * 1000); + programmer_delay(100 * 1000); return 0; } @@ -557,7 +557,7 @@ int spi_sector_erase(const struct flashchip *flash, unsigned long addr) * This usually takes 15-800 ms, so wait in 10 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(10 * 1000); + programmer_delay(10 * 1000); return 0; } @@ -690,7 +690,7 @@ int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) spi_write_enable(); spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); + programmer_delay(10); } return 0; @@ -748,13 +748,13 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf) return result; spi_command(6, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(5); /* SST25VF040B Tbp is max 10us */ while (pos < size) { w[1] = buf[pos++]; w[2] = buf[pos++]; spi_command(3, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(5); /* SST25VF040B Tbp is max 10us */ } spi_write_disable(); return 0; diff --git a/sst28sf040.c b/sst28sf040.c index c858f54..bbbdbd3 100644 --- a/sst28sf040.c +++ b/sst28sf040.c @@ -94,16 +94,16 @@ int probe_28sf040(struct flashchip *flash) uint8_t id1, id2; chip_writeb(RESET, bios); - myusec_delay(10); + programmer_delay(10); chip_writeb(READ_ID, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); - myusec_delay(10); + programmer_delay(10); id2 = chip_readb(bios + 0x01); chip_writeb(RESET, bios); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) @@ -121,7 +121,7 @@ int erase_28sf040(struct flashchip *flash) chip_writeb(CHIP_ERASE, bios); protect_28sf040(bios); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; diff --git a/stm50flw0x0x.c b/stm50flw0x0x.c index b2469f3..5ca769b 100644 --- a/stm50flw0x0x.c +++ b/stm50flw0x0x.c @@ -35,7 +35,7 @@ void protect_stm50flw0x0x(chipaddr bios) chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xA0, bios + 0x5555); - usleep(200); + programmer_delay(200); } int probe_stm50flw0x0x(struct flashchip *flash) @@ -46,11 +46,11 @@ int probe_stm50flw0x0x(struct flashchip *flash) /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); - myusec_delay(40); + programmer_delay(40); /* Read product ID */ id1 = chip_readb(bios); @@ -72,11 +72,11 @@ int probe_stm50flw0x0x(struct flashchip *flash) /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(40); + programmer_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, largeid1, largeid2); @@ -101,7 +101,7 @@ static void wait_stm50flw0x0x(chipaddr bios) // put another command to get out of status register mode chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); @@ -170,7 +170,7 @@ int erase_block_stm50flw0x0x(struct flashchip *flash, int offset) // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); - myusec_delay(10); + programmer_delay(10); wait_stm50flw0x0x(flash->virtual_memory); diff --git a/udelay.c b/udelay.c index 4160300..9a0ab36 100644 --- a/udelay.c +++ b/udelay.c @@ -24,10 +24,10 @@ // count to a billion. Time it. If it's < 1 sec, count to 10B, etc. unsigned long micro = 1; -void myusec_delay(int time) +void myusec_delay(int usecs) { volatile unsigned long i; - for (i = 0; i < time * micro; i++) ; + for (i = 0; i < usecs * micro; i++) ; } void myusec_calibrate_delay(void) diff --git a/w29ee011.c b/w29ee011.c index d630440..77724be 100644 --- a/w29ee011.c +++ b/w29ee011.c @@ -38,17 +38,17 @@ int probe_w29ee011(struct flashchip *flash) /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x60, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); /* Read product ID */ id1 = chip_readb(bios); @@ -56,11 +56,11 @@ int probe_w29ee011(struct flashchip *flash) /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); diff --git a/w39v040c.c b/w39v040c.c index 097d655..48e9bd3 100644 --- a/w39v040c.c +++ b/w39v040c.c @@ -26,22 +26,22 @@ int probe_w39v040c(struct flashchip *flash) uint8_t id1, id2, lock; chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 1); lock = chip_readb(bios + 0xfff2); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(40); + programmer_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); if (!oddparity(id1)) diff --git a/w39v080fa.c b/w39v080fa.c index ba4673a..8dc882a 100644 --- a/w39v080fa.c +++ b/w39v080fa.c @@ -29,7 +29,7 @@ int probe_winbond_fwhub(struct flashchip *flash) chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0x90, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); /* Read product ID */ id1 = chip_readb(bios); @@ -39,7 +39,7 @@ int probe_winbond_fwhub(struct flashchip *flash) chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); @@ -108,7 +108,7 @@ int unlock_winbond_fwhub(struct flashchip *flash) chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0x90, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); /* Read Hardware Lock Bits */ locking = chip_readb(bios + 0xffff2); @@ -117,7 +117,7 @@ int unlock_winbond_fwhub(struct flashchip *flash) chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("Lockout bits:\n"); diff --git a/wbsio_spi.c b/wbsio_spi.c index 045aa0e..554bf2a 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -159,7 +159,7 @@ int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, OUTB(writearr[0], wbsio_spibase); OUTB(mode, wbsio_spibase + 1); - myusec_delay(10); + programmer_delay(10); if (!readcnt) return 0; @@ -203,7 +203,7 @@ int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf) for (pos = 0; pos < size; pos++) { spi_byte_program(pos, buf[pos]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); + programmer_delay(10); } spi_write_disable(); return 0; -- cgit v1.1