From 89edf36c177eec2b1a2cbbcaff48c4e9a946a190 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Fri, 23 Aug 2013 23:29:23 +0000 Subject: Add additional error handling to pcidev_readbar() callers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is mostly a leftover of Niklas' "remove exit call from pcidev_init" patch. While not explicitly necessary detecting errors early is usually a good idea. Corresponding to flashrom svn r1718. Signed-off-by: Niklas Söderlund Signed-off-by: Stefan Tauner Acked-by: Stefan Tauner --- atahpt.c | 2 ++ drkaiser.c | 2 ++ gfxnvidia.c | 3 +++ nic3com.c | 2 ++ nicintel.c | 7 ++++++- nicintel_spi.c | 3 +++ nicnatsemi.c | 2 ++ nicrealtek.c | 2 ++ ogp_spi.c | 3 +++ pcidev.c | 2 +- satamv.c | 6 ++++++ satasii.c | 4 ++++ 12 files changed, 36 insertions(+), 2 deletions(-) diff --git a/atahpt.c b/atahpt.c index f8be8c4..242e14a 100644 --- a/atahpt.c +++ b/atahpt.c @@ -69,6 +69,8 @@ int atahpt_init(void) return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4); + if (!io_base_addr) + return 1; /* Enable flash access. */ reg32 = pci_read_long(dev, REG_FLASH_ACCESS); diff --git a/drkaiser.c b/drkaiser.c index 8c9fb6a..0cf1fdb 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -69,6 +69,8 @@ int drkaiser_init(void) return 1; addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); + if (!addr) + return 1; /* Write magic register to enable flash write. */ rpci_write_word(dev, PCI_MAGIC_DRKAISER_ADDR, PCI_MAGIC_DRKAISER_VALUE); diff --git a/gfxnvidia.c b/gfxnvidia.c index 8f3aa44..d3ee14e 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -90,6 +90,9 @@ int gfxnvidia_init(void) return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + io_base_addr += 0x300000; msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); diff --git a/nic3com.c b/nic3com.c index 8d67b54..27e28c7 100644 --- a/nic3com.c +++ b/nic3com.c @@ -96,6 +96,8 @@ int nic3com_init(void) return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; id = dev->device_id; diff --git a/nicintel.c b/nicintel.c index 305657c..98ba29f 100644 --- a/nicintel.c +++ b/nicintel.c @@ -76,12 +76,17 @@ int nicintel_init(void) return 1; addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); + if (!addr) + return 1; + nicintel_bar = rphysmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); if (nicintel_bar == ERROR_PTR) return 1; addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); - /* FIXME: This is not an aligned mapping. Use 4k? */ + if (!addr) + return 1; + nicintel_control_bar = rphysmap("Intel NIC control/status reg", addr, NICINTEL_CONTROL_MEMMAP_SIZE); if (nicintel_control_bar == ERROR_PTR) return 1; diff --git a/nicintel_spi.c b/nicintel_spi.c index b1bce6a..11b26c7 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -173,6 +173,9 @@ int nicintel_spi_init(void) return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE); /* Automatic restore of EECD on shutdown is not possible because EECD * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, diff --git a/nicnatsemi.c b/nicnatsemi.c index d62a73f..cb8da6d 100644 --- a/nicnatsemi.c +++ b/nicnatsemi.c @@ -64,6 +64,8 @@ int nicnatsemi_init(void) return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 * in another. My NIC has MA16 connected to A16 on the boot ROM socket diff --git a/nicrealtek.c b/nicrealtek.c index fb8e9e1..02fbd39 100644 --- a/nicrealtek.c +++ b/nicrealtek.c @@ -69,6 +69,8 @@ int nicrealtek_init(void) return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; /* Beware, this ignores the vendor ID! */ switch (dev->device_id) { diff --git a/ogp_spi.c b/ogp_spi.c index 3aed6e8..f8f7b2d 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -131,6 +131,9 @@ int ogp_spi_init(void) return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + ogp_spibar = rphysmap("OGP registers", io_base_addr, 4096); if (ogp_spibar == ERROR_PTR) return 1; diff --git a/pcidev.c b/pcidev.c index c7e9d78..3a3f77c 100644 --- a/pcidev.c +++ b/pcidev.c @@ -94,7 +94,7 @@ uintptr_t pcidev_readbar(struct pci_dev *dev, int bar) supported_cycles = pci_read_word(dev, PCI_COMMAND); - msg_pdbg("Requested BAR is "); + msg_pdbg("Requested BAR is of type "); switch (bartype) { case TYPE_MEMBAR: msg_pdbg("MEM"); diff --git a/satamv.c b/satamv.c index b44e1cf..3065f0c 100644 --- a/satamv.c +++ b/satamv.c @@ -88,6 +88,9 @@ int satamv_init(void) return 1; addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!addr) + return 1; + mv_bar = rphysmap("Marvell 88SX7042 registers", addr, 0x20000); if (mv_bar == ERROR_PTR) return 1; @@ -136,6 +139,9 @@ int satamv_init(void) /* Get I/O BAR location. */ tmp = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); + if (!addr) + return 1; + /* Truncate to reachable range. * FIXME: Check if the I/O BAR is actually reachable. * This is an arch specific check. diff --git a/satasii.c b/satasii.c index 37266eb..83dc62c 100644 --- a/satasii.c +++ b/satasii.c @@ -85,9 +85,13 @@ int satasii_init(void) if ((id == 0x3132) || (id == 0x3124)) { addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!addr) + return 1; reg_offset = 0x70; } else { addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5); + if (!addr) + return 1; reg_offset = 0x50; } -- cgit v1.1