From 1d3a2fefbc636fb569bd1d018fb97b1b17c08e99 Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Tue, 27 Jul 2010 22:03:46 +0000 Subject: Convert MMIO accesses of non-internal PCI-based programmers to be endian-agnostic Convert all PCI-based external programmers to use special little-endian accessors for all MMIO regions of PCI devices. This patch does _not_ touch the internal programmer (which is PCI-based as well). Huge thanks go to Misha Manulis who worked with me to create a first version of this patch for the satasii programmer based on modification of generic code. Huge thanks also go to Segher Boessenkool for suggesting the pci_mmio_ prefix for the abstraction layer. NOTE to package maintainers: With this patch, compilation and usage of flashrom should be safe on x86, x86_64, MIPS (little and big endian) and PowerPC (big endian). The internal programmer is disabled on non-x86/x86_64 (but it compiles). The atahpt, nic3com, nicnatsemi, nicrealtek and rayer_spi can not be compiled on non-x86/x86_64 because port space I/O is not (yet) supported. Please compile with default settings on x86/x86_64 and with the following settings on all other architectures: make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no CONFIG_NICNATSEMI=no CONFIG_RAYER_SPI=no Corresponding to flashrom svn r1111. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Misha Manulis --- chipset_enable.c | 4 ++-- drkaiser.c | 4 ++-- flash.h | 8 ++++++++ gfxnvidia.c | 4 ++-- satasii.c | 20 ++++++++++---------- 5 files changed, 24 insertions(+), 16 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 8d64e0c..6254d2f 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -33,10 +33,10 @@ #include #include "flash.h" -#if defined(__i386__) || defined(__x86_64__) - #define NOT_DONE_YET 1 +#if defined(__i386__) || defined(__x86_64__) + static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; diff --git a/drkaiser.c b/drkaiser.c index 09d8daf..0d1f250 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -69,10 +69,10 @@ int drkaiser_shutdown(void) void drkaiser_chip_writeb(uint8_t val, chipaddr addr) { - mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); + pci_mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); } uint8_t drkaiser_chip_readb(const chipaddr addr) { - return mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); + return pci_mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); } diff --git a/flash.h b/flash.h index 8a16396..aba2380 100644 --- a/flash.h +++ b/flash.h @@ -418,6 +418,8 @@ uint16_t internal_chip_readw(const chipaddr addr); uint32_t internal_chip_readl(const chipaddr addr); void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); #endif + +/* hwaccess.c */ void mmio_writeb(uint8_t val, void *addr); void mmio_writew(uint16_t val, void *addr); void mmio_writel(uint32_t val, void *addr); @@ -430,6 +432,12 @@ void mmio_le_writel(uint32_t val, void *addr); uint8_t mmio_le_readb(void *addr); uint16_t mmio_le_readw(void *addr); uint32_t mmio_le_readl(void *addr); +#define pci_mmio_writeb mmio_le_writeb +#define pci_mmio_writew mmio_le_writew +#define pci_mmio_writel mmio_le_writel +#define pci_mmio_readb mmio_le_readb +#define pci_mmio_readw mmio_le_readw +#define pci_mmio_readl mmio_le_readl /* programmer.c */ int noop_shutdown(void); diff --git a/gfxnvidia.c b/gfxnvidia.c index 29e2910..252ddc5 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -100,10 +100,10 @@ int gfxnvidia_shutdown(void) void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr) { - mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); + pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); } uint8_t gfxnvidia_chip_readb(const chipaddr addr) { - return mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); + return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); } diff --git a/satasii.c b/satasii.c index 5c56293..4e1df81 100644 --- a/satasii.c +++ b/satasii.c @@ -61,7 +61,7 @@ int satasii_init(void) sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; /* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) + if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); buses_supported = CHIP_BUSTYPE_PARALLEL; @@ -80,32 +80,32 @@ void satasii_chip_writeb(uint8_t val, chipaddr addr) { uint32_t ctrl_reg, data_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set writes and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(data_reg, (sii_bar + 4)); - mmio_writel(ctrl_reg, sii_bar); + data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val; + pci_mmio_writel(data_reg, (sii_bar + 4)); + pci_mmio_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (pci_mmio_readl(sii_bar) & (1 << 25)) ; } uint8_t satasii_chip_readb(const chipaddr addr) { uint32_t ctrl_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set reads and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); - mmio_writel(ctrl_reg, sii_bar); + pci_mmio_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (pci_mmio_readl(sii_bar) & (1 << 25)) ; - return (mmio_readl(sii_bar + 4)) & 0xff; + return (pci_mmio_readl(sii_bar + 4)) & 0xff; } -- cgit v1.1