path: root/wbsio_spi.c
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* Chips like the SST SST25VF080B can only handle single byte writes outside ↵Carl-Daniel Hailfinger2009-05-091-1/+1
| | | | | | | | | | | | | | | | | | AAI mode Change SPI architecture to handle 1-byte chunk chip writing differently from 256-byte chunk chip writing. Annotate SPI chip write functions with _256 or _1 suffix denoting the number of bytes they write at maximum. The 1-byte chunk writing is cut-n-pasted to different SPI drivers right now. A later patch can move them to the generic spi_chip_write_1. Corresponding to flashrom svn r485. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Carl-Daniel Hailfinger <>
* Refine handling of spi_write_enable() failures to fix chip erases on ichspiCarl-Daniel Hailfinger2009-05-091-1/+4
| | | | | | | | | | | | | | | Until the ICH SPI driver can handle preopcodes as standalone opcodes, we should handle such special opcode failure gracefully on ICH and compatible chipsets. This fixes chip erase on almost all ICH+VIA SPI masters. Thanks to Ali Nadalizadeh for helping track down this bug! Corresponding to flashrom svn r484. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Carl-Daniel Hailfinger <>
* Some coding style and consistency fixesUwe Hermann2009-04-151-6/+12
| | | | | | | Corresponding to flashrom svn r429 and coreboot v2 svn r4117. Signed-off-by: Uwe Hermann <> Acked-by: Uwe Hermann <>
* Winbond SuperIO SPI driverPeter Stuge2009-01-261-0/+201
Developed and tested to work on Intel D201GLY in July 2008. Tested by a helpful person on IRC whose name I've since forgotten. Sorry! Corresponding to flashrom svn r404 and coreboot v2 svn r3910. Signed-off-by: Peter Stuge <> Acked-by: Ward Vandewege <>
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