path: root/programmer.h
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* Use shutdown callback mechanism to shutdown programmersDavid Hendricks2011-06-141-19/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch attempts to resolve some programmer shutdown ordering issues by having the programmer init functions register shutdown callbacks explicitly wherever it makes most sense. Before, assumptions were made that could lead to the internal programmer's state changing before the external programmer could be shut down properly. Now, each programmer cleans up after itself and (hopefully) performs each operation in the correct order. As a side-effect, this patch gives us a better usage model for reverse operations such as rpci_* and rmmio_*. In the long-run, this should make reversing the initialization process easier to understand, less tedious, and less error-prone. In short, this patch does the following: - Registers a shutdown callback during initialization for each programmer. - Kills the .shutdown function pointer from programmer_entry struct. Also, make most shutdown functions static. - Adds a few minor clean-ups and corrections (e.g. missing physunmap() calls). TODO: Remove forward declaration of serprog_shutdown() (added to simplify diff) Corresponding to flashrom svn r1338. Signed-off-by: David Hendricks <> Acked-by: Carl-Daniel Hailfinger <>
* Fix compilation for CONFIG_INTERNAL=noCarl-Daniel Hailfinger2011-06-091-17/+13
| | | | | | | | | | | | CONFIG_INTERNAL implies Super I/O support and NEED_PCI. NEED_PCI is only used to guard PCI stuff which may be needed for external PCI-based programmers. That way, using #if NEED_PCI can be avoided inside #if CONFIG_INTERNAL. Corresponding to flashrom svn r1326. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Michael Karcher <>
* Eliminate magic numbers indicating maximum column sizes in print.cStefan Tauner2011-05-261-4/+4
| | | | | | | | | | | Without this the magic numbers need to be kept in sync with the maximum length of the strings printed in the corresponding column. if not, an overflow and a nasty ' '-storm occur on executing flashrom -L. Corresponding to flashrom svn r1318. Signed-off-by: Stefan Tauner <> Acked-by: Carl-Daniel Hailfinger <>
* Kill central list of SPI programmersMichael Karcher2011-05-111-35/+5
| | | | | | | | | | | | | | | | | | Remove the array spi_programmer, replace it by dynamic registration instead. Also initially start with no busses supported, and switch to the default non-SPI only for the internal programmer. Also this patch changes the initialization for the buses_supported variable from "everything-except-SPI" to "nothing". All programmers have to set the bus type on their own, and this enables register_spi_programmer to just add the SPI both for on-board SPI interfaces (where the internal programmer already detected the other bus types), as well as for external programmers (where we have the default "none"). Corresponding to flashrom svn r1299. Signed-off-by: Michael Karcher <> Acked-by: Carl-Daniel Hailfinger <>
* Factor out SPI write/read chunking wrappersMichael Karcher2011-05-111-13/+8
| | | | | | | Corresponding to flashrom svn r1298. Signed-off-by: Michael Karcher <> Acked-by: Carl-Daniel Hailfinger <>
* Intel NIC with parallel flash supportCarl-Daniel Hailfinger2011-05-081-1/+13
| | | | | | | | | | Tested-by: Maciej Pijanka <> Corresponding to flashrom svn r1297. Signed-off-by: Carl-Daniel Hailfinger <> Tested-by: Anton Kochkov <> Acked-by: Anton Kochkov <>
* Revamp board-specific quirk handling, allow for laptop supportCarl-Daniel Hailfinger2011-05-051-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Handle board-specific quirks in three phases: 1. Before Super I/O probing (e.g. blacklisting of some Super I/O probes, or unhiding the Super I/O) 2. Before the laptop enforcement decision (e.g. whitelisting a laptop for flashing) 3. After chipset enabling (all current board enables) Implementation note: All entries in board_pciid_enables get an additional phase parameter. Alternative variants (3 tables instead of 1) also have their downsides, and I chose table bloat over table multiplication). With this patch, it should be possible to whitelist supported laptops with a matching entry (phase P2) in board_pciid_enables which points to a function setting laptop_ok=1. (In case DMI is broken, matching might be a little bit more difficult, but it is still doable.) Corresponding to flashrom svn r1294. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Michael Karcher <>
* Constify flashchips arrayCarl-Daniel Hailfinger2011-05-041-1/+1
| | | | | | | | | This moves 99.5% of the .data section to .rodata (which ends up in .text). Corresponding to flashrom svn r1293. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Stefan Reinauer <>
* Revert MMIO space writes on shutdown as neededCarl-Daniel Hailfinger2011-05-031-0/+12
| | | | | | | | | | | | | | | | | | Reversible MMIO space writes now use rmmio_write*(). Reversible PCI MMIO space writes now use pci_rmmio_write*(). If a MMIO value needs to be queued for restore without writing it, use rmmio_val*(). MMIO space writes which are one-shot (e.g. communication with some chip) should continue to use the permanent mmio_write* variants. Corresponding to flashrom svn r1292. Signed-off-by: Carl-Daniel Hailfinger <> David tested it successfully on some NM10/ICH7 platforms which switch between SPI and LPC targets (x86 BIOS ROM vs. EC firmware ROM). Acked-by: David Hendricks <>
* Add support for more than one Super I/O or EC per machineCarl-Daniel Hailfinger2011-04-271-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Flashrom currently only supports exactly one Super I/O or Embedded Controller, and this means quite a few notebooks and a small subset of desktop/server boards cannot be handled reliably and easily. Allow detection and initialization of up to 3 Super I/O and/or EC chips. WARNING! If a Super I/O or EC responds on multiple ports (0x2e and 0x4e), the code will do the wrong thing (namely, initialize the hardware twice). I have no idea if we should handle such situations, and whether we should ignore the second chip with identical ID or not. Initializing the hardware twice for the IT87* family is _not_ a problem, but I don't know how well IT85* can handle it (and whether IT85* would listen at more than one port anyway). Corresponding to flashrom svn r1289. Signed-off-by: Carl-Daniel Hailfinger <> Thanks to Thomas Schneider for testing on a board with ITE IT87* SPI. Test report (success) is here: Thanks to David Hendricks for testing on a Google Cr-48 laptop with ITE IT85* EC SPI. Test report (success) is here: Acked-by: David Hendricks <>
* Various IT85* cleanups and fixesCarl-Daniel Hailfinger2011-03-081-1/+3
| | | | | | | | | | | | | | | | | | | | Fix a few typos. Change the EC memory region mapping name. Drop unused function parameter. Use mmio_writeb()/mmio_readb() to get reliable access to volatile memory locations instead of plain pointer access which is optimized away by gcc. Use own it85_* SPI high-level chip read/write functions instead of relying on unrelated ICH functions. Corresponding to flashrom svn r1279. Signed-off-by: Carl-Daniel Hailfinger <> David writes: I applied the patch against the Chromium OS branch and successfully tested read and write operations on a Cr48. Acked-by: David Hendricks <>
* Fix compilation if CONFIG_INTERNAL=noCarl-Daniel Hailfinger2011-03-081-1/+1
| | | | | | | | | | | Fix compilation if everything except CONFIG_SATAMV is no. Do not compile in PCI support for wiki printing if no PCI devices are supported. Corresponding to flashrom svn r1278. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Michael Karcher <>
* Remove vendorid parameter from pcidev_init()Carl-Daniel Hailfinger2011-03-071-4/+1
| | | | | | | | | | | | | | | Simplify pcidev_init by killing the vendorid parameter which was pretty useless anyway since it was present in the pcidevs parameter as well. This also allows us to handle multiple programmers with different vendor IDs in the same driver. Fix compilation of flashrom with only the nicrealtek driver. Corresponding to flashrom svn r1274. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Michael Karcher <>
* Update the ITE IT8500 EC support to match the current state of the ↵David Hendricks2011-02-281-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | flashrom-chromium tree This code has been deployed and tested to work on the Cr-48. There are a few caveats, though: - The boot BIOS straps register must be modified to select LPC. This can be done with the "" script (Install iotools at before using select_bbs). - It is very important to disable power management daemons before running flashrom on this EC. I commented out the brute force method we use in the Chromium OS branch that disables powerd, since IIRC Carl-Daniel has a better approach in the works. - Due to dependencies which may be introduced by the OEM/ODM EC firmware, the code is not guaranteed to work for anything other than the Cr-48. Corresponding to flashrom svn r1263. Signed-off-by: David Hendricks <> Carl-Daniel comments: Code is not hooked up yet because probing needs to be sorted out. Acked-by: Carl-Daniel Hailfinger <>
* Support 64-bit MEM BARs wherever possibleCarl-Daniel Hailfinger2011-02-151-2/+2
| | | | | | | | | | | | | | | | | Add more sanity checks for BARs and abort if resources are unreachable. Undecoded resources are reported, but flashrom will proceed anyway just in case the BIOS screwed up the configuration. (The empty CardBus handler is intentional, according to the spec no BARs in PCI config space are used by CardBus.) Found while working on a driver for the Angelbird PCIe-based SSD which has 64-bit capable MEM BARs. Corresponding to flashrom svn r1261. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Stefan Reinauer <>
* Support for Angelbird Wings PCIe SSD (solid-state drive)Carl-Daniel Hailfinger2011-02-041-0/+12
| | | | | | | | | | | | | | | It uses a Marvell 88SX7042 SATA controller internally which has access to a separate flash chip hosting the option ROM. Thanks to Angelbird Ltd for sponsoring development of this driver! I expect the code to work for that SATA controller even if it is not part of the Angelbird SSD. Corresponding to flashrom svn r1258. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Stefan Reinauer <>
* Compilation fix for djgppIdwer Vollering2010-12-261-3/+3
| | | | | | | | | | | | This corrects a djgpp build error, seen with r1232 and later. pcidev.c:210: error: conflicting types for 'rpci_write_long' programmer.h:226: error: previous declaration of 'rpci_write_long' was here Corresponding to flashrom svn r1249. Signed-off-by: Idwer Vollering <> Acked-by: Michael Karcher <>
* Add support for the Open Graphics Project development card, OGD1, as a SPI ↵Mark Marshall2010-12-031-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flash programmer The project is in the the process of designing and making a complete, open source, graphics card. More info at The first development card is a PCI add in card containing a couple of FPGAs and a couple of serial flash chips (amongst other things). The FPGAs are called XP10 and S3 (their part numbers). The XP10 contains its own flash and does not need to be programmed by flashrom - it ensures that the device can enumerate on the PCI bus without needing further configuration. The larger FPGA is the S3. This is configured from a large SPI flash (2 MBytes). The second SPI flash is used to store the VGA BIOS. It is smaller (128 KBytes). This patch adds support for programming either of the two SPI flash chips. The programmer device takes one configuration option which selects which of the two flash chips is accessed. This must be set to either "cprom" or "bprom". (The project refers to the two chips as "cprom" / "bprom", "s3" and "bios" are more readable alternatives). Add support for SST SST25VF010 (REMS). Mark SST SST25VF016B as tested for write. Corresponding to flashrom svn r1241. Signed-off-by: Mark Marshall <> Acked-by: Carl-Daniel Hailfinger <>
* Add chunked write ability to the Dediprog SF100 driverCarl-Daniel Hailfinger2010-11-231-0/+1
| | | | | | | | | | | | | | Please note that the write speedup only applies to chips which have SPI page write (i.e. chips using spi_chip_write_256). This is a quick fix for write speed until I get around to implementing full bulk SPI write support. Corresponding to flashrom svn r1235. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Richard A. Smith <> Acked-by: Mathias Krause <>
* Revert PCI config space writes on shutdownCarl-Daniel Hailfinger2010-11-101-0/+6
| | | | | | | | | | | | | | | This means all chipset enables etc. will be undone on shutdown. Reversible PCI config space writes now use rpci_write_*(). PCI config space writes which are one-shot (e.g. communication via config space) should continue to use the permanent pci_write_* variants. Extend the number of available register_shutdown slots to 32. Corresponding to flashrom svn r1232. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Michael Karcher <>
* SPI bitbanging: request/release busCarl-Daniel Hailfinger2010-09-151-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | SPI bitbanging on devices which speak SPI natively has a dual-use problem: We need to shut down normal SPI operations to do the bitbanging ourselves. Once we're done, it makes a lot of sense to reenable "normal" SPI operations again. Add request_bus/release_bus functions to struct bitbang_spi_master. Add a bitbang shutdown function (not used yet). Change MCP SPI and Intel NIC SPI to use the new request/release bus infrastructure. Cosmetic changes to a few error messages (80 column limit). There are multiple possible strategies for bus request/release: - Request at the start of a SPI command, release immediately afterwards. - Request at the start of a SPI multicommand, release once all commands of the multicommand are done. - Request on programmer init, release on shutdown. Each strategy has its own advantages. For now, we will stay with the first strategy which worked fine so far. Corresponding to flashrom svn r1171. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Uwe Hermann <>
* Add Intel Gigabit NIC SPI flashing supportIdwer Vollering2010-09-031-3/+22
| | | | | | | | | | | | | | | | | | | | Tested on a 82541PI (0x8086, 0x107c) using 32-bit hardware. The last line in nicintel_request_spibus() could be changed so that FL_BUSY is used instead. Shortened sample log: [...] Found "Intel 82541PI Gigabit Ethernet Controller" (8086:107c, BDF 01:03.0). Found chip "ST M25P10.RES" (128 KB, SPI) at physical address 0xfffe0000. Multiple flash chips were detected: M25P05.RES M25P10.RES Please specify which chip to use with the -c <chipname> option. [...] Corresponding to flashrom svn r1151. Signed-off-by: Idwer Vollering <> Acked-by: Uwe Hermann <>
* Various cosmetic and coding-style fixesUwe Hermann2010-08-081-5/+5
| | | | | | | | | | | | | | | | | | | | | - Fix incorrect whitespace, indentation, and coding style in some places. - Drop '/**' Doxygen comments, we don't use Doxygen. Even if we would use it, the comments are useless as we don't have any Doxygen markup in there. - Use consistent vendor name spelling as per current website (NVIDIA, abit, GIGABYTE). - Use consistent / common format for "Suited for:" lines in board_enable.c. - Add some missing 'void's in functions taking no arguments. - Add missing fullstops in sentences, remove them from non-sentences (lists). Corresponding to flashrom svn r1134. Signed-off-by: Uwe Hermann <> Acked-by: Uwe Hermann <>
* Add support for the Amontec JTAGkey2Jörg Fischer2010-07-291-2/+11
| | | | | | | | | | | | | | | | | | | | | | Add support for the Amontec JTAGkey2, see This FTDI 2232H variant has an additional output enable, which will be set to its "on" (L) when CS is pulled low. But it lacks a power supply and you need an external 3.3V source. The attached patch adds "jtagkey" as "type" parameter for ft2232_spi. It should work with all JTAGkeys (JTAGkey, JTAGkey-tiny and JTAGkey2) but I only have a JTAGkey2 here for testing. Add all FT2232H/FT4232H based programmers to the list printed with flashrom -L Corresponding to flashrom svn r1119. Signed-off-by: Jörg Fischer <> Acked-by: Carl-Daniel Hailfinger <>
* Add Nvidia nForce MCP61/MCP65/MCP67/MCP78S/MCP73/MCP79 SPI flashing supportCarl-Daniel Hailfinger2010-07-281-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Huge thanks go to Michael Karcher for reverse engineering the interface and to Johannes Sjölund for testing the first iterations of my patch on his hardware until it worked. Thanks to the following testers of the patch: * MCP61, 10de:03e0, LPC OK, ECS Geforce6100SM-M, Andrew Cleveland * MCP61, 10de:03e0, LPC OK, Biostar NF520-A2 NF61D-A2, Vitaliy Buchynskyy * MCP65, 10de:0441, SPI OK, MSI MS-7369 K9N Neo-F v2, Kjell Braden * MCP65, 10de:0441, SPI OK, MSI MS-7369, Wolfgang Schnitker * MCP65, 10de:0441, SPI OK, MSI MS-7369, Johannes Sjölund * MCP65, 10de:0441, SPI OK, MSI MS-7369, Melchior Franz * MCP78S, 10de:075c, SPI OK, Asus M3N78 PRO, Brad Rogers * MCP78S, 10de:075c, SPI OK, Asus M3N78-VM, Marcel Partap * MCP78S, 10de:075c, SPI OK, Asus M4N78 PRO, Kimmo Vuorinen * MCP78S, 10de:075c, SPI OK, Asus M4N78 PRO, Vikram Ambrose * MCP79, 10de:0aad, SPI OK, Acer Aspire R3600, Andrew Morgan * MCP79, 10de:0aae, LPC ??, Lenovo Ideapad S12 laptop, Christian Schmitt * MCP79, 10de:0aae, SPI OK, Apple iMac9,1 Mac-F2218EA9, David "dledson" flashrom will refuse to write/erase for safety reasons if MCP6x/MCP7x SPI is detected. Corresponding to flashrom svn r1113. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Uwe Hermann <>
* Split off programmer.h from flash.hCarl-Daniel Hailfinger2010-07-271-0/+558
Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h header from coreboot, internal programmer only spi.h SPI command definitions Corresponding to flashrom svn r1112. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Uwe Hermann <>
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