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SPI bitbanging on devices which speak SPI natively has a dual-use
problem: We need to shut down normal SPI operations to do the bitbanging
ourselves. Once we're done, it makes a lot of sense to reenable "normal"
SPI operations again. Add request_bus/release_bus functions to struct
bitbang_spi_master.
Add a bitbang shutdown function (not used yet).
Change MCP SPI and Intel NIC SPI to use the new request/release bus
infrastructure.
Cosmetic changes to a few error messages (80 column limit).
There are multiple possible strategies for bus request/release:
- Request at the start of a SPI command, release immediately afterwards.
- Request at the start of a SPI multicommand, release once all commands
of the multicommand are done.
- Request on programmer init, release on shutdown.
Each strategy has its own advantages. For now, we will stay with the
first strategy which worked fine so far.
Corresponding to flashrom svn r1171.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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- Fix incorrect whitespace, indentation, and coding style in some places.
- Drop '/**' Doxygen comments, we don't use Doxygen. Even if we would use
it, the comments are useless as we don't have any Doxygen markup in there.
- Use consistent vendor name spelling as per current website (NVIDIA,
abit, GIGABYTE).
- Use consistent / common format for "Suited for:" lines in board_enable.c.
- Add some missing 'void's in functions taking no arguments.
- Add missing fullstops in sentences, remove them from non-sentences (lists).
Corresponding to flashrom svn r1134.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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Huge thanks go to Michael Karcher for reverse engineering the interface
and to Johannes Sjölund for testing the first iterations of my patch on
his hardware until it worked.
Thanks to the following testers of the patch:
* MCP61, 10de:03e0, LPC OK, ECS Geforce6100SM-M, Andrew Cleveland
* MCP61, 10de:03e0, LPC OK, Biostar NF520-A2 NF61D-A2, Vitaliy Buchynskyy
* MCP65, 10de:0441, SPI OK, MSI MS-7369 K9N Neo-F v2, Kjell Braden
* MCP65, 10de:0441, SPI OK, MSI MS-7369, Wolfgang Schnitker
* MCP65, 10de:0441, SPI OK, MSI MS-7369, Johannes Sjölund
* MCP65, 10de:0441, SPI OK, MSI MS-7369, Melchior Franz
* MCP78S, 10de:075c, SPI OK, Asus M3N78 PRO, Brad Rogers
* MCP78S, 10de:075c, SPI OK, Asus M3N78-VM, Marcel Partap
* MCP78S, 10de:075c, SPI OK, Asus M4N78 PRO, Kimmo Vuorinen
* MCP78S, 10de:075c, SPI OK, Asus M4N78 PRO, Vikram Ambrose
* MCP79, 10de:0aad, SPI OK, Acer Aspire R3600, Andrew Morgan
* MCP79, 10de:0aae, LPC ??, Lenovo Ideapad S12 laptop, Christian Schmitt
* MCP79, 10de:0aae, SPI OK, Apple iMac9,1 Mac-F2218EA9, David "dledson"
flashrom will refuse to write/erase for safety reasons if MCP6x/MCP7x
SPI is detected.
Corresponding to flashrom svn r1113.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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