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* Add ICH opcode debuggingPeter Stuge2009-01-151-0/+1
| | | | | | | Corresponding to flashrom svn r383 and coreboot v2 svn r3862. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Various ichspi.c refinementsFENG yu ning2008-12-151-27/+30
| | | | | | | | | | | | | | | | | | | | * add a generic preop-opcode-pair table. * rename ich_check_opcodes to ich_init_opcodes. * let ich_init_opcodes do not need to access flashchip structure: . move the definition of struct preop_opcode_pair to a better place . remove preop_opcode_pairs from 'struct flashchip' . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure * call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works. * fix a coding style mistake. Corresponding to flashrom svn r367 and coreboot v2 svn r3814. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI ↵FENG yu ning2008-12-081-0/+134
| | | | | | | | | configuration is locked down Corresponding to flashrom svn r364 and coreboot v2 svn r3805. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* ichspi: use spi_nbyte_read() instead of running the opcode directlyCarl-Daniel Hailfinger2008-11-181-9/+5
| | | | | | | | | | | | | | Currently flashrom assumes every vendor BIOS shares our view about which SPI opcodes should be placed in which location. Move to a less optimistic implementation and actually use the generic SPI read functions. They're useful for abstracting exactly this stuff and that makes them the preferred choice. Corresponding to flashrom svn r346 and coreboot v2 svn r3758. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add additional SPI sector erase and chip erase command functionsCarl-Daniel Hailfinger2008-11-031-16/+5
| | | | | | | | | | | | | | | | | | | Not all chips support all commands, so allow the implementer to select the matching function. Fix a layering violation in ICH SPI code to be less bad. Still not perfect, but the new code is shorter, more generic and architecturally more sound. TODO (in a separate patch): - move the generic sector erase code to spi.c - decide which erase command to use based on info about the chip - create a generic spi_erase_all_sectors function which calls the generic sector erase function Thanks to Stefan for reviewing and commenting. Corresponding to flashrom svn r337 and coreboot v2 svn r3722. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Drop nr/opcode_index parameter from run_opcode and search the opmenu for the ↵Stefan Reinauer2008-11-021-15/+45
| | | | | | | | | | | | opcode instead This is slightly slower (ha, ha), but works on boards with a locked opmenu. Tested on ICH7 and works. Corresponding to flashrom svn r336 and coreboot v2 svn r3721. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Coding-style fixes for flashrom, partly indent-aidedUwe Hermann2008-10-181-12/+12
| | | | | | | Corresponding to flashrom svn r326 and coreboot v2 svn r3669. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Trivial indent fix in ichspi.cPeter Stuge2008-07-071-3/+3
| | | | | | | Corresponding to flashrom svn r301 and coreboot v2 svn r3417. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* First attempt to clean up SPI probing and create a common construct: the ↵Stefan Reinauer2008-06-301-53/+54
| | | | | | | | | | | | | | | | | | flash bus At some point the flash bus will be part of struct flashchip. Pardon me for pushing this in, but I think it is important to beware of further decay and it will improve things for other developers in the short run. Carl-Daniel, I will consider your suggestions in another patch. I want to keep things from getting too much for now. The patch includes Rudolf's VIA SPI changes though. Corresponding to flashrom svn r285 and coreboot v2 svn r3401. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* This patch adds support for VIA SPI controller on VT8237SRudolf Marek2008-06-301-26/+44
| | | | | | | | | It is similar with few documented exceptions to ICH7 SPI controller. Corresponding to flashrom svn r282 and coreboot v2 svn r3398. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se>
* Add a debug marker after ICH SPI opcode programmingCarl-Daniel Hailfinger2008-06-291-1/+2
| | | | | | | Corresponding to flashrom svn r281 and coreboot v2 svn r3397. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Fix ICH7 non-SPI that broke in r3393Peter Stuge2008-06-291-1/+1
| | | | | | | | | | | | r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back to 0 when BOOT BIOS Straps indicate something else than SPI. Also fixes a build error in ichspi.c with gcc 4.2.2. Corresponding to flashrom svn r280 and coreboot v2 svn r3395. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Multiple unrelated changesStefan Reinauer2008-06-271-41/+211
| | | | | | | | | | | | * ICH7 SPI support * fix some variable names in ichspi.c (Offset -> offset) * Dump ICH7 SPI bar with -V * Improve error message in case IOPL goes wrong. (It might not even be an IOPL) Corresponding to flashrom svn r278 and coreboot v2 svn r3393. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se>
* Indent according to development guidelinesStefan Reinauer2008-06-271-48/+40
| | | | | | | Corresponding to flashrom svn r277 and coreboot v2 svn r3392. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add support for SPI chips on ICH9Dominik Geyer2008-05-161-0/+468
This is done by using the generic SPI interface. Corresponding to flashrom svn r239 and coreboot v2 svn r3325. Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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