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path: root/chipset_enable.c
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* Fix decoding of SB600 LPC ROM protection registersMathias Krause2011-01-011-6/+6
* Revert PCI config space writes on shutdownCarl-Daniel Hailfinger2010-11-101-45/+33
* Refine text of requests to send logsPaul Menzel2010-10-081-3/+8
* Remove duplicate includes from the codeStefan Reinauer2010-10-061-1/+0
* Add a board-enable for the ASRock K7S41, chipset-enable for SiS 741Uwe Hermann2010-10-051-0/+1
* Add chipset enable for Broadcom OSB4Joshua Roys2010-09-151-0/+18
* Add a board enable for MSI MS-6561 (745 Ultra)Mattias Mattsson2010-09-111-1/+1
* Add support for Intel 5 Series / 3400 Series chipsetsHelge Wagner2010-08-111-0/+14
* Various cosmetic and coding-style fixesUwe Hermann2010-08-081-3/+3
* Add support for SIS661 (SIS963)David Borg2010-07-311-0/+1
* Add Nvidia nForce MCP61/MCP65/MCP67/MCP78S/MCP73/MCP79 SPI flashing supportCarl-Daniel Hailfinger2010-07-281-146/+39
* Split off programmer.h from flash.hCarl-Daniel Hailfinger2010-07-271-0/+1
* Convert MMIO accesses of non-internal PCI-based programmers to be endian-agno...Carl-Daniel Hailfinger2010-07-271-2/+2
* Move SB600 SPI initialization to sb600spi.cMichael Karcher2010-07-221-77/+5
* Move Intel SPI initialisation to ichspi.cMichael Karcher2010-07-221-200/+18
* Fix out-of-bounds ICH FREG permission printingCarl-Daniel Hailfinger2010-07-131-3/+4
* Unify programmer parameter extractionCarl-Daniel Hailfinger2010-07-081-1/+1
* Various places in the flashrom source feature custom parameter extraction fro...Carl-Daniel Hailfinger2010-07-061-5/+10
* Kill global variables, constants and functions if local scope sufficesCarl-Daniel Hailfinger2010-07-031-30/+30
* ICH9/10: display FRAP/FREGx access controlsJoshua Roys2010-07-011-15/+47
* Kill unneeded #include wherever possibleCarl-Daniel Hailfinger2010-06-211-3/+1
* Fill in buses_supported for remaining Intel chipsets (ICH0-ICH5, Poulsbo)Carl-Daniel Hailfinger2010-06-201-0/+2
* VIA: disable byte mergingMichael Karcher2010-06-131-7/+52
* Board-enable for MS-7025 (K8N Neo2 Platinum)Michael Karcher2010-06-121-0/+1
* Remove unneeded #include statements completelyCarl-Daniel Hailfinger2010-05-301-0/+1
* ichspi: try harder to conform to address restrictionsCarl-Daniel Hailfinger2010-05-281-4/+4
* Handle the following architectures in generic flashrom codeCarl-Daniel Hailfinger2010-05-261-1/+6
* Print found PCI IDs during chipset detectionCarl-Daniel Hailfinger2010-05-221-0/+3
* Disable probing for one variant of MCP55 to enable Tyan S2915Carl-Daniel Hailfinger2010-05-221-1/+9
* Convert various prints to use msg_p* and msg_g* respectivelySean Nelson2010-05-071-108/+108
* Rename identifiers called 'byte'Michael Karcher2010-02-251-14/+14
* Refactor MCP SPI detectionCarl-Daniel Hailfinger2010-02-181-54/+101
* Add SPI mode diagnostics for all post-MCP55 (nForce 5) chipsets from NvidiaCarl-Daniel Hailfinger2010-02-131-1/+137
* Add Intel NM10 chipset enableDavid Hendricks2010-01-191-0/+1
* Don't use "byte" as identifierMichael Karcher2010-01-121-11/+11
* Chipset: Fix sis5x0 register write verificationLuc Verhaegen2010-01-101-13/+3
* Fix Intel FWH decode sizeMichael Karcher2010-01-031-2/+2
* Add VIA VT8233A identification, mark as testedRaúl Soriano2009-12-231-0/+1
* Chipset/Board: vt8237: Set All mem cycles to LPC in chipset enableLuc Verhaegen2009-12-231-0/+7
* Chipset: Add support for Intel Poulsbo chipsetAdam Jurkowski2009-12-211-0/+22
* Use the maximum decode size infrastructureCarl-Daniel Hailfinger2009-12-171-27/+96
* Internal (onboard) programming was the only feature which could not be disabledCarl-Daniel Hailfinger2009-12-131-21/+0
* Chipset: remove sis630 chipset enable for sis540Luc Verhaegen2009-12-091-51/+17
* Intel PIIX* chipsets only support parallel flash (no LPC/FWH/SPI)Maciej Pijanka2009-12-081-0/+2
* Add support for Intel 3400 series / 5 series chipsetCarl-Daniel Hailfinger2009-11-261-0/+3
* Mark Elitegroup K7S5A as supportedCarl-Daniel Hailfinger2009-11-151-28/+28
* Add support for every single SiS chipset out thereCarl-Daniel Hailfinger2009-11-151-67/+200
* Add infrastructure to check the maximum supported flash size of chipsets and ...Carl-Daniel Hailfinger2009-10-311-0/+11
* Mark NVIDIA Nforce4/MCP04 as testedLuc Verhaegen2009-10-061-1/+1
* Chipset support for the nVidia nForce 4Luc Verhaegen2009-10-051-0/+1
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