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* The VIA VX800 chipset works with the VT8237S code after adding an entry for ↵Arjan Koers2009-06-151-0/+1
| | | | | | | | | | the VX800 PCI ID Corresponding to flashrom svn r591. Signed-off-by: Arjan Koers <0h3q2rmn2bdb@list.nospam.xutrox.com> Acked-by: Bari Ari <bari@onelabs.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Mark 3COM "3C905B: Cyclone 10/100/BNC" as fully testedUwe Hermann2009-06-021-6/+6
| | | | | | | | | Also do some random cleanups while I'm at it. Corresponding to flashrom svn r567. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Only probe for chips with compatible bus protocolsCarl-Daniel Hailfinger2009-06-011-6/+17
| | | | | | | | | | | | | | | | | | It doesn't make sense to probe for SPI chips on a LPC host, nor does it make sense to probe for LPC chips on a Parallel host. This change is backwards compatible, but adding host protocol info to chipset init functions will speed up probing. Once all chipset init functions are updated and the Winbond W29EE011 and AMIC A49LF040A chip definitions are updated, the W29EE011 workaround can be deleted as the W29/A49 conflict magically disappears. Corresponding to flashrom svn r560. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested on real hardware and Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add bus type annotation to struct flashchipsCarl-Daniel Hailfinger2009-05-311-10/+9
| | | | | | | | | | | | | | | | | | | Right now, the annotation only differentiates between SPI and non-SPI. Anyone who knows more about a specific flash chip should feel free to update it. The existing flashbus variable was abused to denote the SPI controller type. Use an aptly named variable for that purpose. Once this patch is merged, the chipset/programmer init functions can set supported flash chip types and flashrom can automatically select only matching probe/read/erase/write functions. A side benefit of that will be the elimination of the Winbond W29EE011 vs. AMIC A49LF040A conflict. Corresponding to flashrom svn r556. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add NForce2 chipset enableLuc Verhaegen2009-05-261-0/+14
| | | | | | | | | | | | | While the other chipset enables for nvidia could potentially also work, this one, by not touching other bits, seems like the safest solution. Uwe tested this on his Asus A7N8X Deluxe, so hopefully the A7N8X-E (reporter unknown) is now no longer an issue. Corresponding to flashrom svn r548. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* A bunch of output beautifications and improvements, as well as doc fixesUwe Hermann2009-05-221-10/+16
| | | | | | | | | | | | | | | | | | | | | | | - Update manpage, we now report supported boards via -L. - Add some missing escaping for '-' characters in the manpage. Corresponding to flashrom svn r543. - Shorten some of the really long device names, so that -L output looks nicer. - Display a "table header" for all entries/columns in -L output. - Make -L output tabular for all lists for better readability. - Do not print "unknown XXXX SPI chip" entries in -L output. - And random other cosmetics... Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
* Use accessor functions for MMIOCarl-Daniel Hailfinger2009-05-171-35/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some MMIO accesses used volatile, others didn't (and risked non-execution of side effects) and even with volatile, some accesses looked dubious. Since the MMIO accessor functions and the onboard flash accessor functions are functionally identical (but have different signatures), make the flash accessors wrappers for the MMIO accessors. For some of the conversions, I used Coccinelle. Semantic patch follows: @@ typedef uint8_t; expression a; volatile uint8_t *b; @@ - b[a] + *(b + a) @@ expression a; volatile uint8_t *b; @@ - *(b) |= (a); + *(b) = *(b) | (a); @@ expression a; volatile uint8_t *b; @@ - *(b) = (a); + mmio_writeb(a, b); @@ volatile uint8_t *b; @@ - *(b) + mmio_readb(b) @@ type T; T b; @@ ( mmio_readb | mmio_writeb ) (..., - (T) - (b) + b ) Corresponding to flashrom svn r524. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Uwe tested read, write, erase with this patch on a random board to make sure nothing breaks. Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* List all boards which areUwe Hermann2009-05-161-19/+17
| | | | | | | | | | | | | | - Supported out of the box (no flash enables required) - Verifiably not yet working (unknown flash enable) Also, move some structs to flash.h in preparation for later wiki output support. Corresponding to flashrom svn r523. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Drop unused/duplicated #includes and some dead codeUwe Hermann2009-05-161-3/+0
| | | | | | | | | Build-tested on 32bit x86. Corresponding to flashrom svn r521. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Uwe tested the recent SB600 SPI commit and notified me of one unexpected problemCarl-Daniel Hailfinger2009-05-151-1/+25
| | | | | | | | | | | | It seems some boards do not use SPI_HOLD at all. Take that into account when trying to figure out if SPI is available. Print the SB600 ROM strap override register status for better debugging. Corresponding to flashrom svn r516. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Create a SB600 SPI detection heuristicCarl-Daniel Hailfinger2009-05-101-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | I know that the data sheets say we can't read the ROM straps, but creative interpretation of the data sheets yielded a heuristic which should work pretty well. NOTE: If you test this, make sure you power down and _unplug_ the machine for a few minutes before you boot and run flashrom with this patch. If the machine is not unplugged for some time, the test will yield incorrect results. If you run a slightly older flashrom version than svn HEAD, the test will yield incorrect results. If you run any flashrom version (except svn HEAD plus this patch) after poweron, the test will yield incorrect results. Explanation: Older flashrom versions unconditionally write to registers which are used for this heuristic. These registers are in the S5 power domain, so even powering down does not clear them, you really have to unplug the machine and remove the battery if this is a laptop. Corresponding to flashrom svn r491. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Make chipset list alphabetically ordered as the other listsUwe Hermann2009-05-081-39/+40
| | | | | | | Corresponding to flashrom svn r477. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Store and display chipset test status (not only chip status)Uwe Hermann2009-05-071-83/+91
| | | | | | | | | | | | The list of tested chipsets is synced from the wiki. Also, split the chipset vendor and name into two fields for easier wiki-syntax output later. Corresponding to flashrom svn r472. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Clarify error message in enable_flash_sb600() a littlePeter Stuge2009-05-061-1/+1
| | | | | | | Corresponding to flashrom svn r469. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Revert r466 because of inverted logicCarl-Daniel Hailfinger2009-05-061-5/+6
| | | | | | | | | If unprotect succeeded, it will print "SB600 unprotect failed". Corresponding to flashrom svn r467. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Cleanup redundant condition and clarify message a littlePeter Stuge2009-05-061-6/+5
| | | | | | | Corresponding to flashrom svn r466. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Touch up some error messages in enable_flash_cs5536()Peter Stuge2009-05-061-2/+2
| | | | | | | Corresponding to flashrom svn r465. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Clean up the SB400 chipset enable codeCarl-Daniel Hailfinger2009-05-061-9/+1
| | | | | | | | | | Use pci_dev_find() instead of setting up a filter and iterating over PCI devices. Corresponding to flashrom svn r464. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Rewrite the SB600 chipset enable functionCarl-Daniel Hailfinger2009-05-051-17/+33
| | | | | | | | | | | | | | | | - Check for read/write protected regions first. - Region protection is write-once according to the data sheets. Check if the write succeeded. Don't write if the region is not protected. - Verbose region protection dumping. - Improve readability of BAR mapping code. - Align BAR mapping to a page boundary (4k) instead of a 16k boundary. This patch prepares the code for a SPI detection heuristic. Corresponding to flashrom svn r463. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se>
* Here is a fix for chipset_enable.c when there is not /dev/cpuBertrand Jacquin2009-05-051-1/+1
| | | | | | | | | | Open fails so there is no reason to lseek in. Actually this is a trivial fix for a bad return value from open. Corresponding to flashrom svn r462. Signed-off-by: Bertrand Jacquin <beber@meleeweb.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com>
* Force enabling SPI mode for SB600 is a bad idea and leads to hangsZheng Bao2009-05-041-0/+8
| | | | | | | | | | | | Only access LPC ROM if we boot via LPC ROM. Only access SPI ROM if we boot via SPI ROM. The code to force enable SPI is commented out in case someone wants to reenable it for a particular board with LPC and SPI flash. Corresponding to flashrom svn r459. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Some coding style and consistency fixesUwe Hermann2009-04-151-1/+1
| | | | | | | Corresponding to flashrom svn r429 and coreboot v2 svn r4117. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Following patch fixes VIA SPI (VT8237S)Rudolf Marek2009-02-011-0/+1
| | | | | | | | | It needs to have opcodes initialized same way as ICH7. Corresponding to flashrom svn r413 and coreboot v2 svn r3926. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se>
* Add VT8237A PCI IDPeter Stuge2009-01-261-0/+1
| | | | | | | Corresponding to flashrom svn r411 and coreboot v2 svn r3919. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Abstract mmap() in physmap.c and only open /dev/mem on the first physmap() callStefan Reinauer2009-01-261-30/+4
| | | | | | | | Corresponding to flashrom svn r397 and coreboot v2 svn r3903. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Check all mmap() calls and print helpful Linux error messagePeter Stuge2009-01-231-0/+4
| | | | | | | Corresponding to flashrom svn r386 and coreboot v2 svn r3890. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Fix ICH9 locking register address and add important debug outputFENG yu ning2009-01-181-12/+26
| | | | | | | | Corresponding to flashrom svn r384 and coreboot v2 svn r3869. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: FENG yu ning <fengyuning1984@gmail.com>
* Add AMD-768 chipset supportSven Schnelle2009-01-071-0/+1
| | | | | | | Corresponding to flashrom svn r372 and coreboot v2 svn r3849. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add i631x LPC supportSven Schnelle2009-01-071-0/+1
| | | | | | | Corresponding to flashrom svn r371 and coreboot v2 svn r3848. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Initialize ICH SPI opcodes also for ICH9 and laterPeter Stuge2008-12-221-0/+1
| | | | | | | Corresponding to flashrom svn r368 and coreboot v2 svn r3830. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Various ichspi.c refinementsFENG yu ning2008-12-151-0/+1
| | | | | | | | | | | | | | | | | | | | * add a generic preop-opcode-pair table. * rename ich_check_opcodes to ich_init_opcodes. * let ich_init_opcodes do not need to access flashchip structure: . move the definition of struct preop_opcode_pair to a better place . remove preop_opcode_pairs from 'struct flashchip' . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure * call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works. * fix a coding style mistake. Corresponding to flashrom svn r367 and coreboot v2 svn r3814. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI ↵FENG yu ning2008-12-081-0/+3
| | | | | | | | | configuration is locked down Corresponding to flashrom svn r364 and coreboot v2 svn r3805. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add AMD SB700 flash enableNiels Ole Salscheider2008-12-051-0/+1
| | | | | | | | | | | This patch adds SB700 support to flashrom. The code for enabling the flash rom is the same as for SB600. It was tested (read, write, verify) with an ASUS M3A-H/HDMI which contains a Macronix MX25L8005. Corresponding to flashrom svn r361 and coreboot v2 svn r3799. Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Acked-by: Peter Stuge <peter@stuge.se>
* Replace #ifdefs for sc520 systems by run time probingStefan Reinauer2008-12-031-0/+56
| | | | | | | | | | Fixes #109 Corresponding to flashrom svn r355 and coreboot v2 svn r3790. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for the AMD/ATI SB600 southbridge SPI functionalityJason Wang2008-11-281-10/+25
| | | | | | | | | | This has been tested by Uwe Hermann on an RS690/SB600 board. Corresponding to flashrom svn r351 and coreboot v2 svn r3779. Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Dump ICH8/ICH9/ICH10 SPI registersCarl-Daniel Hailfinger2008-11-031-5/+45
| | | | | | | | | This helps a lot if we have to track down configuration weirdnesses. Corresponding to flashrom svn r338 and coreboot v2 svn r3723. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Enable SPI boot flash support on EP80579, which has the ICH7 register setEd Swierk2008-10-291-1/+1
| | | | | | | Corresponding to flashrom svn r332 and coreboot v2 svn r3706. Signed-off-by: Ed Swierk <eswierk@aristanetworks.com> Acked-by: Ed Swierk <eswierk@aristanetworks.com>
* Add support for the Intel 82371MX (MPIIX) southbridgeUwe Hermann2008-10-281-3/+5
| | | | | | | | | | Untested, but should work just as well as the other *PIIX* southbridges according to the datasheets. Corresponding to flashrom svn r330 and coreboot v2 svn r3696. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridgesUwe Hermann2008-10-261-1/+7
| | | | | | | | | Tested on PIIX3 hardware. Corresponding to flashrom svn r329 and coreboot v2 svn r3694. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com>
* Add support for the VIA VT82C586A/B chipset, improve documentationUwe Hermann2008-10-251-1/+4
| | | | | | | Corresponding to flashrom svn r328 and coreboot v2 svn r3693. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Coding-style fixes for flashrom, partly indent-aidedUwe Hermann2008-10-181-48/+61
| | | | | | | Corresponding to flashrom svn r326 and coreboot v2 svn r3669. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Allow the SiS 620 chipset to detect and read at least 256kb chipsUrja Rannikko2008-10-181-0/+11
| | | | | | | | | | Based on the 5595 datasheet and uniflash 1.40 sources, only looking for info about SiS620. Corresponding to flashrom svn r325 and coreboot v2 svn r3668. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* SB600 has four write once LPC ROM protect areasMarc Jones2008-10-151-0/+21
| | | | | | | | | | | | It is not possible to write enable that area once the register is set so print a warning. Corresponding to flashrom svn r324 and coreboot v2 svn r3659. Signed-off-by: Marc Jones <marcj.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add ICH10 supportCarl-Daniel Hailfinger2008-10-101-0/+10
| | | | | | | | | | The ICH9 and ICH10 data sheets are identical regarding FWH/SPI flash interfaces, so this just adds the required PCI IDs. Corresponding to flashrom svn r323 and coreboot v2 svn r3648. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se>
* Recognize the Intel EP80579 LPC flash interfaceEd Swierk2008-08-201-0/+1
| | | | | | | Corresponding to flashrom svn r310 and coreboot v2 svn r3532. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Adding support for flashing system with Nvidia MCP67Stefan Reinauer2008-07-051-0/+1
| | | | | | | Corresponding to flashrom svn r298 and coreboot v2 svn r3414. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* First attempt to clean up SPI probing and create a common construct: the ↵Stefan Reinauer2008-06-301-49/+95
| | | | | | | | | | | | | | | | | | flash bus At some point the flash bus will be part of struct flashchip. Pardon me for pushing this in, but I think it is important to beware of further decay and it will improve things for other developers in the short run. Carl-Daniel, I will consider your suggestions in another patch. I want to keep things from getting too much for now. The patch includes Rudolf's VIA SPI changes though. Corresponding to flashrom svn r285 and coreboot v2 svn r3401. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* This patch adds support for VIA SPI controller on VT8237SRudolf Marek2008-06-301-0/+20
| | | | | | | | | It is similar with few documented exceptions to ICH7 SPI controller. Corresponding to flashrom svn r282 and coreboot v2 svn r3398. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se>
* Fix ICH7 non-SPI that broke in r3393Peter Stuge2008-06-291-0/+2
| | | | | | | | | | | | r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back to 0 when BOOT BIOS Straps indicate something else than SPI. Also fixes a build error in ichspi.c with gcc 4.2.2. Corresponding to flashrom svn r280 and coreboot v2 svn r3395. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Multiple unrelated changesStefan Reinauer2008-06-271-4/+41
| | | | | | | | | | | | * ICH7 SPI support * fix some variable names in ichspi.c (Offset -> offset) * Dump ICH7 SPI bar with -V * Improve error message in case IOPL goes wrong. (It might not even be an IOPL) Corresponding to flashrom svn r278 and coreboot v2 svn r3393. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se>
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