summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Fix stupid off-by-one error in erase verificationPeter Stuge2009-01-251-1/+1
| | | | | | | | | As reported by Jody McIntyre. Thanks! Corresponding to flashrom svn r389 and coreboot v2 svn r3894. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* ST M50FW080 TEST_OK_ PROBE READ ERASE WRITEPeter Stuge2009-01-241-1/+1
| | | | | | | | | Report by Jody McIntyre. Thanks! Corresponding to flashrom svn r388 and coreboot v2 svn r3893. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* SST25VF080B TEST_OK_PROBEPeter Stuge2009-01-241-1/+1
| | | | | | | | | Report by Scaldov M.V. Thanks! Corresponding to flashrom svn r387 and coreboot v2 svn r3892. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Check all mmap() calls and print helpful Linux error messagePeter Stuge2009-01-234-7/+19
| | | | | | | Corresponding to flashrom svn r386 and coreboot v2 svn r3890. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Provide some hints for the user in case /dev/mem mmap failsPeter Stuge2009-01-221-0/+7
| | | | | | | | | Resolves #121 Corresponding to flashrom svn r385 and coreboot v2 svn r3889. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Fix ICH9 locking register address and add important debug outputFENG yu ning2009-01-181-12/+26
| | | | | | | | Corresponding to flashrom svn r384 and coreboot v2 svn r3869. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: FENG yu ning <fengyuning1984@gmail.com>
* Add ICH opcode debuggingPeter Stuge2009-01-151-0/+1
| | | | | | | Corresponding to flashrom svn r383 and coreboot v2 svn r3862. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Use designated initializers for the board enable tableStephan Guilloux2009-01-151-51/+362
| | | | | | | | | | | | | | | | | | | Similarly to flashchips array, this patch intends to make the table board_pciid_enables more readable. Corresponding to flashrom svn r382 and coreboot v2 svn r3861. Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> > What real problem does this solve? 1. Next time someone adds a new struct member, we avoid mistakes of ordering of initializers 2. we avoid mistakes in the first place. The .x = y stuff was added for a (good) reason, I think this is an improvement. Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Always print address when verification fails, not only with -VPeter Stuge2009-01-131-4/+5
| | | | | | | Corresponding to flashrom svn r381 and coreboot v2 svn r3860. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Board enable for GIGABYTE GA-MA78G-DS3HPeter Stuge2009-01-121-0/+2
| | | | | | | | | | | This board has 2x MX25L8005 flash chips behind an IT8718F LPC->SPI bridge. The board uses GIGABYTE's patented BIOS failover technology, and at this point we do not know how to control which of the two chips flashrom actually hits. Corresponding to flashrom svn r380 and coreboot v2 svn r3859. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Yul Rottmann <yulrottmann@bitel.net>
* IT8718F works just like IT8716FPeter Stuge2009-01-121-1/+1
| | | | | | | Corresponding to flashrom svn r379 and coreboot v2 svn r3858. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Yul Rottmann <yulrottmann@bitel.net>
* Check return value of fscanf()/fwrite()/fread()Peter Stuge2009-01-122-9/+15
| | | | | | | | | Fix build error on distros with warn_unused_result attributes in glibc. Corresponding to flashrom svn r378 and coreboot v2 svn r3857. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Yul Rottmann <yulrottmann@bitel.net>
* Update usage in READMEIdwer Vollering2009-01-111-1/+4
| | | | | | | | | Mimicked from flashrom.c Corresponding to flashrom svn r377 and coreboot v2 svn r3855. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* Add erase and write functions to the following chip definitionsCarl-Daniel Hailfinger2009-01-081-27/+27
| | | | | | | | | | | | | AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 Straight from the data sheets, untested because I lack the hardware. Corresponding to flashrom svn r376 and coreboot v2 svn r3853. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se>
* The flashrom man page has incomplete author/copyright sections and an ↵Carl-Daniel Hailfinger2009-01-081-9/+37
| | | | | | | | | | | | | | | | incorrect license section - Remove the copyright listings and refer the reader to the source files. - Update the author list to those which have copyright messages in the source files. - Correct the license from GPL v2+ to (GPL v2, with some files under later versions as well) Corresponding to flashrom svn r375 and coreboot v2 svn r3852. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* This patch improves machine parseability and human readability of flashchips.cStephan Guilloux2009-01-081-925/+2087
| | | | | | | | | | | The explicit initialization makes sure any future struct flashchip reordering is not needed. (Except for the case where we need arrays of some of the struct members.) Corresponding to flashrom svn r374 and coreboot v2 svn r3851. Signed-off-by: Stephan Guilloux <mailto:stephan.guilloux@free.fr> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add SST49LF020 supportSven Schnelle2009-01-072-0/+7
| | | | | | | Corresponding to flashrom svn r373 and coreboot v2 svn r3850. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add AMD-768 chipset supportSven Schnelle2009-01-071-0/+1
| | | | | | | Corresponding to flashrom svn r372 and coreboot v2 svn r3849. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add i631x LPC supportSven Schnelle2009-01-071-0/+1
| | | | | | | Corresponding to flashrom svn r371 and coreboot v2 svn r3848. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* If you pass a bogus layout file to the -l option flashrom will segfaultUwe Hermann2008-12-221-0/+5
| | | | | | | | | | Fix that by throwing an error instead. Corresponding to flashrom svn r370 and coreboot v2 svn r3834. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se>
* Add another board-enable line for the Kontron 986LCD-M/mITXUwe Hermann2008-12-221-0/+3
| | | | | | | | | | | | There seem to be at least two versions of the board out there, and the subsystem IDs changed between the versions. Patch successfully tested on hardware. Corresponding to flashrom svn r369 and coreboot v2 svn r3833. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se>
* Initialize ICH SPI opcodes also for ICH9 and laterPeter Stuge2008-12-221-0/+1
| | | | | | | Corresponding to flashrom svn r368 and coreboot v2 svn r3830. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Various ichspi.c refinementsFENG yu ning2008-12-153-35/+32
| | | | | | | | | | | | | | | | | | | | * add a generic preop-opcode-pair table. * rename ich_check_opcodes to ich_init_opcodes. * let ich_init_opcodes do not need to access flashchip structure: . move the definition of struct preop_opcode_pair to a better place . remove preop_opcode_pairs from 'struct flashchip' . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure * call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works. * fix a coding style mistake. Corresponding to flashrom svn r367 and coreboot v2 svn r3814. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* Add 28 flash chips of the MX29 series to the flashrom ID table and support ↵Carl-Daniel Hailfinger2008-12-102-0/+34
| | | | | | | | | | | the MX29LV040C MX29LV040C probe and read support tested by khetzal on IRC. Corresponding to flashrom svn r366 and coreboot v2 svn r3809. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Kill obsolete and misplaced commentCarl-Daniel Hailfinger2008-12-081-1/+1
| | | | | | | Corresponding to flashrom svn r365 and coreboot v2 svn r3806. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI ↵FENG yu ning2008-12-083-0/+145
| | | | | | | | | configuration is locked down Corresponding to flashrom svn r364 and coreboot v2 svn r3805. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Breaks chip info into multiple linesFENG yu ning2008-12-081-160/+937
| | | | | | | Corresponding to flashrom svn r363 and coreboot v2 svn r3804. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Display test status in -L chip listingPeter Stuge2008-12-061-4/+51
| | | | | | | | | | | | | | | | | | Looks like this: Supported flash chips: Tested OK operations: Known BAD operations: AMD Am29F002(N)BB AMD Am29F002(N)BT PROBE READ ERASE WRITE AMD Am29F016D AMD Am29F040B PROBE READ ERASE WRITE AMD Am29LV040B Atmel AT45CS1282 READ Corresponding to flashrom svn r362 and coreboot v2 svn r3803. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add AMD SB700 flash enableNiels Ole Salscheider2008-12-051-0/+1
| | | | | | | | | | | This patch adds SB700 support to flashrom. The code for enabling the flash rom is the same as for SB600. It was tested (read, write, verify) with an ASUS M3A-H/HDMI which contains a Macronix MX25L8005. Corresponding to flashrom svn r361 and coreboot v2 svn r3799. Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Acked-by: Peter Stuge <peter@stuge.se>
* Fix compilation of r3797 with gcc-4.3.2Peter Stuge2008-12-051-1/+1
| | | | | | | | | Thanks to Niels Ole Salscheider for the problem report. Corresponding to flashrom svn r360 and coreboot v2 svn r3798. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Check if erase succeeds and exit with error on failurePeter Stuge2008-12-051-4/+17
| | | | | | | | | Flashrom used to exit 0 even if erase failed. Not anymore. Corresponding to flashrom svn r359 and coreboot v2 svn r3797. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add RDID/REMS IDs for the following flash chipsCarl-Daniel Hailfinger2008-12-041-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SST_25VF512A_REMS SST_25VF010_REMS SST_25VF020_REMS SST_25VF040_REMS SST_25VF040B_REMS SST_25VF080_REMS SST_25VF080B_REMS SST_25VF032B_REMS SST_26VF016 SST_26VF032 W_25X16 W_25X32 W_25X64 Straight from the data sheets. The REMS IDs help in case the RDID opcode is unavailable (due to opcode lockdown) or unsupported by the chip. Some day, we need to pair probe functions together with IDs. Multiple pairs can exist per chip and duplicating chip definitions does not really make sense. Corresponding to flashrom svn r358 and coreboot v2 svn r3793. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Gcc thinks base could be used uninitialized, so shut it upPeter Stuge2008-12-031-1/+1
| | | | | | | | | Bug from r3791. Corresponding to flashrom svn r357 and coreboot v2 svn r3792. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Fix bug in r3790Peter Stuge2008-12-031-5/+5
| | | | | | | | | | If flashbase was set before probe_flash() it would only ever be used once, for the very first flash chip probe. Corresponding to flashrom svn r356 and coreboot v2 svn r3791. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Replace #ifdefs for sc520 systems by run time probingStefan Reinauer2008-12-034-11/+64
| | | | | | | | | | Fixes #109 Corresponding to flashrom svn r355 and coreboot v2 svn r3790. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Copyright update by Jason Wang for freshly written sb600 codeJason Wang2008-11-291-3/+3
| | | | | | | | Corresponding to flashrom svn r354 and coreboot v2 svn r3782. Signed-off-by: Jason Wang <Qingpei.wang@amd.com> Reviewed-by: Joe, Bao <Zheng.Bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Declare special commands to support the Atmel AT25F512ACarl-Daniel Hailfinger2008-11-281-0/+5
| | | | | | | Corresponding to flashrom svn r353 and coreboot v2 svn r3781. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Do not indicate known-bad functions as untestedCarl-Daniel Hailfinger2008-11-282-6/+11
| | | | | | | | | | | If a chip has any TEST_BAD_* flag set, we don't even list the unsupported functions, giving the user the impression that the unsupported functions are tested. Corresponding to flashrom svn r352 and coreboot v2 svn r3780. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se>
* Add support for the AMD/ATI SB600 southbridge SPI functionalityJason Wang2008-11-287-19/+245
| | | | | | | | | | This has been tested by Uwe Hermann on an RS690/SB600 board. Corresponding to flashrom svn r351 and coreboot v2 svn r3779. Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add SST25VF080B flash chip supportJason Wang2008-11-281-0/+1
| | | | | | | | | | | This is the first chip which uses the infrastructure for alternative erase commands, namely spi_chip_erase_60_c7(). Corresponding to flashrom svn r350 and coreboot v2 svn r3776. Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Flashrom already has the following probe functionsCarl-Daniel Hailfinger2008-11-283-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | - probe_spi_rdid with opcode 0x9f, usually 3 bytes ID - probe_spi_res with opcode 0xab, usually 1 byte ID We are missing the following probe function: - probe_spi_rems with opcode 0x90, usually 2 bytes ID RDID provides best specifity (manufacturer, device class and device) and RES is supported by quite a few old chips. However, RES only returns one byte and there are multiple flash chips with different sizes on the market and all of them have the same RES ID. REMS is from the same age as RES, but it provides a manufacturer and a device ID. It is therefore on par with the probing for parallel flash chips and specific enough. The order in which chips should be detected is as follows: 1. RDID 2. REMS 3. RES Corresponding to flashrom svn r349 and coreboot v2 svn r3775. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se>
* Try RES even if RDID failsCarl-Daniel Hailfinger2008-11-271-7/+5
| | | | | | | | | | | | | | | | | | | The existing check in probe_spi_res() was right for SPI controllers which support all commands, but may not exist. For controllers which support only a subset of commands, it will fail in unexpected ways. Even if a command is supported by the controller, it may be unavailable if the controller is locked down. The new logic checks if RDID could be issued and its return values made sense (not 0xff 0xff 0xff). In that case, RES probing is not performed. Otherwise, we try RES. There is one drawback: If RDID returned unexpected values, we don't issue a RES probe. However, in that case we should try to match RDID anyway. Corresponding to flashrom svn r348 and coreboot v2 svn r3774. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: FENG yu ning <fengyuning1984@gmail.com>
* Add support for 32Mbit SPI flash SST25VF032BTero O Peippola2008-11-241-0/+1
| | | | | | | | | | | Tested on gigabyte m57sli. File util/flashrom/flash.h already had correct ID for that part. Corresponding to flashrom svn r347 and coreboot v2 svn r3769. Signed-off-by: Tero O Peippola <xeropp@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* ichspi: use spi_nbyte_read() instead of running the opcode directlyCarl-Daniel Hailfinger2008-11-181-9/+5
| | | | | | | | | | | | | | Currently flashrom assumes every vendor BIOS shares our view about which SPI opcodes should be placed in which location. Move to a less optimistic implementation and actually use the generic SPI read functions. They're useful for abstracting exactly this stuff and that makes them the preferred choice. Corresponding to flashrom svn r346 and coreboot v2 svn r3758. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Check for failed SPI command executionCarl-Daniel Hailfinger2008-11-182-21/+71
| | | | | | | | | | | | | | | | | | | | | | | Although SPI itself does not have a mechanism to signal command failure, the SPI host may be unable to send a given command over the wire due to security or hardware limitations. The current code ignores these mechanisms completely and simply assumes almost every command succeeds. Complain if SPI command execution fails. Since locked down Intel chipsets (like the one we had problems with earlier) only allow a small subset of commands, find the common subset of commands between the chipset and the ROM in the chip erase case. That is accomplished by the new spi_chip_erase_60_c7() which can be used for chips supporting both 0x60 and 0xc7 chip erase commands. Both parts of the patch address problems seen in the real world. The increased verbosity for the error case will help us diagnose and address problems better. Corresponding to flashrom svn r345 and coreboot v2 svn r3757. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Implement read support for the following Atmel chipsCarl-Daniel Hailfinger2008-11-181-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 I double-checked the data sheets and am confident this will work. Corresponding to flashrom svn r344 and coreboot v2 svn r3756. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* SST39VF020 TEST_OK_ PROBE READ ERASE WRITEMart Raudsepp2008-11-171-1/+1
| | | | | | | | | Tested fully on a ThinCan DBE61A Corresponding to flashrom svn r343 and coreboot v2 svn r3755. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
* The AT25 and AT26 series SPI chips from Atmel are plain EEPROMsCarl-Daniel Hailfinger2008-11-153-2/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AT45 series SPI chips are DataFlash EEPROMs which means they have odd (non-power-of-two) sector sizes, but some of the DataFlash chips can be configured or ordered with power-of-two sector sizes. Add probe support for the following Atmel SPI chips: AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 AT45CS1282 AT45DB011D AT45DB021D AT45DB041D AT45DB081D AT45DB161D AT45DB321C AT45DB321D AT45DB642D Add an explanation why the following chips can't be probed: AT45BR3214B AT45D011 AT45D021A AT45D041A AT45D081A AT45D161 AT45DB011 AT45DB011B AT45DB021A AT45DB021B AT45DB041A AT45DB081A AT45DB161 AT45DB161B AT45DB321 AT45DB321B AT45DB642 Add the ID, but no probing function for this chip: AT25F512A Corresponding to flashrom svn r342 and coreboot v2 svn r3754. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Myles Watson <mylesgw@gmail.com>
* SST39SF040 TEST_OK_ PROBE READ ERASE WRITEPeter Stuge2008-11-081-1/+1
| | | | | | | | | Per report from Mario Rogen. Thanks! Corresponding to flashrom svn r341 and coreboot v2 svn r3736. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se>
* Mark ST M25P16 as fully testedCarl-Daniel Hailfinger2008-11-051-1/+1
| | | | | | | | | This has been confirmed by Stéphan Guilloux. Corresponding to flashrom svn r340 and coreboot v2 svn r3731. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
OpenPOWER on IntegriCloud