diff options
Diffstat (limited to 'it85spi.c')
| -rw-r--r-- | it85spi.c | 18 |
1 files changed, 11 insertions, 7 deletions
@@ -226,6 +226,14 @@ void it85xx_exit_scratch_rom() #endif } +static int it85xx_shutdown(void *data) +{ + msg_pdbg("%s():%d\n", __func__, __LINE__); + it85xx_exit_scratch_rom(); + + return 0; /* FIXME: Should probably return something meaningful */ +} + static int it85xx_spi_common_init(struct superio s) { chipaddr base; @@ -233,6 +241,9 @@ static int it85xx_spi_common_init(struct superio s) msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__, s.vendor); + if (register_shutdown(it85xx_shutdown, NULL)) + return 1; + #ifdef LPC_IO /* Get LPCPNP of SHM. That's big-endian */ sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */ @@ -300,13 +311,6 @@ int it85xx_spi_init(struct superio s) return ret; } -int it85xx_shutdown(void) -{ - msg_pdbg("%s():%d\n", __func__, __LINE__); - it85xx_exit_scratch_rom(); - return 0; -} - /* According to ITE 8502 document, the procedure to follow mode is following: * 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high) * 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI |
