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-rw-r--r--ich_descriptors.h329
1 files changed, 328 insertions, 1 deletions
diff --git a/ich_descriptors.h b/ich_descriptors.h
index 714eda9..34bcc6a 100644
--- a/ich_descriptors.h
+++ b/ich_descriptors.h
@@ -227,22 +227,349 @@ struct ich_desc_master {
};
};
+#ifdef ICH_DESCRIPTORS_FROM_DUMP
+struct ich_desc_north_strap {
+ union {
+ uint32_t STRPs[1]; /* current maximum: ich8 */
+ struct { /* ich8 */
+ struct { /* STRP2 (in the datasheet) */
+ uint32_t MDB :1,
+ :31;
+ };
+ } ich8;
+ };
+};
+
+struct ich_desc_south_strap {
+ union {
+ uint32_t STRPs[16]; /* current maximum: ibex peak */
+ struct { /* ich8 */
+ struct { /* STRP1 */
+ uint32_t ME_DISABLE :1,
+ :6,
+ TCOMODE :1,
+ ASD :7,
+ BMCMODE :1,
+ :3,
+ GLAN_PCIE_SEL :1,
+ GPIO12_SEL :2,
+ SPICS1_LANPHYPC_SEL :1,
+ MESM2SEL :1,
+ :1,
+ ASD2 :7;
+ };
+ } ich8;
+ struct { /* ibex peak */
+ struct { /* STRP0 */
+ uint32_t :1,
+ cs_ss2 :1,
+ :5,
+ SMB_EN :1,
+ SML0_EN :1,
+ SML1_EN :1,
+ SML1FRQ :2,
+ SMB0FRQ :2,
+ SML0FRQ :2,
+ :4,
+ LANPHYPC_GP12_SEL :1,
+ cs_ss1 :1,
+ :2,
+ DMI_REQID_DIS :1,
+ :4,
+ BBBS :2,
+ :1;
+ };
+ struct { /* STRP1 */
+ uint32_t cs_ss3 :4,
+ :28;
+ };
+ struct { /* STRP2 */
+ uint32_t :8,
+ MESMASDEN :1,
+ MESMASDA :7,
+ :8,
+ MESMI2CEN :1,
+ MESMI2CA :7;
+ };
+ struct { /* STRP3 */
+ uint32_t :32;
+ };
+ struct { /* STRP4 */
+ uint32_t PHYCON :2,
+ :6,
+ GBEMAC_SMBUS_ADDR_EN :1,
+ GBEMAC_SMBUS_ADDR :7,
+ :1,
+ GBEPHY_SMBUS_ADDR :7,
+ :8;
+ };
+ struct { /* STRP5 */
+ uint32_t :32;
+ };
+ struct { /* STRP6 */
+ uint32_t :32;
+ };
+ struct { /* STRP7 */
+ uint32_t MESMA2UDID_VENDOR :16,
+ MESMA2UDID_DEVICE :16;
+ };
+ struct { /* STRP8 */
+ uint32_t :32;
+ };
+ struct { /* STRP9 */
+ uint32_t PCIEPCS1 :2,
+ PCIEPCS2 :2,
+ PCIELR1 :1,
+ PCIELR2 :1,
+ DMILR :1,
+ :1,
+ PHY_PCIEPORTSEL :3,
+ PHY_PCIE_EN :1,
+ :20;
+ };
+ struct { /* STRP10 */
+ uint32_t :1,
+ ME_BOOT_FLASH :1,
+ cs_ss5 :1,
+ VE_EN :1,
+ :4,
+ MMDDE :1,
+ MMADDR :7,
+ cs_ss7 :1,
+ :1,
+ ICC_SEL :3,
+ MER_CL1 :1,
+ :10;
+ };
+ struct { /* STRP11 */
+ uint32_t SML1GPAEN :1,
+ SML1GPA :7,
+ :16,
+ SML1I2CAEN :1,
+ SML1I2CA :7;
+ };
+ struct { /* STRP12 */
+ uint32_t :32;
+ };
+ struct { /* STRP13 */
+ uint32_t :32;
+ };
+ struct { /* STRP14 */
+ uint32_t :8,
+ VE_EN2 :1,
+ :5,
+ VE_BOOT_FLASH :1,
+ :1,
+ BW_SSD :1,
+ NVMHCI_EN :1,
+ :14;
+ };
+ struct { /* STRP15 */
+ uint32_t :3,
+ cs_ss6 :2,
+ :1,
+ IWL_EN :1,
+ :1,
+ t209min :2,
+ :22;
+ };
+ } ibex;
+ struct { /* cougar point */
+ struct { /* STRP0 */
+ uint32_t :1,
+ cs_ss1 :1,
+ :5,
+ SMB_EN :1,
+ SML0_EN :1,
+ SML1_EN :1,
+ SML1FRQ :2,
+ SMB0FRQ :2,
+ SML0FRQ :2,
+ :4,
+ LANPHYPC_GP12_SEL :1,
+ LINKSEC_DIS :1,
+ :2,
+ DMI_REQID_DIS :1,
+ :4,
+ BBBS :2,
+ :1;
+ };
+ struct { /* STRP1 */
+ uint32_t cs_ss3 :4,
+ :4,
+ cs_ss2 :1,
+ :28;
+ };
+ struct { /* STRP2 */
+ uint32_t :8,
+ MESMASDEN :1,
+ MESMASDA :7,
+ MESMMCTPAEN :1,
+ MESMMCTPA :7,
+ MESMI2CEN :1,
+ MESMI2CA :7;
+ };
+ struct { /* STRP3 */
+ uint32_t :32;
+ };
+ struct { /* STRP4 */
+ uint32_t PHYCON :2,
+ :6,
+ GBEMAC_SMBUS_ADDR_EN :1,
+ GBEMAC_SMBUS_ADDR :7,
+ :1,
+ GBEPHY_SMBUS_ADDR :7,
+ :8;
+ };
+ struct { /* STRP5 */
+ uint32_t :32;
+ };
+ struct { /* STRP6 */
+ uint32_t :32;
+ };
+ struct { /* STRP7 */
+ uint32_t MESMA2UDID_VENDOR :16,
+ MESMA2UDID_DEVICE :16;
+ };
+ struct { /* STRP8 */
+ uint32_t :32;
+ };
+ struct { /* STRP9 */
+ uint32_t PCIEPCS1 :2,
+ PCIEPCS2 :2,
+ PCIELR1 :1,
+ PCIELR2 :1,
+ DMILR :1,
+ cs_ss4 :1,
+ PHY_PCIEPORTSEL :3,
+ PHY_PCIE_EN :1,
+ :2,
+ SUB_DECODE_EN :1,
+ :7,
+ PCHHOT_SML1ALERT_SEL :1,
+ :9;
+ };
+ struct { /* STRP10 */
+ uint32_t :1,
+ ME_BOOT_FLASH :1,
+ :6,
+ MDSMBE_EN :1,
+ MDSMBE_ADD :7,
+ :2,
+ ICC_SEL :3,
+ MER_CL1 :1,
+ ICC_PRO_SEL :1,
+ Deep_SX_EN :1,
+ ME_DBG_LAN :1,
+ :7;
+ };
+ struct { /* STRP11 */
+ uint32_t SML1GPAEN :1,
+ SML1GPA :7,
+ :16,
+ SML1I2CAEN :1,
+ SML1I2CA :7;
+ };
+ struct { /* STRP12 */
+ uint32_t :32;
+ };
+ struct { /* STRP13 */
+ uint32_t :32;
+ };
+ struct { /* STRP14 */
+ uint32_t :32;
+ };
+ struct { /* STRP15 */
+ uint32_t cs_ss6 :6,
+ IWL_EN :1,
+ cs_ss5 :2,
+ :4,
+ SMLINK1_THERM_SEL :1,
+ SLP_LAN_GP29_SEL :1,
+ :16;
+ };
+ struct { /* STRP16 */
+ uint32_t :32;
+ };
+ struct { /* STRP17 */
+ uint32_t ICML :1,
+ cs_ss7 :1,
+ :30;
+ };
+ } cougar;
+ };
+};
+
+struct ich_desc_upper_map {
+ union {
+ uint32_t FLUMAP1; /* Flash Upper Map 1 */
+ struct {
+ uint32_t VTBA :8, /* ME VSCC Table Base Address */
+ VTL :8, /* ME VSCC Table Length */
+ :16;
+ };
+ };
+ struct {
+ union { /* JEDEC-ID Register */
+ uint32_t JID;
+ struct {
+ uint32_t vid :8, /* Vendor ID */
+ cid0 :8, /* Component ID 0 */
+ cid1 :8, /* Component ID 1 */
+ :8;
+ };
+ };
+ union { /* Vendor Specific Component Capabilities */
+ uint32_t VSCC;
+ struct {
+ uint32_t ubes :2, /* Upper Block/Sector Erase Size */
+ uwg :1, /* Upper Write Granularity */
+ uwsr :1, /* Upper Write Status Required */
+ uwews :1, /* Upper Write Enable on Write Status */
+ :3,
+ ueo :8, /* Upper Erase Opcode */
+ lbes :2, /* Lower Block/Sector Erase Size */
+ lwg :1, /* Lower Write Granularity */
+ lwsr :1, /* Lower Write Status Required */
+ lwews :1, /* Lower Write Enable on Write Status */
+ :3,
+ leo :16; /* Lower Erase Opcode */
+ };
+ };
+ } vscc_table[128];
+};
+#endif /* ICH_DESCRIPTORS_FROM_DUMP */
+
struct ich_descriptors {
struct ich_desc_content content;
struct ich_desc_component component;
struct ich_desc_region region;
struct ich_desc_master master;
+#ifdef ICH_DESCRIPTORS_FROM_DUMP
+ struct ich_desc_north_strap north;
+ struct ich_desc_south_strap south;
+ struct ich_desc_upper_map upper;
+#endif /* ICH_DESCRIPTORS_FROM_DUMP */
};
-void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc);
+void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc);
void prettyprint_ich_descriptor_content(const struct ich_desc_content *content);
void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc);
void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc);
void prettyprint_ich_descriptor_master(const struct ich_desc_master *master);
+#ifdef ICH_DESCRIPTORS_FROM_DUMP
+
+void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap);
+void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc);
+int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struct ich_descriptors *desc);
+
+#else /* ICH_DESCRIPTORS_FROM_DUMP */
+
int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc);
int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx);
+#endif /* ICH_DESCRIPTORS_FROM_DUMP */
#endif /* __ICH_DESCRIPTORS_H__ */
#endif /* defined(__i386__) || defined(__x86_64__) */
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