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-rw-r--r--flashchips.c36
-rw-r--r--flashchips.h51
2 files changed, 57 insertions, 30 deletions
diff --git a/flashchips.c b/flashchips.c
index 946e4fc..35b9a5d 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -3138,10 +3138,10 @@ struct flashchip flashchips[] = {
{
.vendor = "Intel",
- .name = "28F001BX-B",
+ .name = "28F001BN/BX-B",
.bustype = CHIP_BUSTYPE_PARALLEL,
.manufacture_id = INTEL_ID,
- .model_id = P28F001BXB,
+ .model_id = INTEL_28F001B,
.total_size = 128,
.page_size = 128 * 1024, /* 8k + 2x4k + 112k */
.tested = TEST_UNTESTED,
@@ -3164,10 +3164,10 @@ struct flashchip flashchips[] = {
{
.vendor = "Intel",
- .name = "28F001BX-T",
+ .name = "28F001BN/BX-T",
.bustype = CHIP_BUSTYPE_PARALLEL,
.manufacture_id = INTEL_ID,
- .model_id = P28F001BXT,
+ .model_id = INTEL_28F001T,
.total_size = 128,
.page_size = 128 * 1024, /* 112k + 2x4k + 8k */
.tested = TEST_UNTESTED,
@@ -3190,10 +3190,10 @@ struct flashchip flashchips[] = {
{
.vendor = "Intel",
- .name = "28F002BC-T",
+ .name = "28F002BC/BL/BV/BX-T",
.bustype = CHIP_BUSTYPE_PARALLEL,
.manufacture_id = INTEL_ID,
- .model_id = P28F002BC,
+ .model_id = INTEL_28F002T,
.total_size = 256,
.page_size = 256 * 1024,
.tested = TEST_UNTESTED,
@@ -3217,10 +3217,10 @@ struct flashchip flashchips[] = {
{
.vendor = "Intel",
- .name = "28F004S5",
+ .name = "28F008S3/S5/SC",
.bustype = CHIP_BUSTYPE_PARALLEL,
.manufacture_id = INTEL_ID,
- .model_id = E_28F004S5,
+ .model_id = INTEL_28F004S3,
.total_size = 512,
.page_size = 256,
.tested = TEST_UNTESTED,
@@ -3240,10 +3240,10 @@ struct flashchip flashchips[] = {
{
.vendor = "Intel",
- .name = "28F004BV/BE-B",
+ .name = "28F004B5/BE/BV/BX-B",
.bustype = CHIP_BUSTYPE_PARALLEL,
.manufacture_id = INTEL_ID,
- .model_id = P28F004BB,
+ .model_id = INTEL_28F004B,
.total_size = 512,
.page_size = 128 * 1024, /* maximal block size */
.tested = TEST_UNTESTED,
@@ -3267,10 +3267,10 @@ struct flashchip flashchips[] = {
{
.vendor = "Intel",
- .name = "28F004BV/BE-T",
+ .name = "28F004B5/BE/BV/BX-T",
.bustype = CHIP_BUSTYPE_PARALLEL,
.manufacture_id = INTEL_ID,
- .model_id = P28F004BT,
+ .model_id = INTEL_28F004T,
.total_size = 512,
.page_size = 128 * 1024, /* maximal block size */
.tested = TEST_UNTESTED,
@@ -3294,10 +3294,10 @@ struct flashchip flashchips[] = {
{
.vendor = "Intel",
- .name = "28F400BV/CV/CE-B",
+ .name = "28F400BV/BX/CE/CV-B",
.bustype = CHIP_BUSTYPE_PARALLEL,
.manufacture_id = INTEL_ID,
- .model_id = P28F400BB,
+ .model_id = INTEL_28F400B,
.total_size = 512,
.page_size = 128 * 1024, /* maximal block size */
.feature_bits = FEATURE_ADDR_SHIFTED,
@@ -3322,10 +3322,10 @@ struct flashchip flashchips[] = {
{
.vendor = "Intel",
- .name = "28F400BV/CV/CE-T",
+ .name = "28F400BV/BX/CE/CV-T",
.bustype = CHIP_BUSTYPE_PARALLEL,
.manufacture_id = INTEL_ID,
- .model_id = P28F400BT,
+ .model_id = INTEL_28F400T,
.total_size = 512,
.page_size = 128 * 1024, /* maximal block size */
.feature_bits = FEATURE_ADDR_SHIFTED,
@@ -3353,7 +3353,7 @@ struct flashchip flashchips[] = {
.name = "82802AB",
.bustype = CHIP_BUSTYPE_FWH,
.manufacture_id = INTEL_ID,
- .model_id = I_82802AB,
+ .model_id = INTEL_82802AB,
.total_size = 512,
.page_size = 64 * 1024,
.feature_bits = FEATURE_REGISTERMAP,
@@ -3377,7 +3377,7 @@ struct flashchip flashchips[] = {
.name = "82802AC",
.bustype = CHIP_BUSTYPE_FWH,
.manufacture_id = INTEL_ID,
- .model_id = I_82802AC,
+ .model_id = INTEL_82802AC,
.total_size = 1024,
.page_size = 64 * 1024,
.feature_bits = FEATURE_REGISTERMAP,
diff --git a/flashchips.h b/flashchips.h
index dbe6d93..414d220 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -296,18 +296,45 @@
#define IMT_IM29F004T 0xAF
#define INTEL_ID 0x89 /* Intel */
-#define I_82802AB 0xAD
-#define I_82802AC 0xAC
-#define E_28F004S5 0xA7
-#define E_28F008S5 0xA6
-#define E_28F016S5 0xAA
-#define P28F001BXT 0x94 /* 28F001BX-T */
-#define P28F001BXB 0x95 /* 28F001BX-B */
-#define P28F002BC 0x7C /* 28F002BC-T */
-#define P28F004BT 0x78 /* 28F004BV/BE-T */
-#define P28F004BB 0x79 /* 28F004BV/BE-B */
-#define P28F400BT 0x70 /* 28F400BV/CV/CE-T */
-#define P28F400BB 0x71 /* 28F400BV/CV/CE-B */
+#define INTEL_28F320J5 0x14
+#define INTEL_28F640J5 0x15
+#define INTEL_28F320J3 0x16
+#define INTEL_28F640J3 0x17
+#define INTEL_28F128J3 0x18
+#define INTEL_28F256J3 0x1D
+#define INTEL_28F400T 0x70 /* 28F400BV/BX/CE/CV-T */
+#define INTEL_28F400B 0x71 /* 28F400BV/BX/CE/CV-B */
+#define INTEL_28F200T 0x74 /* 28F200BL/BV/BX/CV-T */
+#define INTEL_28F200B 0x75 /* 28F200BL/BV/BX/CV-B */
+#define INTEL_28F004T 0x78 /* 28F004B5/BE/BV/BX-T */
+#define INTEL_28F004B 0x79 /* 28F004B5/BE/BV/BX-B */
+#define INTEL_28F002T 0x7C /* 28F002BC/BL/BV/BX-T */
+#define INTEL_28F002B 0x7D /* 28F002BL/BV/BX-B */
+#define INTEL_28F001T 0x94 /* 28F001BN/BX-T */
+#define INTEL_28F001B 0x95 /* 28F001BN/BX-B */
+#define INTEL_28F008T 0x98 /* 28F008BE/BV-T */
+#define INTEL_28F008B 0x99 /* 28F008BE/BV-B */
+#define INTEL_28F800T 0x9C /* 28F800B5/BV/CE/CV-T */
+#define INTEL_28F800B 0x9D /* 28F800B5/BV/CE/CV-B */
+#define INTEL_28F016SV 0xA0 /* 28F016SA/SV */
+#define INTEL_28F008SA 0xA2
+#define INTEL_28F008S3 0xA6 /* 28F008S3/S5/SC */
+#define INTEL_28F004S3 0xA7 /* 28F008S3/S5/SC */
+#define INTEL_28F016XS 0xA8
+#define INTEL_28F016S3 0xAA /* 28F016S3/S5/SC */
+#define INTEL_82802AC 0xAC
+#define INTEL_82802AB 0xAD
+#define INTEL_28F010 0xB4
+#define INTEL_28F512 0xB8
+#define INTEL_28F256A 0xB9
+#define INTEL_28F020 0xBD
+#define INTEL_28F016B3T 0xD0 /* 28F016B3-T */
+#define INTEL_28F016B3B 0xD1 /* 28F016B3-B */
+#define INTEL_28F008B3T 0xD2 /* 28F008B3-T */
+#define INTEL_28F008B3B 0xD3 /* 28F008B3-B */
+#define INTEL_28F004B3T 0xD4 /* 28F004B3-T */
+#define INTEL_28F004B3B 0xD5 /* 28F004B3-B */
+
#define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */
#define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */
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